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Wed, 05 Aug 2026 05:20:31 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, tan.siewert@9elements.com, linux-serial@vger.kernel.org, mfd@lists.linux.dev, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v5 1/6] dt-bindings: serial: 8250: aspeed: add ast2600 and aspeed,vuart-over-pci Date: Wed, 5 Aug 2026 14:19:48 +0200 Message-ID: <52d5bce1cf8ec3ff0b27e7313655cf7ffa2236b5.1785932211.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The ASPEED AST2600 has 2 Virtual UARTs accessible over PCI. The ASPEED AST2600 can be used as a PCI device. 2 Virtual UART can be exposed to the host via this PCI device. These are 8250-compatible register sets and can be used to have UART communication between the PCI BMC and the host. This boolean can be set to specify if a VUART is used over PCI. A VUART over PCI needs a syscon phandle. The syscon gives a regmap to the SCU, which is used to set the enable bits of the PCI device. On the aspeed's chips, the clocks phandle already points at the SCU node. But deriving the regmap from the clock provider would misuse the clocks binding. An explicit syscon phandle states the dependency directly. Signed-off-by: Gr=C3=A9goire Layet Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/serial/8250.yaml | 42 ++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documenta= tion/devicetree/bindings/serial/8250.yaml index bb7b9c87a807..8dd4b7af0c0d 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -18,12 +18,34 @@ allOf: - aspeed,lpc-io-reg - required: - aspeed,lpc-interrupts + then: + properties: + compatible: + contains: + enum: + - aspeed,ast2500-vuart + - aspeed,ast2600-vuart + - if: + anyOf: - required: - aspeed,sirq-polarity-sense then: properties: compatible: const: aspeed,ast2500-vuart + - if: + required: + - aspeed,vuart-over-pci + then: + required: + - aspeed,scu-syscon + properties: + compatible: + contains: + const: aspeed,ast2600-vuart + else: + properties: + aspeed,scu-syscon: false - if: properties: compatible: @@ -106,6 +128,9 @@ properties: - const: ns16850 - const: aspeed,ast2400-vuart - const: aspeed,ast2500-vuart + - items: + - const: aspeed,ast2600-vuart + - const: aspeed,ast2500-vuart - const: intel,xscale-uart - const: mrvl,pxa-uart - const: nuvoton,wpcm450-uart @@ -297,7 +322,8 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array maxItems: 1 description: | - The VUART LPC address. Only applicable to aspeed,ast2500-vuart. + The VUART LPC address. Only applicable to aspeed,ast2500-vuart and + aspeed,ast2600-vuart. =20 aspeed,lpc-interrupts: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -306,7 +332,19 @@ properties: description: | A 2-cell property describing the VUART SIRQ number and SIRQ polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only - applicable to aspeed,ast2500-vuart. + applicable to aspeed,ast2500-vuart and aspeed,ast2600-vuart. + + aspeed,vuart-over-pci: + type: boolean + description: + Enable the VUART over the BMC PCI device. Only applicable to + aspeed,ast2600-vuart. + + aspeed,scu-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the SCU syscon, used to enable the VUART over the BMC PCI + device. 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Wed, 05 Aug 2026 05:20:35 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, tan.siewert@9elements.com, linux-serial@vger.kernel.org, mfd@lists.linux.dev, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v5 2/6] serial: 8250_aspeed_vuart: add aspeed,ast2600-vuart compatible string Date: Wed, 5 Aug 2026 14:19:49 +0200 Message-ID: <56aa0a5e26ea76e4f9a27ed059d2b05bec9cffa5.1785932211.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Make the driver compatible with the ast2600-vuart. Enable specific configuration for the AST2600. Signed-off-by: Gr=C3=A9goire Layet Reviewed-by: Tan Siewert --- drivers/tty/serial/8250/8250_aspeed_vuart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/seri= al/8250/8250_aspeed_vuart.c index 26fc0464f1cc..6afa2f4057e1 100644 --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c @@ -560,6 +560,7 @@ static void aspeed_vuart_remove(struct platform_device = *pdev) static const struct of_device_id aspeed_vuart_table[] =3D { { .compatible =3D "aspeed,ast2400-vuart" }, { .compatible =3D "aspeed,ast2500-vuart" }, + { .compatible =3D "aspeed,ast2600-vuart" }, { }, }; MODULE_DEVICE_TABLE(of, aspeed_vuart_table); --=20 2.54.0 From nobody Mon Aug 24 04:16:56 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD10C42D761 for ; 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Wed, 05 Aug 2026 05:20:38 -0700 (PDT) Received: from gregwork.sec.9e.network ([188.111.3.154]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49949f68f95sm196663515e9.0.2026.08.05.05.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:20:38 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, tan.siewert@9elements.com, linux-serial@vger.kernel.org, mfd@lists.linux.dev, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v5 3/6] serial: 8250_aspeed_vuart: add VUART over PCI Date: Wed, 5 Aug 2026 14:19:50 +0200 Message-ID: <84efc6b23b79e901245e9ed7f58546bef6089530.1785932211.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enable the VUART over PCI for the AST2600. Activate it only if the 'aspeed,vuart-over-pci' property flag is set on an 'ast2600-vuart' compatible node. The AST2600 has 2 VUART that are usable over PCI. These are already defined as the VUART3 and VUART4 in the 'aspeed-g6.dtsi'. Sets the BMC PCI device enable bits, sets the PCI class code to unassgined/device specific, and configures MSI interrupts. There is no disable function. Removing this driver should not disable the BMC PCI device, as other drivers could use it. However, if all the drivers using it are removed, the BMC PCI device will still be activated, which is not ideal. But in reality, this is not a use case for a BMC, the drivers will never be removed. This is useful on PCIe BMC expansion cards that use the AST2600, such as the ASUS Kommando IPMI Expansion Card. Register initialisation taken from ASPEED 6.18 Kernel SDK. Add return code checks to each register write. Simplify the code and add macros. The ASPEED_SCUC24 regmap update is missing a macro for 'BIT(14)'. I was unable to determine the purpose of this bit. In the AST2600 A3 datasheet it is marked as 'reserved'. It is only used on the other revision. As I only have the AST2600A3, I was unable to try this code path. This BIT14 was set in the ASPEED SDK so I kept it. I can remove it and the untested path if necessary. Signed-off-by: Jacky Chou Signed-off-by: aspeedyh Signed-off-by: Gr=C3=A9goire Layet Reviewed-by: Tan Siewert --- Change from v4 to v5: - Change bit 14 to RESERVED macro - Changed ordering of macros - use FIELD_PREP macro --- drivers/tty/serial/8250/8250_aspeed_vuart.c | 91 +++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/seri= al/8250/8250_aspeed_vuart.c index 6afa2f4057e1..2360d37139bf 100644 --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c @@ -32,6 +32,28 @@ #define ASPEED_VUART_DEFAULT_SIRQ 4 #define ASPEED_VUART_DEFAULT_SIRQ_POLARITY IRQ_TYPE_LEVEL_LOW =20 +#define ASPEED_SCU_SILICON_REVISION_ID 0x04 +#define AST2600A3_REVISION_ID 0x05030303 + +#define ASPEED_SCU_PCIE_CONF_CTRL 0xC20 +#define SCU_PCIE_CONF_BMC_DEV_EN BIT(8) +#define SCU_PCIE_CONF_BMC_DEV_EN_MMIO BIT(9) +#define SCU_PCIE_CONF_BMC_DEV_EN_MSI BIT(11) +#define SCU_PCIE_CONF_BMC_DEV_EN_IRQ BIT(13) +#define SCU_PCIE_CONF_BMC_DEV_EN_PCIE_BUS_MASTER BIT(14) +#define SCU_PCIE_CONF_BMC_DEV_EN_E2L BIT(15) +#define SCU_PCIE_CONF_BMC_DEV_EN_LPC_DECODE BIT(21) + +#define ASPEED_SCUC24 0xC24 +#define ASPEED_SCUC24_MSI_ROUTING_MASK GENMASK(11, 10) +#define ASPEED_SCUC24_MSI_ROUTING_PCIE2LPC_PCIDEV1 \ + FIELD_PREP(ASPEED_SCUC24_MSI_ROUTING_MASK, 2) +#define ASPEED_SCUC24_RESERVED_14 BIT(14) +#define ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN BIT(17) +#define ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN BIT(18) + +#define ASPEED_SCU_BMC_DEV_CLASS 0xC68 + struct aspeed_vuart { struct device *dev; int line; @@ -412,6 +434,66 @@ static int aspeed_vuart_map_irq_polarity(u32 dt) } } =20 +static int aspeed_ast2600_vuart_over_pci_set_enabled(struct platform_devic= e *pdev) +{ + struct device *dev =3D &pdev->dev; + u32 silicon_revision_id; + struct regmap *scu; + int rc; + + u32 pcie_config_ctl =3D SCU_PCIE_CONF_BMC_DEV_EN_IRQ | + SCU_PCIE_CONF_BMC_DEV_EN_MMIO | + SCU_PCIE_CONF_BMC_DEV_EN_MSI | + SCU_PCIE_CONF_BMC_DEV_EN_PCIE_BUS_MASTER | + SCU_PCIE_CONF_BMC_DEV_EN_E2L | + SCU_PCIE_CONF_BMC_DEV_EN_LPC_DECODE | + SCU_PCIE_CONF_BMC_DEV_EN; + + scu =3D syscon_regmap_lookup_by_phandle(dev->of_node, "aspeed,scu-syscon"= ); + if (IS_ERR(scu)) { + dev_err(dev, "failed to find SCU regmap\n"); + return PTR_ERR(scu); + } + + /* update class code to be an Unassigned/device specific class device */ + if (regmap_write(scu, ASPEED_SCU_BMC_DEV_CLASS, 0xff000000)) { + dev_err(dev, "could not set PCIe class code\n"); + return -EIO; + } + + if (regmap_update_bits(scu, ASPEED_SCU_PCIE_CONF_CTRL, + pcie_config_ctl, pcie_config_ctl)) { + dev_err(dev, "could not set PCIe configuration\n"); + return -EIO; + } + + if (regmap_read(scu, ASPEED_SCU_SILICON_REVISION_ID, &silicon_revision_id= )) { + dev_err(dev, "could not read silicon revision\n"); + return -EIO; + } + + if (silicon_revision_id =3D=3D AST2600A3_REVISION_ID) + rc =3D regmap_update_bits(scu, ASPEED_SCUC24, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN | + ASPEED_SCUC24_MSI_ROUTING_MASK, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN | + ASPEED_SCUC24_MSI_ROUTING_PCIE2LPC_PCIDEV1); + else + rc =3D regmap_update_bits(scu, ASPEED_SCUC24, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN | + ASPEED_SCUC24_RESERVED_14 | + ASPEED_SCUC24_MSI_ROUTING_MASK, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN | + ASPEED_SCUC24_RESERVED_14 | + ASPEED_SCUC24_MSI_ROUTING_PCIE2LPC_PCIDEV1); + if (rc) { + dev_err(dev, "could not set PCI device 1 MSI interrupt routing\n"); + return -EIO; + } + + return 0; +} + static int aspeed_vuart_probe(struct platform_device *pdev) { struct of_phandle_args sirq_polarity_sense_args; @@ -540,6 +622,15 @@ static int aspeed_vuart_probe(struct platform_device *= pdev) aspeed_vuart_set_host_tx_discard(vuart, true); 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Wed, 05 Aug 2026 05:20:42 -0700 (PDT) Received: from gregwork.sec.9e.network ([188.111.3.154]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49949f68f95sm196663515e9.0.2026.08.05.05.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:20:42 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= , Tan Siewert Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, linux-serial@vger.kernel.org, mfd@lists.linux.dev, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v5 4/6] soc: mfd: add ASPEED AST2600 PCIe BMC device driver Date: Wed, 5 Aug 2026 14:19:51 +0200 Message-ID: <51db5e5bb5bf44dd5ab893b8d547291f04e1d3c7.1785932211.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for UART over PCIe between ASPEED AST2600 BMC and host. This is the host-side driver. Based on ASPEED 6.18 Kernel SDK and trimmed down and changed to MFD driver. The AST2600 has two 8250-compatible register set usable over PCIe. These act as two UARTs. As there is only a FIFO internally between both ends, they are called Virtual UARTs. This patch adds both VUARTs as plat_serial8250_port. This is the core driver in charge of setting up MSI interrupts. It doesn't bind the whole PCIe resource to allow each sub-driver to bind the needed addresses. This is not added as a PCI 8250 UART device, but as a MFD driver, as this host driver can be expanded upon for IPMI over KCS. It can also be used in the future for custom BMC<->host communication with shared memory and doorbell. This host module should be the entry point for setting up all features related to an AST2600 present on the PCI bus. Notes on the implementation: The host can't detect the VUART addresses, so they are forced to 0x3f8 and 0x2f8, as in the initial ASPEED driver. The MSI vector index of VUART2 has been changed from 15 to 17. The index 15 used in the initial driver was not working. Tested: Data path in both direction is tested on both VUARTs. Signed-off-by: Jacky Chou Signed-off-by: aspeedyh Signed-off-by: Gr=C3=A9goire Layet --- MAINTAINERS | 6 ++ drivers/mfd/Kconfig | 12 ++++ drivers/mfd/Makefile | 2 + drivers/mfd/aspeed-pci-core.c | 120 ++++++++++++++++++++++++++++++++++ 4 files changed, 140 insertions(+) create mode 100644 drivers/mfd/aspeed-pci-core.c diff --git a/MAINTAINERS b/MAINTAINERS index 4016b3db13af..6afe1b8c6555 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4011,6 +4011,12 @@ S: Maintained F: Documentation/devicetree/bindings/crypto/aspeed,* F: drivers/crypto/aspeed/ =20 +ASPEED PCI BMC DEVICE DRIVER +M: Gr=C3=A9goire Layet +M: Tan Siewert +S: Maintained +F: drivers/mfd/aspeed-pci-core.c + ASPEED PECI CONTROLLER M: Iwona Winiarska L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 763ce6a34782..dd780f72d169 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2573,5 +2573,17 @@ config MFD_MAX7360 additional drivers must be enabled in order to use the functionality of the device. =20 +config MFD_ASPEED_PCI_BMC_DEVICE + tristate "ASPEED BMC PCIe device" + depends on PCI + select MFD_CORE + help + Host-side driver for the ASPEED AST2600 BMC PCIe device found on + BMC expansion cards. Exposes two 8250-compatible VUART + ports. + + If unsure, say N. Choose M here if this machine has an + AST2600-based BMC expansion card on its PCIe bus. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index dd4bb7e77c33..a364b1b5936b 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -303,3 +303,5 @@ obj-$(CONFIG_MFD_RSMU_SPI) +=3D rsmu_spi.o rsmu_core.o obj-$(CONFIG_MFD_UPBOARD_FPGA) +=3D upboard-fpga.o =20 obj-$(CONFIG_MFD_LOONGSON_SE) +=3D loongson-se.o + +obj-$(CONFIG_MFD_ASPEED_PCI_BMC_DEVICE) +=3D aspeed-pci-core.o diff --git a/drivers/mfd/aspeed-pci-core.c b/drivers/mfd/aspeed-pci-core.c new file mode 100644 index 000000000000..ad6732133ec5 --- /dev/null +++ b/drivers/mfd/aspeed-pci-core.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (C) ASPEED Technology Inc. + +#include +#include +#include +#include +#include +#include +#include + +#define ASPEED_BMC_MULTI_MSI 32 +#define ASPEED_BMC_PCI_DEVICE_ID 0x2402 +#define ASPEED_BMC_REVISION_AST2700 0x27 +#define ASPEED_BMC_VUART 2 + +#define DRIVER_NAME "ast2600-pci-core" + +static const unsigned int vuart_msi_index[ASPEED_BMC_VUART] =3D { 16, 17 }; +static const u16 vuart_port_addr[ASPEED_BMC_VUART] =3D { 0x3f8, 0x2f8 }; + +struct aspeed_pci_bmc_dev { + struct plat_serial8250_port uart[ASPEED_BMC_VUART + 1]; + struct mfd_cell cell; +}; + +static int aspeed_pci_bmc_device_setup_vuart(struct pci_dev *pdev, + struct aspeed_pci_bmc_dev *pci_bmc_dev) +{ + resource_size_t bar =3D pci_resource_start(pdev, 1); + struct plat_serial8250_port *port; + u16 vuart_ioport; + unsigned int i; + + for (i =3D 0; i < ASPEED_BMC_VUART; i++) { + port =3D &pci_bmc_dev->uart[i]; + + /* ASPEED BMC device shift addresses by 2 to the left */ + vuart_ioport =3D vuart_port_addr[i] << 2; + + port->mapbase =3D bar + vuart_ioport; + port->uartclk =3D 115200 * 16; + port->irq =3D pci_irq_vector(pdev, vuart_msi_index[i]); + port->iotype =3D UPIO_MEM32; + port->type =3D PORT_16550A; + port->flags |=3D (UPF_IOREMAP | UPF_FIXED_PORT | UPF_FIXED_TYPE); + port->regshift =3D 2; + } + + pci_bmc_dev->cell =3D (struct mfd_cell) { + .name =3D "serial8250", + .platform_data =3D pci_bmc_dev->uart, + .pdata_size =3D sizeof(pci_bmc_dev->uart), + }; + + return 0; +} + +static void aspeed_bmc_pci_free_irqs(void *pdev) +{ + pci_free_irq_vectors(pdev); +} + +static int aspeed_pci_host_bmc_device_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct device *dev =3D &pdev->dev; + struct aspeed_pci_bmc_dev *pci_bmc_dev; + int rc =3D 0; + + if (pdev->revision =3D=3D ASPEED_BMC_REVISION_AST2700) + return dev_err_probe(dev, -ENODEV, "AST2700 detected but not supported\n= "); + + pci_bmc_dev =3D devm_kzalloc(dev, sizeof(*pci_bmc_dev), GFP_KERNEL); + if (!pci_bmc_dev) + return -ENOMEM; + + rc =3D pcim_enable_device(pdev); + if (rc) + return dev_err_probe(dev, rc, "failed to enable device\n"); + + pci_set_master(pdev); + + rc =3D pci_alloc_irq_vectors(pdev, ASPEED_BMC_MULTI_MSI, ASPEED_BMC_MULTI= _MSI, PCI_IRQ_MSI); + if (rc < 0) + return dev_err_probe(dev, rc, "failed to allocate %d MSI vectors\n", + ASPEED_BMC_MULTI_MSI); + + rc =3D devm_add_action_or_reset(dev, aspeed_bmc_pci_free_irqs, pdev); + if (rc) + return rc; + + aspeed_pci_bmc_device_setup_vuart(pdev, pci_bmc_dev); + + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, + &pci_bmc_dev->cell, 1, &pdev->resource[1], + 0, NULL); +} + +static struct pci_device_id aspeed_bmc_dev_pci_ids[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_ASPEED, ASPEED_BMC_PCI_DEVICE_ID), + .class =3D PCI_CLASS_OTHERS << 16, + .class_mask =3D 0xFFFF00 + }, + { 0 } +}; + +MODULE_DEVICE_TABLE(pci, aspeed_bmc_dev_pci_ids); + +static struct pci_driver aspeed_host_bmc_dev_driver =3D { + .name =3D DRIVER_NAME, + .id_table =3D aspeed_bmc_dev_pci_ids, + .probe =3D aspeed_pci_host_bmc_device_probe, +}; + +module_pci_driver(aspeed_host_bmc_dev_driver); + +MODULE_AUTHOR("Gr=C3=A9goire Layet "); +MODULE_DESCRIPTION("Host-side driver for the ASPEED BMC PCIe device"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Mon Aug 24 04:16:56 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 405F546C838 for ; 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Wed, 05 Aug 2026 05:20:46 -0700 (PDT) Received: from gregwork.sec.9e.network ([188.111.3.154]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49949f68f95sm196663515e9.0.2026.08.05.05.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:20:46 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, tan.siewert@9elements.com, linux-serial@vger.kernel.org, mfd@lists.linux.dev, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v5 5/6] ARM: dts: aspeed: g6: Change vuart compatible string for ast2600 Date: Wed, 5 Aug 2026 14:19:52 +0200 Message-ID: X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the ast2600 compatible string. Make it more precise and enable specific ast2600 properties. Still use the ast2500 compatible string as a fallback. Signed-off-by: Gr=C3=A9goire Layet Reviewed-by: Tan Siewert --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/as= peed/aspeed-g6.dtsi index 56bb3b0444f7..7c02633f2bd6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -707,7 +707,7 @@ emmc: sdhci@1e750100 { }; =20 vuart1: serial@1e787000 { - compatible =3D "aspeed,ast2500-vuart"; + compatible =3D "aspeed,ast2600-vuart", "aspeed,ast2500-vuart"; reg =3D <0x1e787000 0x40>; reg-shift =3D <2>; interrupts =3D ; @@ -717,7 +717,7 @@ vuart1: serial@1e787000 { }; =20 vuart3: serial@1e787800 { - compatible =3D "aspeed,ast2500-vuart"; + compatible =3D "aspeed,ast2600-vuart", "aspeed,ast2500-vuart"; reg =3D <0x1e787800 0x40>; reg-shift =3D <2>; interrupts =3D ; @@ -727,7 +727,7 @@ vuart3: serial@1e787800 { }; =20 vuart2: serial@1e788000 { - compatible =3D "aspeed,ast2500-vuart"; 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Wed, 05 Aug 2026 05:20:49 -0700 (PDT) Received: from gregwork.sec.9e.network ([188.111.3.154]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49949f68f95sm196663515e9.0.2026.08.05.05.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:20:49 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, tan.siewert@9elements.com, linux-serial@vger.kernel.org, mfd@lists.linux.dev, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v5 6/6] ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4 Date: Wed, 5 Aug 2026 14:19:53 +0200 Message-ID: <8d24d424b3504105394055de268e0a11515635a9.1785932211.git.gregoire.layet@9elements.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The VUART 3 and 4 are VUART over PCI. Set this flag to indicate this information. Also set the syscon phandle. Signed-off-by: Gr=C3=A9goire Layet --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/as= peed/aspeed-g6.dtsi index 7c02633f2bd6..fbd7ab6332a1 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -722,7 +722,9 @@ vuart3: serial@1e787800 { reg-shift =3D <2>; interrupts =3D ; clocks =3D <&syscon ASPEED_CLK_APB2>; + aspeed,scu-syscon =3D <&syscon>; no-loopback-test; + aspeed,vuart-over-pci; status =3D "disabled"; }; =20 @@ -742,7 +744,9 @@ vuart4: serial@1e788800 { reg-shift =3D <2>; interrupts =3D ; clocks =3D <&syscon ASPEED_CLK_APB2>; + aspeed,scu-syscon =3D <&syscon>; no-loopback-test; + aspeed,vuart-over-pci; status =3D "disabled"; }; =20 --=20 2.54.0