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Sun, 2 Aug 2026 23:01:55 -0400 From: Jonathan Santos To: , CC: Jonathan Santos , , , , , , Subject: [PATCH v2 1/5] spi: support simultaneous assertion of multiple CS Date: Mon, 3 Aug 2026 00:01:48 -0300 Message-ID: <545ce92de534e90123af6fa1c75768b9482eb686.1785725359.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDAyMyBTYWx0ZWRfX+vGTkrvXwYdO adNL0vda4SvQwy1GUpm4+Zgan6zov+R+0tjA6YWyDRhAbuP5SqnFSXvYw5TgNiIPFo54mzILkPx Re3KzDn4aJ3Xfqk2LB6GqYwd/fm+YLNUMY+PkplqZCUOf26utF/yCLG0Wpmd8DQEZMxAKBgcUuH W2jwYGuw6woHfmty6EByU/xEOC/1wVhkQtXuH1ibqDB2EEM90W+/IOiSOpGXvm08hXPAuOYZBsV QaK55YErjPE/bkBwl5Y54c+NpkYfr0F2gPDk3IA0wSJRcUVbIZjBr38gkLvmNWDyAqAIHhpnA6+ ogbnmXM6Bh6xILTotaySpYrj9oAoS1phzxhqGRFj456TqRmz7hvzkqtuAC76hNQBspEs6vah9C4 7ZVupsLl1FhaNzq0aMXMvx+9ZFza20oz2y9yCkI9Mus4s4YpKquucgVzcEgne7agnKZyOC8ncIs d44iT6hdrwdTD61BgxA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDAyMyBTYWx0ZWRfX/MDiLv8foA2n rF6wLR4E2hcRCukgDzl+pF1hPV2egnWRznZiE4c5mbhwFJOYjWN92EHRCpeDcMB77l52FC5+UKS yUPvsxhZdm1sinB3O75XDpZAx6dmXdjv86VSt8qforfLgkKY+H+W X-Proofpoint-ORIG-GUID: UubqVlN89pBwkxQl7lbK_kZApya2cDtw X-Proofpoint-GUID: UubqVlN89pBwkxQl7lbK_kZApya2cDtw X-Authority-Analysis: v=2.4 cv=QKRYgALL c=1 sm=1 tr=0 ts=6a7004ad cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=k-FQ2K6VbMuEqB_s0bsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030023 Some SPI controllers allow multiple CS lines to be toggled at the same time. The existing code always used CS index 0 when tracking the last active CS in spi_set_cs(), and unconditionally set cs_index_mask to BIT(0) when parsing DT, both forcing the single CS usage. Modify spi_set_cs() to iterate last_cs[] using each logical CS index instead of always reading index 0. Modify of_spi_parse_dt() to build cs_index_mask from all parsed CS entries rather than hardcoding BIT(0), so the controller correctly identifies which CS lines belong to a device when asserting them simultaneously. Board info, ACPI, and ancillary device paths are not updated here. Board info would require an API change to accept an array of CS values and is left for a follow-up when we have a use case for this. Ancillary devices are by design single-CS, so multi-CS is not a current use case for them. ACPI represents the CS as a 64-bit integer with no established convention for encoding multiple CS indices yet, so any extension there would require a separate specification effort. Acked-by: Nuno S=C3=A1 Signed-off-by: Jonathan Santos --- Changes in v2: * Include Summary describind why the other SPI paths were not addressed here. --- drivers/spi/spi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index d9e6b4b87c89..55fb96fea243 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1090,7 +1090,7 @@ static void spi_set_cs(struct spi_device *spi, bool e= nable, bool force) spi->controller->last_cs_index_mask =3D spi->cs_index_mask; for (idx =3D 0; idx < SPI_DEVICE_CS_CNT_MAX; idx++) { if (enable && idx < spi->num_chipselect) - spi->controller->last_cs[idx] =3D spi_get_chipselect(spi, 0); + spi->controller->last_cs[idx] =3D spi_get_chipselect(spi, idx); else spi->controller->last_cs[idx] =3D SPI_INVALID_CS; } @@ -2594,10 +2594,11 @@ static int of_spi_parse_dt(struct spi_controller *c= tlr, struct spi_device *spi, spi_set_chipselect(spi, idx, cs[idx]); =20 /* - * By default spi->chip_select[0] will hold the physical CS number, - * so set bit 0 in spi->cs_index_mask. + * Set cs_index_mask to indicate which logical CS indices are active. + * Each bit corresponds to a logical CS index in the spi->chip_select arr= ay. */ - spi->cs_index_mask =3D BIT(0); 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charset="utf-8" The device name for SPI devices was formatted as ., always using only the first chip-select index, ignoring the remaining CS lines. Change the naming format to .++... so that all active chip-selects are reflected in the device name. Single-CS devices are not affected since the loop only appends extra indices when num_chipselect is greater than one. Signed-off-by: Jonathan Santos --- Changes in v2: * New patch. --- drivers/spi/spi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 55fb96fea243..61423aee1525 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -594,6 +594,8 @@ static void spi_dev_set_name(struct spi_device *spi) { struct device *dev =3D &spi->dev; struct fwnode_handle *fwnode =3D dev_fwnode(dev); + char cs_str[32]; + int cs_len; =20 if (is_acpi_device_node(fwnode)) { dev_set_name(dev, "spi-%s", acpi_dev_name(to_acpi_device_node(fwnode))); @@ -605,8 +607,12 @@ static void spi_dev_set_name(struct spi_device *spi) return; } =20 - dev_set_name(&spi->dev, "%s.%u", dev_name(&spi->controller->dev), - spi_get_chipselect(spi, 0)); + cs_len =3D scnprintf(cs_str, sizeof(cs_str), "%u", spi_get_chipselect(spi= , 0)); + for (int idx =3D 1; idx < spi->num_chipselect; idx++) + cs_len +=3D scnprintf(cs_str + cs_len, sizeof(cs_str) - cs_len, + "+%u", spi_get_chipselect(spi, idx)); + + dev_set_name(&spi->dev, "%s.%s", dev_name(&spi->controller->dev), cs_str); } =20 /* --=20 2.34.1 From nobody Fri Oct 2 09:21:37 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A77B23395F; Mon, 3 Aug 2026 03:02:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785726158; cv=none; b=gW+4QMgNQh4RandvVOXhAebv90TMQMoyju+8ntISuHGe/GGUZRkuMnfNIaVMUkIE9R2oOwfFQZFF0CzwvbE6hwlbs/Eh3qF4rI9qPBy6Apz3qAloFKjVMnqPPRYdZGrdiOPBI5OQNwRAjzQeHApoHiSvJGaKbNbw8lpymHmgh0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785726158; c=relaxed/simple; bh=89VaO+GuejkXaL0nK7MMQZwZAfJXlOlOReouxxIDrAA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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charset="utf-8" The existing spi_new_ancillary_device() creates an ancillary SPI device but does not consider the parent's lane map. In multi-device setups where each sub-device's chip-select is bound to a dedicated data lane, there is no way to bind an ancillary device to an arbitrary lane index. Introduce spi_new_ancillary_device_with_lane() and devm_spi_new_ancillary_device_with_lane(), which accept rx_lane_idx and tx_lane_idx parameters to select a specific lane from the parent's rx_lane_map and tx_lane_map respectively. The resulting ancillary device is registered with a single RX and TX lane, keeping it independent from the other sub-devices sharing the same controller. Signed-off-by: Jonathan Santos --- Changes in v2: * New patch. --- drivers/spi/spi.c | 102 ++++++++++++++++++++++++++++++++++++++++ include/linux/spi/spi.h | 8 ++++ 2 files changed, 110 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 61423aee1525..d41c9392c04e 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2749,6 +2749,72 @@ struct spi_device *spi_new_ancillary_device(struct s= pi_device *spi, } EXPORT_SYMBOL_GPL(spi_new_ancillary_device); =20 +/** + * spi_new_ancillary_device_with_lane() - Register ancillary SPI device bo= und to specific lane + * @spi: Pointer to the main SPI device registering the ancillary= device + * @chip_select: Chip Select of the ancillary device + * @rx_lane_idx: Lane index within the parent's rx_lane_map + * @tx_lane_idx: Lane index within the parent's tx_lane_map + * + * Like spi_new_ancillary_device(), but additionally binds the ancillary d= evice + * to a single lane from the parent's lane map. Use this in multi-device s= etups + * where each sub-device is physically wired to a dedicated CS and a dedic= ated + * data lane. + * + * This may only be called from main SPI device's probe routine. + * + * Return: Pointer to new ancillary device on success; ERR_PTR on failure + */ +struct spi_device *spi_new_ancillary_device_with_lane(struct spi_device *s= pi, + u8 chip_select, + unsigned int rx_lane_idx, + unsigned int tx_lane_idx) +{ + struct spi_controller *ctlr =3D spi->controller; + struct spi_device *ancillary; + int rc; + + ancillary =3D spi_alloc_device(ctlr); + if (!ancillary) { + rc =3D -ENOMEM; + goto err_out; + } + + strscpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias)); + + spi_set_chipselect(ancillary, 0, chip_select); + + ancillary->max_speed_hz =3D spi->max_speed_hz; + ancillary->mode =3D spi->mode; + ancillary->cs_index_mask =3D BIT(0); + + if (rx_lane_idx >=3D spi->num_rx_lanes || tx_lane_idx >=3D spi->num_tx_la= nes) { + rc =3D -EINVAL; + goto err_out; + } + + ancillary->rx_lane_map[0] =3D spi->rx_lane_map[rx_lane_idx]; + ancillary->num_rx_lanes =3D 1; + ancillary->tx_lane_map[0] =3D spi->tx_lane_map[tx_lane_idx]; + ancillary->num_tx_lanes =3D 1; + + WARN_ON(!mutex_is_locked(&ctlr->add_lock)); + + /* Register the new device, passing the parent to skip CS conflict check = */ + rc =3D __spi_add_device(ancillary, spi); + if (rc) { + dev_err(&spi->dev, "failed to register ancillary device\n"); + goto err_out; + } + + return ancillary; + +err_out: + spi_dev_put(ancillary); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_GPL(spi_new_ancillary_device_with_lane); + static void devm_spi_unregister_device(void *spi) { spi_unregister_device(spi); @@ -2789,6 +2855,42 @@ struct spi_device *devm_spi_new_ancillary_device(str= uct spi_device *spi, } EXPORT_SYMBOL_GPL(devm_spi_new_ancillary_device); =20 +/** + * devm_spi_new_ancillary_device_with_lane() - Register managed ancillary = SPI device bound to a lane + * @spi: Pointer to the main SPI device registering the ancillary = device + * @chip_select: Chip Select of the ancillary device + * @rx_lane_idx: Per-device lane index within the parent's rx_lane_map + * @tx_lane_idx: Per-device lane index within the parent's tx_lane_map + * + * Managed version of spi_new_ancillary_device_with_lane(). The ancillary = device + * will be unregistered automatically when the parent SPI device is unregi= stered. + * + * This may only be called from main SPI device's probe routine. + * + * Return: Pointer to new ancillary device on success; ERR_PTR on failure + */ +struct spi_device *devm_spi_new_ancillary_device_with_lane(struct spi_devi= ce *spi, + u8 chip_select, + unsigned int rx_lane_idx, + unsigned int tx_lane_idx) +{ + struct spi_device *ancillary; + int ret; + + ancillary =3D spi_new_ancillary_device_with_lane(spi, chip_select, + rx_lane_idx, tx_lane_idx); + if (IS_ERR(ancillary)) + return ancillary; + + ret =3D devm_add_action_or_reset(&spi->dev, devm_spi_unregister_device, + ancillary); + if (ret) + return ERR_PTR(ret); + + return ancillary; +} +EXPORT_SYMBOL_GPL(devm_spi_new_ancillary_device_with_lane); + #ifdef CONFIG_ACPI struct acpi_spi_lookup { struct spi_controller *ctlr; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 4c285d3ede1d..91c9e2d2e7e3 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -385,6 +385,14 @@ static inline void spi_unregister_driver(struct spi_dr= iver *sdrv) =20 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi,= u8 chip_select); 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Sun, 2 Aug 2026 23:02:37 -0400 From: Jonathan Santos To: , CC: Jonathan Santos , , , , , , Subject: [PATCH v2 4/5] spi: spi-engine-ex: Add support for multi-CS devices Date: Mon, 3 Aug 2026 00:02:29 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDAyMyBTYWx0ZWRfX4tjDlGewoT5i zMz5IIvsLqIiI4KAH4BIH/wS0mEq7zbfCsQrHDGTB7hcECPlR+GPQ+QFl9O8jseqaRe1EbfksPJ fsyuYxhoHeHA+iQx5ty5kOSFd8VBjVsgPU5IdKS0WvWhfjnaiJa0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDAyMyBTYWx0ZWRfX5KFNOPQp8SGD 1SPJ40HtAGllKhcY60MMK759npUhCYnEcn5MxANGs/poYmT0/sjbQxW9HQ9Phlo+imQfCXFw+oZ CumtbWl44CTncDbRQHGrEl1+o5PNA04n+Y7LutD94OlqE1Q8791dbx81inNSzZrVVc3nmgR6vsC Bc4bgnBVlf45cYFHLoysv3C4StajFNCrfIAqCyfGgb1CoNuoWc/JtTX2+OYfeyuezddUjiLha/l p+GsoIriKebWdMrQNMCYdOTKhSfO8Cw1A5JKrhfkwgMl3AcQwfMWH/flljly+7tiTp5wSqJfey1 ZSymkEcV2yo5PLUAT51i+B86LBF+YFyaNdm1SGwQ1MJNizwXHj3d98+lqBkNy5ko7ZYB1l57VFG BoX+ajD9WkS4e37RvqveTuIxe7FDGxMeOl+Yyu4I6BfAa7SsLL9rd/2lzFD2HInSpNNsbpmZ041 x3izX8EL+uh2epZMoIg== X-Authority-Analysis: v=2.4 cv=daWwG3Xe c=1 sm=1 tr=0 ts=6a7004d9 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=uXIjobp8t2wMuQ0fPvqm:22 a=gAnH3GRIAAAA:8 a=ENVVfsUtpBKDjCfSmAkA:9 X-Proofpoint-ORIG-GUID: AowrSaE64hGZqx0p1x_bEysYRjDOe1_A X-Proofpoint-GUID: AowrSaE64hGZqx0p1x_bEysYRjDOe1_A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 bulkscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030023 Content-Type: text/plain; charset="utf-8" The SPI Engine controller only handled the first chip select when asserting CS lines and configuring CS polarity inversion, ignoring additional CS indices present in cs_index_mask. Update spi_engine_gen_cs() to iterate over all set bits in cs_index_mask and toggle each corresponding CS line in the assert mask. Update spi_engine_setup() likewise so that SPI_CS_HIGH polarity is applied to every active CS index rather than only index 0. Set SPI_CONTROLLER_MULTI_CS in the controller flags to reflect the capability to the SPI core. Signed-off-by: Jonathan Santos Acked-by: Nuno S=C3=A1 --- Changes in v2: * Adaptation of the patch "spi: spi-engine-ex: Add support for multi-CS devices" from v1, discarding the per transfer CS mask and keeping the Multi-CS support only. --- drivers/spi/spi-axi-spi-engine.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index 02bbc5d0cfc5..8a2cae81aea6 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -46,6 +46,7 @@ #define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec =20 #define SPI_ENGINE_MAX_NUM_OFFLOADS 32 +#define SPI_ENGINE_MAX_CS 8 =20 #define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + SPI_ENGINE_MAX_NUM_OFFLOA= DS * (x)) #define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + SPI_ENGINE_MAX_NUM_OFFLO= ADS * (x)) @@ -281,10 +282,14 @@ static void spi_engine_gen_sleep(struct spi_engine_pr= ogram *p, bool dry, static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry, struct spi_device *spi, bool assert) { + unsigned long cs_index_mask =3D spi->cs_index_mask; unsigned int mask =3D 0xff; + unsigned int cs_bit; =20 - if (assert) - mask ^=3D BIT(spi_get_chipselect(spi, 0)); + if (assert) { + for_each_set_bit(cs_bit, &cs_index_mask, SPI_ENGINE_MAX_CS) + mask ^=3D BIT(spi_get_chipselect(spi, cs_bit)); + } =20 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(0, mask)); } @@ -886,12 +891,16 @@ static int spi_engine_setup(struct spi_device *device) { struct spi_controller *host =3D device->controller; struct spi_engine *spi_engine =3D spi_controller_get_devdata(host); + unsigned long cs_index_mask =3D device->cs_index_mask; unsigned int reg; + u32 cs_bit; =20 - if (device->mode & SPI_CS_HIGH) - spi_engine->cs_inv |=3D BIT(spi_get_chipselect(device, 0)); - else - spi_engine->cs_inv &=3D ~BIT(spi_get_chipselect(device, 0)); + for_each_set_bit(cs_bit, &cs_index_mask, SPI_ENGINE_MAX_CS) { + if (device->mode & SPI_CS_HIGH) + spi_engine->cs_inv |=3D BIT(spi_get_chipselect(device, cs_bit)); + else + spi_engine->cs_inv &=3D ~BIT(spi_get_chipselect(device, cs_bit)); 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charset="utf-8" The AD7768-1 family is a single-channel ADC, but it is designed to allow connecting multiple devices to the same SPI controller, each on a dedicated CS and data lane, clocked synchronously, and sharing SDO and SCLK. The number of aggregated devices are derived from spi->num_rx_lanes, assuming all parts are single lane. The DRDY pins are combined to trigger the data interrupt when all devices are ready, and since the synchronization pins are tied, they stay in synchrony. To reflect the multidevice setup, IIO channels are dynamically set based on the number of devices. Restrict buffered capture to the all-channels scan mask, since all devices sample in lockstep. Register an ancillary SPI device per lane for individual direct reads, and enable SPI_MULTI_LANE_MODE_STRIPE in offload mode to interleave samples from all lanes into the DMA stream. Since all devices must be in sync, all configurations that affects the sampling rate are unified, so they always have the same sampling frequency. Signed-off-by: Jonathan Santos --- Changes in v2: * New patch. --- drivers/iio/adc/ad7768-1.c | 99 +++++++++++++++++++++++++++++++++----- 1 file changed, 88 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index e9060c1bbe6f..0a34d408c188 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -120,7 +120,8 @@ =20 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 =20 -#define AD7768_MAX_CHANNELS 1 +#define AD7768_MAX_CHANNELS 1 +#define AD7768_MAX_AGGR_DEVICES 4 =20 #define ADAQ7768_PGA_PINS 3 =20 @@ -300,10 +301,12 @@ struct ad7768_chip_info { =20 struct ad7768_state { struct spi_device *spi; + struct spi_device *spi_anc[AD7768_MAX_AGGR_DEVICES]; struct spi_offload *offload; struct spi_offload_trigger *offload_trigger; struct regmap *regmap; struct regmap *regmap24; + struct regmap *regmap24_anc[AD7768_MAX_AGGR_DEVICES]; int vref_uv; struct regulator_dev *vcm_rdev; unsigned int vcm_output_sel; @@ -322,11 +325,12 @@ struct ad7768_state { struct gpio_descs *pga_gpios; struct gpio_desc *gpio_sync_in; struct gpio_desc *gpio_reset; - const char *labels[AD7768_MAX_CHANNELS]; + const char *labels[AD7768_MAX_CHANNELS * AD7768_MAX_AGGR_DEVICES]; struct gpio_chip gpiochip; struct spi_transfer offload_xfer; struct spi_message offload_msg; const struct ad7768_chip_info *chip; + u8 num_devices; bool en_spi_sync; struct mutex pga_lock; /* protect device internal state (PGA) */ /* @@ -335,7 +339,7 @@ struct ad7768_state { */ union { struct { - __be32 chan; + __be32 chan[AD7768_MAX_AGGR_DEVICES]; aligned_s64 timestamp; } scan; __be32 d32; @@ -478,7 +482,7 @@ static int ad7768_set_mode(struct ad7768_state *st, AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode)); } =20 -static int ad7768_scan_direct(struct iio_dev *indio_dev) +static int ad7768_scan_direct(struct iio_dev *indio_dev, unsigned int chan) { struct ad7768_state *st =3D iio_priv(indio_dev); int readval, ret; @@ -492,9 +496,15 @@ static int ad7768_scan_direct(struct iio_dev *indio_de= v) if (!ret) return -ETIMEDOUT; =20 - ret =3D regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); - if (ret) - return ret; + if (st->num_devices > 1) { + ret =3D regmap_read(st->regmap24_anc[chan], AD7768_REG24_ADC_DATA, &read= val); + if (ret) + return ret; + } else { + ret =3D regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); + if (ret) + return ret; + } =20 /* * When the decimation rate is set to x8, the ADC data precision is @@ -989,7 +999,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, if (!iio_device_claim_direct(indio_dev)) return -EBUSY; =20 - ret =3D ad7768_scan_direct(indio_dev); + ret =3D ad7768_scan_direct(indio_dev, chan->channel); =20 iio_device_release_direct(indio_dev); if (ret < 0) @@ -1391,6 +1401,8 @@ static int ad7768_offload_buffer_postenable(struct ii= o_dev *indio_dev) st->offload_xfer.len =3D spi_bpw_to_bytes(scan_type->realbits); st->offload_xfer.bits_per_word =3D scan_type->realbits; st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + if (st->num_devices > 1) + st->offload_xfer.multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); st->offload_msg.offload =3D st->offload; @@ -1694,6 +1706,55 @@ static int ad7768_parse_aaf_gain(struct device *dev,= struct ad7768_state *st) return 0; } =20 +static int ad7768_probe_multidevices(struct iio_dev *indio_dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + struct device *dev =3D indio_dev->dev.parent; + struct iio_chan_spec *channels; + unsigned long *masks; + u8 cs; + int i; + + indio_dev->num_channels =3D st->num_devices * st->chip->num_channels; + channels =3D devm_kcalloc(dev, indio_dev->num_channels, sizeof(*channels)= , GFP_KERNEL); + if (!channels) + return -ENOMEM; + + for (i =3D 0; i < st->num_devices; i++) { + struct iio_chan_spec *chan =3D &channels[i]; + + *chan =3D *st->chip->channel_spec; + chan->channel =3D i; + chan->scan_index =3D i; + } + + indio_dev->channels =3D channels; + + masks =3D devm_kcalloc(dev, st->chip->num_channels + 1, sizeof(*masks), G= FP_KERNEL); + if (!masks) + return -ENOMEM; + + masks[0] =3D GENMASK(st->num_devices - 1, 0); + indio_dev->available_scan_masks =3D masks; + + /* Setup ancillary SPI devices for single device access */ + for (i =3D 0; i < st->num_devices; i++) { + cs =3D spi_get_chipselect(st->spi, i); + st->spi_anc[i] =3D devm_spi_new_ancillary_device_with_lane(st->spi, + cs, i, 0); + if (IS_ERR(st->spi_anc[i])) + return dev_err_probe(dev, PTR_ERR(st->spi_anc[i]), + "failed to register ancillary device\n"); + + st->regmap24_anc[i] =3D devm_regmap_init_spi(st->spi_anc[i], + &ad7768_regmap24_config); + if (IS_ERR(st->regmap24_anc[i])) + return PTR_ERR(st->regmap24_anc[i]); + } + + return 0; +} + static bool ad7768_offload_trigger_match(struct spi_offload_trigger *trigg= er, enum spi_offload_trigger_type type, u64 *args, u32 nargs) @@ -1830,6 +1891,15 @@ static int ad7768_probe(struct spi_device *spi) =20 st->chip =3D spi_get_device_match_data(spi); st->spi =3D spi; + /* + * This family is composed of 1-lane devices, so we assume that each + * lane is bound to a different device. + */ + st->num_devices =3D spi->num_rx_lanes; + if (st->num_devices > AD7768_MAX_AGGR_DEVICES) + return dev_err_probe(&spi->dev, -EINVAL, + "Too many devices (%u), max %d supported\n", + st->num_devices, AD7768_MAX_AGGR_DEVICES); =20 st->regmap =3D devm_regmap_init_spi(spi, &ad7768_regmap_config); if (IS_ERR(st->regmap)) @@ -1853,11 +1923,18 @@ static int ad7768_probe(struct spi_device *spi) =20 st->mclk_freq =3D clk_get_rate(st->mclk); =20 - indio_dev->channels =3D st->chip->channel_spec; - indio_dev->num_channels =3D st->chip->num_channels; indio_dev->name =3D st->chip->name; indio_dev->info =3D &ad7768_info; indio_dev->modes =3D INDIO_DIRECT_MODE; + if (st->num_devices > 1) { + ret =3D ad7768_probe_multidevices(indio_dev); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to configure multidevice\n"); + } else { + indio_dev->channels =3D st->chip->channel_spec; + indio_dev->num_channels =3D st->chip->num_channels; + } =20 /* Register VCM output regulator */ if (st->chip->has_vcm_regulator) { @@ -1889,7 +1966,7 @@ static int ad7768_probe(struct spi_device *spi) return ret; } =20 - ret =3D ad7768_set_channel_label(indio_dev, st->chip->num_channels); + ret =3D ad7768_set_channel_label(indio_dev, st->num_devices); if (ret) return ret; =20 --=20 2.34.1