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charset="utf-8" i.MX8MQ can drive PCIe REF_CLK either from the internal PLL or from an off-chip oscillator. Allow an optional fifth "extref" clock to describe the latter, matching the name already used for i.MX95. Signed-off-by: Rudi Heitbaum --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index e8b8131f5f23..8fb0c919ae57 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -46,7 +46,8 @@ properties: - description: PCIe PHY clock. - description: Additional required clock entry for imx6sx-pcie, imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. - - description: PCIe internal reference clock. + - description: PCIe internal reference clock for imx95-pcie, or the + external reference clock for imx8mq-pcie. - description: PCIe additional external reference clock. =20 clock-names: @@ -173,13 +174,16 @@ allOf: then: properties: clocks: - maxItems: 4 + minItems: 4 + maxItems: 5 clock-names: + minItems: 4 items: - const: pcie - const: pcie_bus - const: pcie_phy - const: pcie_aux + - const: extref # Optional =20 - if: properties: --=20 2.53.0 From nobody Fri Oct 2 10:07:21 2026 Received: from SY2PR01CU004.outbound.protection.outlook.com (mail-australiaeastazon11021099.outbound.protection.outlook.com [40.107.39.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE293AC0D3; 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charset="utf-8" i.MX8MQ has two PCIe REF_CLK sources: an off-chip oscillator and the internal PLL. The driver unconditionally selected the oscillator, which is what the /* TODO: This code assumes external oscillator is being used */ comment refers to. Boards wiring an oscillator to the pad describe it as the "pcie_bus" clock, but nothing in the driver looks that clock up by name, so it does not select anything. Reuse the generic enable_ext_refclk flag, set when an "extref" clock is supplied, to select between the two, as is already done for i.MX95 in commit d8574ce57d76 ("PCI: imx6: Add external reference clock input mode support"). Signed-off-by: Rudi Heitbaum --- drivers/pci/controller/dwc/pci-imx6.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index dcdeba1856f7..5a350b458782 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -445,11 +445,16 @@ static int pcie_phy_write(struct imx_pcie *imx_pcie, = int addr, u16 data) =20 static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) { - /* TODO: This code assumes external oscillator is being used */ + bool ext =3D imx_pcie->enable_ext_refclk; + + /* + * Select the off-chip oscillator as REF_CLK when an "extref" clock is + * supplied, otherwise fall back to the internal PLL. + */ regmap_update_bits(imx_pcie->iomuxc_gpr, imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, - IMX8MQ_GPR_PCIE_REF_USE_PAD); + ext ? IMX8MQ_GPR_PCIE_REF_USE_PAD : 0); /* * Per the datasheet, the PCIE_VPH is suggested to be 1.8V. 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charset="utf-8" Boards feeding PCIe REF_CLK from an off-chip oscillator described it as the "pcie_bus" clock, which the driver never looks up by name and which therefore selects nothing. The oscillator was used only because the driver forced IMX8MQ_GPR_PCIE_REF_USE_PAD unconditionally. Now that the selection follows the "extref" clock, name the oscillator explicitly on every board that depends on it so the behaviour is unchanged. The "pcie_bus" entries are left alone. Endpoint nodes are not touched: they are all disabled and use a separate binding. Signed-off-by: Rudi Heitbaum --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 8 ++++++-- .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 8 ++++++-- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 4 +++- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 8 ++++++-- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 8 ++++++-- 5 files changed, 27 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot= /dts/freescale/imx8mq-evk.dts index e7d87ea81b69..3dc0047cd1de 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -374,7 +374,9 @@ &pcie0 { clocks =3D <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; vph-supply =3D <&vgen5_reg>; supports-clkreq; status =3D "okay"; @@ -402,7 +404,9 @@ &pcie1 { clocks =3D <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie0_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; vpcie-supply =3D <®_pcie1>; vpcie3v3aux-supply =3D <®_pcie1>; vph-supply =3D <&vgen5_reg>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/= arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index d8cf1f27c3ec..8cf6a64db1a7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -247,7 +247,9 @@ &pcie0 { clocks =3D <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; status =3D "okay"; }; =20 @@ -256,7 +258,9 @@ &pcie1 { clocks =3D <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; fsl,max-link-speed =3D <1>; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/ar= m64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 3ae3824be027..bf931d2f3a87 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -199,7 +199,9 @@ &pcie1 { clocks =3D <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch= /arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index 0165f3a25985..761c43db3026 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -97,7 +97,9 @@ &pcie0 { clocks =3D <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&pcieclk 3>, <&pcieclk 2>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcieclk 3>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; status =3D "okay"; }; =20 @@ -109,7 +111,9 @@ &pcie1 { clocks =3D <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcieclk 1>, <&pcieclk 0>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcieclk 1>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm= 64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index c7bbba45f368..31db96adb237 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -551,7 +551,9 @@ &pcie0 { clocks =3D <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; vph-supply =3D <&vgen5_reg>; status =3D "okay"; }; @@ -563,7 +565,9 @@ &pcie1 { clocks =3D <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "extref"; vph-supply =3D <&vgen5_reg>; status =3D "okay"; }; --=20 2.53.0