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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49541eb7372sm3786325e9.13.2026.07.15.12.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 12:09:14 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shawn Guo , Daniel Baluta , Josua Mayer , Alexander Stein , Ernest Van Hoecke , Maud Spierings , Francesco Dolcini , Hugo Villeneuve , Krzysztof Kozlowski Subject: [PATCH v5 1/3] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX8 QuadMax Boards Date: Wed, 15 Jul 2026 21:09:07 +0200 Message-ID: X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add DT compatible strings for Variscite VAR-SOM-MX8 QuadMax SoM and Variscite Symphony development carrier Board. Acked-by: Krzysztof Kozlowski Signed-off-by: Stefano Radaelli --- v4->v5: -=20 v3->v4: -=20 v2->v3: -=20 v1->v2: -=20 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 6237fb2ae50e..532e4308dc46 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1381,6 +1381,12 @@ properties: - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - const: fsl,imx8qm =20 + - description: i.MX8QM Variscite VAR-SOM-MX8 based Boards + items: + - const: variscite,var-som-imx8qm-symphony + - const: variscite,var-som-imx8qm + - const: fsl,imx8qm + - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules items: - enum: --=20 2.47.3 From nobody Sat Jul 25 16:50:44 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E263C43F0AD for ; Wed, 15 Jul 2026 19:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784142571; cv=none; b=MZ2zZMeu4tNmgGouWE8onMe+fFsmOO+iQ5cksEHF8RpLoERKkOhf/AIQSYo5s1koIFWn6auJ6Ud3Kvyufh2BrZAi5UUR1Y44TmxnaQ4sxi4VLwYA9RTV8+QFxCr56MlCrd3joZkPyVzYIs4FUIWDX8W0pQpfjZm+0zgh8t5W/4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784142571; c=relaxed/simple; bh=3O4UxIFO/h5ffJjfrBu+TO3Urd31DIETXrLKFCgY3uU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jkJY/ZQK3GX3DefBmvOPCEcAUPZN2r0wmczBpKQhLc0/ETNXEq9263AkCXWul92nBeY+LZ21kQvJFp61LgLBHfT5n/3KQeZ45WQ62WvRj3s3OCS0hG3yAKCtQDffqRTgk9g9V5OvIOAZw0YPsUVE8I0MEexhCqJhj41LN2pPxA8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=N+WWYTjn; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N+WWYTjn" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-493bfe9f886so31528505e9.0 for ; Wed, 15 Jul 2026 12:09:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784142556; x=1784747356; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fv9umQ6k9AYmo0dKCqNs7HYkNt4I5paAKMEenHsDbUM=; b=N+WWYTjnwo7o7543RnrDT9YO232tEeAbCISIFnztGrQseT/SvPX6MqO9nwFvO8vcY2 5/CQxtU7EqpxtA/pmcnhyGPQjsaq+Y6q4y1UNX5KaXYKXsiUa8qS9s00PD5BeVCXXzT5 WcRXb1SBA5d3WLSm+sizs3WaTuwSgifJISeoCIUYIVJlteGAVpl5q/epVhmamoqbAfI9 gLqKA2bJ7mkZBknZbzZ+L8m5D7v6A8yxDXmqp5+1fICjM75htos+32fDaT0UjZVdHpo9 OdGc9YU7tKO2b0ik0dN5NqMLKT3JA2fqdyJiej2gSD9FV0+BBxT+eEUuESyhULcQv/bD x8lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784142556; x=1784747356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fv9umQ6k9AYmo0dKCqNs7HYkNt4I5paAKMEenHsDbUM=; b=An2QIibMzsaJh8r+4nVIACoD1bWs/+67oZwLZbml9IsP2KCnNu2H2/Ed3tMCmTJfgR RZsJNcNyMUzlk2gDspOrkj+HFVpfSd3jHZVUl1vX6S29HRmiHAOL8ey6rvK+/AAJyyBu odu2oz4M2KkRrXwBHpyFqo+Gy86LDKg//v6lFaum4+BZ27/pkNXb/vHascjoGolFJDrF BPUgx0TpeO+bNh9C/CddvA1D/pdpdfNpySs8CIFgHn43g5q8BvJC+64+Kw3bqsxpIkkl gCxpZBYKkFBWxJeBytOat7KgKjulVO1x2vhtNEF8VOu6e/QGllJ9yO9+XdaF+eEzFSdQ fUTw== X-Gm-Message-State: AOJu0Yy9zFnnsM09WjX2hPCMoTij8QbCz2RbOR86yL55cI0arDa32dg0 hEEr2n27FQO/0Ifv11ROl+LIL3Jmts98oIINlBoBf251ddNxEJiNN1mwUMd1Uw== X-Gm-Gg: AfdE7cmsmzt++smqpxMQQOmglSIru1AoDQs552hQg4Q+6/hdOU7FP4+31RNm1n7jAdb BuXQcnOxRRZ8q629JR05cQdgYxkpowaJio+RECXrK9aCYXB7pum4HNOigKly+nRxaBsaShPSOwa kgup4tEcun85uUSC9WH85cmF0OBzvzt0tlLGa0QZiZ0aBvp54+KTDCEum4ghuv9JDq/LMEok/P/ w1HZmDohdI0zW5980LgR4LHBhqZybM47ivfauIqlZZR0lZvLeXgThRh3WuK1YhmPNZ45eLpPkou nMaKI2/yoBNR9oAThB3VEhde39zcJ86kz5wBR4iAWCft7/tdC5QFzq9UlccTYUhvfh1c/s/QhdY iUUhYxcw5DEWgJf9LfdV6rEmi7Cp0szQMsBPfEidUvJ0SBusMY1/lIIBfJO3jK1daGXCC35Kxra dMcCXM8m5Manw0FXdXmiv/ZNwbaQ1mKFrF653WeMO2vQp7Ea1d5iN42p7seMwloBPBUoUd5VGa+ XltZ0BHC6C16KSODMqwiMNe5CM/OzMseI07 X-Received: by 2002:a05:600c:4e0d:b0:495:39dc:583d with SMTP id 5b1f17b1804b1-4953c150667mr46493555e9.6.1784142555852; Wed, 15 Jul 2026 12:09:15 -0700 (PDT) Received: from Lord-Beerus.station (net-93-144-65-248.cust.dsl.teletu.it. [93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49541eb7372sm3786325e9.13.2026.07.15.12.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 12:09:15 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shawn Guo , Daniel Baluta , Josua Mayer , Alexander Stein , Ernest Van Hoecke , Maud Spierings , Francesco Dolcini , Hugo Villeneuve Subject: [PATCH v5 2/3] arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMax Date: Wed, 15 Jul 2026 21:09:08 +0200 Message-ID: <0dab340bd29e1f4b1fab05a29532cad3177abc7f.1784142385.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite VAR-SOM-MX8 QuadMax system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8 QuadMax MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quad= plus/var-som-mx8/ Signed-off-by: Stefano Radaelli --- v4->v5: - Fix sai7 clock - Fix codec regulator voltage v3->v4: - Fix sai peripherals clocks - Add comment to clarify 1GB variant v2->v3: -=20 v1->v2: - Added non-removable property to usdhc3 - Removed unused fec gpio pinctrl .../boot/dts/freescale/imx8qm-var-som.dtsi | 531 ++++++++++++++++++ 1 file changed, 531 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi b/arch/arm64= /boot/dts/freescale/imx8qm-var-som.dtsi new file mode 100644 index 000000000000..28964de3b080 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite VAR-SOM-MX8 + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-= quadplus/var-som-mx8/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8qm.dtsi" + +/ { + model =3D "Variscite i.MX8QM VAR-SOM-MX8 Module"; + compatible =3D "variscite,var-som-imx8qm", "fsl,imx8qm"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_audio_supply: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "wm8904-supply"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible =3D "regulator-fixed"; + regulator-name =3D "vddio-1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + vdev0vring0: memory@90000000 { + reg =3D <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@90008000 { + reg =3D <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@90010000 { + reg =3D <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@90018000 { + reg =3D <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table0: memory@900ff000 { + reg =3D <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdev2vring0: memory@90100000 { + reg =3D <0 0x90100000 0 0x8000>; + no-map; + }; + + vdev2vring1: memory@90108000 { + reg =3D <0 0x90108000 0 0x8000>; + no-map; + }; + + vdev3vring0: memory@90110000 { + reg =3D <0 0x90110000 0 0x8000>; + no-map; + }; + + vdev3vring1: memory@90118000 { + reg =3D <0 0x90118000 0 0x8000>; + no-map; + }; + + rsc_table1: memory@901ff000 { + reg =3D <0 0x901ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: memory@90400000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x90400000 0 0x100000>; + no-map; + }; + + dsp_reserved: memory@92400000 { + reg =3D <0 0x92400000 0 0x1000000>; + no-map; + }; + + dsp_vdev0vring0: memory@942f0000 { + reg =3D <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: memory@942f8000 { + reg =3D <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: memory@94300000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x94300000 0 0x100000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible =3D "shared-dma-pool"; + /* VAR-SOM-MX8QM doesn't have 1GB variant */ + alloc-ranges =3D <0 0xc0000000 0 0x3c000000>; + size =3D <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + sound-wm8904 { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,name =3D "wm8904-audio"; + simple-audio-card,routing =3D + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets =3D + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai =3D <&esai0>; + }; + }; +}; + +&acm { + status =3D "okay"; +}; + +&asrc0 { + fsl,asrc-rate =3D <48000>; + status =3D "okay"; +}; + +&asrc1 { + fsl,asrc-rate =3D <48000>; + status =3D "okay"; +}; + +&cm41_intmux { + status =3D "okay"; +}; + +&esai0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_esai0>; + assigned-clocks =3D <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents =3D <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates =3D <0>, <786432000>, <49152000>, <12288000>, <49152= 000>; + #sound-dai-cells =3D <0>; + status =3D "okay"; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy0>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@4 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + reset-gpios =3D <&lsio_gpio2 28 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <20000>; + vddio-supply =3D <®_phy_vddio>; + }; + }; +}; + +&gpio0_mipi_csi0 { + status =3D "disabled"; +}; + +&gpio0_mipi_csi1 { + status =3D "disabled"; +}; + +&i2c0 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c0>; + status =3D "okay"; + + wm8904: codec@1a { + compatible =3D "wlf,wm8904"; + reg =3D <0x1a>; + #sound-dai-cells =3D <0>; + clocks =3D <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names =3D "mclk"; + assigned-clocks =3D <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates =3D <786432000>, <49152000>, <12288000>, <12288000>; + AVDD-supply =3D <®_audio_supply>; + CPVDD-supply =3D <®_audio_supply>; + DBVDD-supply =3D <®_audio_supply>; + DCVDD-supply =3D <®_audio_supply>; + MICVDD-supply =3D <®_audio_supply>; + wlf,drc-cfg-names =3D "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP =3D 0, KNEE_OP =3D 0, HI_COMP =3D 1, LO_COMP =3D 1 + * KNEE_IP =3D -24, KNEE_OP =3D -6, HI_COMP =3D 1/4, LO_COMP =3D 1 + * KNEE_IP =3D -42, KNEE_OP =3D -3, HI_COMP =3D 0, LO_COMP =3D 1 + * KNEE_IP =3D -45, KNEE_OP =3D -9, HI_COMP =3D 1/8, LO_COMP =3D 1 + * KNEE_IP =3D -30, KNEE_OP =3D -10.5, HI_COMP =3D 1/4, LO_COMP =3D 1 + */ + wlf,drc-cfg-regs =3D /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 =3D DMIC_CLK, don't touch others */ + wlf,gpio-cfg =3D <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +/* Bluetooth */ +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart1>; + uart-has-rtscts; + status =3D "okay"; +}; + +&mu_m0{ + status =3D "okay"; +}; + +&mu1_m0{ + status =3D "okay"; +}; + +&mu2_m0{ + status =3D "okay"; +}; + +&rtc { + status =3D "disabled"; +}; + +&sai6 { + assigned-clocks =3D <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents =3D <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates =3D <0>, <786432000>, <98304000>, <12288000>, <98304= 000>; + fsl,sai-asynchronous; + status =3D "okay"; +}; + +&sai7 { + assigned-clocks =3D <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents =3D <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates =3D <0>, <786432000>, <98304000>, <12288000>, <98304= 000>; + fsl,sai-asynchronous; + status =3D "okay"; +}; + +&thermal_zones { + pmic-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + pmic_crit0: trip1 { + temperature =3D <125000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&pmic_alert0>; + cooling-device =3D <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +/* WIFI */ +&usdhc3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>, <&pinctrl_wifi>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>; + bus-width =3D <4>; + non-removable; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + }; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_esai0: esai0grp { + fsl,pins =3D < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins =3D < + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041 + IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041 + IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041 + IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins =3D < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins =3D < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { + fsl,pins =3D < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins =3D < + /* GPIOs used by user space WiFi init */ + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021 + IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; +}; --=20 2.47.3 From nobody Sat Jul 25 16:50:44 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E412446C1D for ; Wed, 15 Jul 2026 19:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784142580; cv=none; b=FViKtPN1RrTP0uGMor5fotkqUtyjuV8bxGycrgN1briRvOeqn+hMwQJlKTU1cheHy1ug3V/b0C6ntu4FrmRLnEu9FHZl2hEfLKG6wJuaUbUSP7VY61YpiZO+CZTlj2CRkcoH9hNI5pg6C0RufPdGHCSSv0QLlMzrvxiwgkKim58= ARC-Message-Signature: i=1; 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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49541eb7372sm3786325e9.13.2026.07.15.12.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 12:09:16 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shawn Guo , Daniel Baluta , Josua Mayer , Alexander Stein , Ernest Van Hoecke , Maud Spierings , Francesco Dolcini , Hugo Villeneuve Subject: [PATCH v5 3/3] arm64: dts: imx8qm-var-som: Add support for Variscite Symphony board Date: Wed, 15 Jul 2026 21:09:09 +0200 Message-ID: <354dc61e75c935f6a7adea7b8c64fc324651d63b.1784142385.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-MX8 QuadMax system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals - PCIE support Link: https://variscite.com/carrier-boards/symphony-board/ Signed-off-by: Stefano Radaelli --- v4->v5: -=20 v3->v4: -=20 v2->v3: - Fix led typo - Moved reset-gpios in pciea_port0 - Removed wrong captouch pinctrl gpio v1->v2: - Fix ptn5150 interrupt - Fix ecspi1 cs gpio arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qm-var-som-symphony.dts | 490 ++++++++++++++++++ 2 files changed, 491 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.d= ts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 430085123b4e..ceb31556a8c0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -540,6 +540,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-ixora-v1= .1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-tqma8qm-mba8x.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-var-som-symphony.dtb =20 imx8qm-mek-ov5640-csi0-dtbs :=3D imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo dtb-${CONFIG_ARCH_MXC} +=3D imx8qm-mek-ov5640-csi0.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts b/ar= ch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts new file mode 100644 index 000000000000..7c7fc8958efc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Symphony carrier board for VAR-SOM-MX8 QuadMax + * + * Link: https://variscite.com/carrier-boards/symphony-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8qm-var-som.dtsi" + +/ { + model =3D "Variscite VAR-SOM-MX8 on Symphony evaluation board"; + compatible =3D "variscite,var-som-imx8qm-symphony", + "variscite,var-som-imx8qm", "fsl,imx8qm"; + chosen { + stdout-path =3D &lpuart0; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-back { + label =3D "Back"; + gpios =3D <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + button-home { + label =3D "Home"; + gpios =3D <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + button-menu { + label =3D "Menu"; + gpios =3D <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-heartbeat { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pca9534 0 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + reg_fec_phy: regulator-fec-phy { + compatible =3D "regulator-fixed"; + regulator-name =3D "fec-phy"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <20000>; + vin-supply =3D <®_vselect>; + gpio =3D <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb_otg1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&lsio_gpio0 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "sw-3p3-sd1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reg_vselect: regulator-vselect { + compatible =3D "regulator-fixed"; + regulator-name =3D "reg_vselect"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + gpio =3D <&pca9534 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ðphy0 { + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; +}; + +&fec1 { + mdio { + ethphy1: ethernet-phy@5 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <5>; + vddio-supply =3D <®_phy_vddio>; + reset-gpios =3D <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec2>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy1>; + phy-supply =3D <®_fec_phy>; + status =3D "okay"; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + status =3D "okay"; +}; + +&hsio_phy { + fsl,hsio-cfg =3D "pciea-pcieb-sata"; + fsl,refclk-pad-mode =3D "input"; + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pca9534: gpio@20 { + compatible =3D "nxp,pca9534"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pca9534>; + interrupt-parent =3D <&lsio_gpio1>; + interrupts =3D <24 IRQ_TYPE_LEVEL_LOW>; + }; + + /* USB Type-C Controller */ + typec_ptn5150: typec@3d { + compatible =3D "nxp,ptn5150"; + reg =3D <0x3d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ptn5150>; + interrupt-parent =3D <&lsio_gpio3>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + + port { + typec_dr_sw: endpoint { + remote-endpoint =3D <&usb3_drd_sw>; + }; + }; + }; +}; + +&i2c4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c4>; + status =3D "okay"; + + pca6408: gpio@21 { + compatible =3D "nxp,pcal6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "lvds_brg_en"; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible =3D "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg =3D <0x2e>; + label =3D "tpm"; + reset-gpios =3D <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + + /* Capacitive touch */ + ft5x06_ts: touchscreen@38 { + compatible =3D "edt,edt-ft5406"; + pinctrl-names =3D "default"; + reg =3D <0x38>; + pinctrl-0 =3D <&pinctrl_captouch>; + interrupt-parent =3D <&lsio_gpio0>; + interrupts =3D <19 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x =3D <800>; + touchscreen-size-y =3D <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + }; +}; + +&lpspi1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi1>; + cs-gpios =3D <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +/* console */ +&lpuart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart0>; + status =3D "okay"; +}; + +/* header */ +&lpuart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart2>; + status =3D "okay"; +}; + +&pca9534 { + usb3-signal-route-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "usb3_signal_route"; + }; +}; + +&pciea{ + phys =3D <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names =3D "pcie-phy"; + status =3D "okay"; +}; + +&pciea_port0 { + reset-gpios =3D <&pca6408 1 GPIO_ACTIVE_LOW>; +}; + +&usb3_phy { + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usbotg1>; + vbus-supply =3D <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status =3D "okay"; +}; + +&usbotg3 { + status =3D "okay"; +}; + +&usbotg3_cdns3 { + dr_mode =3D "otg"; + usb-role-switch; + status =3D "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint =3D <&typec_dr_sw>; + }; + }; +}; + +&usbphy1 { + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + cd-gpios =3D <&lsio_gpio0 14 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins =3D < + IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins =3D < + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins =3D < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins =3D < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA 0xc6000020 + IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL 0xc6000020 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins =3D < + IMX8QM_ENET1_MDC_DMA_I2C4_SCL 0xc6000020 + IMX8QM_ENET1_MDIO_DMA_I2C4_SDA 0xc6000020 + >; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins =3D < + IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004c + IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004c + IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004c + IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins =3D < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins =3D < + IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins =3D < + IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021 + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins =3D < + IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + >; + }; + + pinctrl_usbotg1: otg1grp { + fsl,pins =3D < + IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000048 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins =3D < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x00000021 + >; + }; +}; --=20 2.47.3