From nobody Sat Jul 25 18:05:55 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013042.outbound.protection.outlook.com [40.93.196.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 350C6225413; Wed, 15 Jul 2026 06:28:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.196.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096922; cv=fail; b=nfjPx6bdqI8TaJJwKlJ1165ZJQ4Rc+y3L4FiS+tWBsoiEZIORhmBPvwo9x5G44tLppEim0VnSXU/AUHUMteX3WAZ4um4szRB6XH2QX2ZaDwmlMLv7UEbp4q4WXon2CPLP47dhzgGxD8IFuPesmTDkGHrHePxY7T8in3R43VU7RI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096922; c=relaxed/simple; bh=7nXH2o91zbDXpwOzG5CGiDtK4lLAaqlF1GDYNC4XkBc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=n5N+CRn4X+eueuxjVafWuhgaLFzRlBCxp5X7rM15zmmZO/qlx4Ya0qlfLAawWSZHQTNKV0qgQy/sFuD8GIGPMv/inFd5n30TW02D7aZD+r5C0+YQMYMUpYsZg2DfNa15NJk4wy1TYQuLRDCQfdVYwOxBzic1ojDWZKscKydvgFQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=altera.com; spf=pass smtp.mailfrom=altera.com; dkim=pass (2048-bit key) header.d=altera.com header.i=@altera.com header.b=o/G3GjX4; arc=fail smtp.client-ip=40.93.196.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=altera.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=altera.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=altera.com header.i=@altera.com header.b="o/G3GjX4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=m0V9DlynbFdMbYIFEIPxxu8cKr0TCAoUCCV4k9u2ClTm6W21c6R25tj7i+Fa8VermMmCSpLc7Ja7cszlou2DnVk1cgpxaY8aqpMfeJKw2bmlIRouQpHYIxHonnaWIp9P9oLg5wZGRrBDRXGs3CXjWHDTDuEZThBH/Jx9j2bBwgEnZFTECZIjt57rYied9eF8TfVXw0WFdJSE7FwRA61+56b/o/9PsQZv41H7moNM6ZEJJnpHFlwfdU7Js0+RN5Ohnv3/5PYXL4nxnHLYuceVgJs+pzPxwPUM9SVLT0v/wIkudtatP11ItfMLYSGHzxfHSquJR88jPEJKQKeD2xEi9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kPrDjP169imGiMH0ZPmB3TQHIT92AAChcM/23+lB/xk=; b=RY+xfeTG//irSQoZi3ipn6eSKTzIcJoQae0EDihKsURiLwqb3fc5qRdl3VUWJaUjRLFNasELWap1l2H2RWVVn5APFzin5ELjevu0dVIibmVbWN6ZD+FgKbvYtfPWQ8wNBNrACS7cbgD+3WvIAjC6NGQH9XXAOV9Hn0eTRhYjqIzijDgPgyu22pQG2rNdK5Qk5Kms2zenvuM/ioRzvHUUIoPxqFHAccOy8mfDvnj5BVAK2ANuN+AnRDPJdwEr7eK2jCVVh1W8T9yU7w39rgOblZ20gIDNx4Sc1FpnHg6GPmARMfpGhVRNA4DKYe2FgWDgbHtbnUFAcbmq6/VxEgd12A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=altera.com; dmarc=pass action=none header.from=altera.com; dkim=pass header.d=altera.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kPrDjP169imGiMH0ZPmB3TQHIT92AAChcM/23+lB/xk=; b=o/G3GjX40i8+nQ1q9fe4vLQfFnW59+QEzk/wqSstmC3+jizHvcqP6eI37Jm6fZ60KOdpVG3kHzlzAVpTNRxN2amxyRgz++I/B30P2g24LtPT0XBVFlnyTYG3ovWCrWI6QmZVmU1t895z8X+4MbHK4Zi0p4yvQAjEsHwAnIJPZ7vE1bOZBMu5AdxhYZ43zYZvBUGVa0PgmonUezydIQir7USYCdKqziqwNvC0/knfvh9uW20dnSzEBAr2uQKxENSwX+sZF4xAAwSoW4cXdg33tSH4CBr/yKaKR3U2hTpt0tGtAqZDxQzoEecU3d1KmkEkNw33oRFqj66RRhuNkFqCoA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=altera.com; Received: from CO1PR03MB5937.namprd03.prod.outlook.com (2603:10b6:303:6e::18) by SA5PR03MB989111.namprd03.prod.outlook.com (2603:10b6:806:4d6::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.202.18; Wed, 15 Jul 2026 06:28:39 +0000 Received: from CO1PR03MB5937.namprd03.prod.outlook.com ([fe80::f970:684e:8c80:91c3]) by CO1PR03MB5937.namprd03.prod.outlook.com ([fe80::f970:684e:8c80:91c3%6]) with mapi id 15.21.0223.011; Wed, 15 Jul 2026 06:28:36 +0000 From: tze.yee.ng@altera.com To: Dinh Nguyen , linux-kernel@vger.kernel.org, Guenter Roeck , Jonathan Corbet , Shuah Khan , linux-hwmon@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v5 1/2] firmware: stratix10-svc: add async HWMON read commands and register socfpga-hwmon device Date: Tue, 14 Jul 2026 23:28:01 -0700 Message-ID: <66493aed36c36718ab90d4792d04948d3926d377.1784096224.git.tze.yee.ng@altera.com> X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY1P220CA0007.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:59d::13) To CO1PR03MB5937.namprd03.prod.outlook.com (2603:10b6:303:6e::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PR03MB5937:EE_|SA5PR03MB989111:EE_ X-MS-Office365-Filtering-Correlation-Id: 684347aa-119e-4409-17fd-08dee23a45a9 X-MS-Exchange-AtpMessageProperties: SA X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|366016|1800799024|3023799007|6133799003|56012099006|22082099003|18002099003|55112099003|11063799006; X-Microsoft-Antispam-Message-Info: MYg572dNuSxtz+RSNgm9nDPQWazdxB6CzofPgLTqFUVbSNaOIiKsp52VCykGXy57MjQ3ey06a4cGJ67xu72f6AzI8aFZ+Gen0HPIle/o+ILPeNxvaa3rh677mXJQ+YV3EQhltjbSF1/ffFE18FbfQ0VqccM7cFJyhXteeJXuU7icLAPvhZoqG8I9OUH2bveHdAmaSOiVD3txCNdI/C8JoE54JbXyBFpQTNyTX8Gould1InyCNg2GK35Qzm70lqveH/Jru4n1cx3XrpWneNml6TZWlHuQbTYC4llonhlc7n0bko+XWaxBp35LFzus4LZytx1so+D2Z787TovXAiUaK3XCi6DPzUv0ozpWPTTL+Mt15CzMFy82jTnBWLxu3szqZa+OSQLELYt4mhaX++hG9ONo1zFgO6vRLHfTHes4qkslcj8silxquPRE/LzSYGYXeRAvaoxe1Q4WHXwLDeRtb8MftTU2OI/DtZI2s4AtQjWW9wmSrEUTWuIFhWeSzt0Xdiy5kdSxMnYMlX+jpnDTA7rRyXNYnNXYYwf9mSwjpboSZiwmucsfgi02tSB8ixAQ+AolHr9arYEe+uTAi6/HZM95LEotzThkcZy0tZfuz2FEh8T/1LwsaFlQTRo9HKnbb/d73megHBwXI4qSfg1m+NisOzmTbcC9Mu2g9d6cHOQ= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO1PR03MB5937.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(23010399003)(376014)(366016)(1800799024)(3023799007)(6133799003)(56012099006)(22082099003)(18002099003)(55112099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?3TltxbuW1df7G1xtl79ChTZMij96/YVpetGlQ6KBWkijgErj2GRgd2WdVnsZ?= =?us-ascii?Q?kX2ZzW9l6sebmUrnSQsZ6F2PzCNt/pIF5+gaCZrmU8imggtM3WagmVtGcHeE?= =?us-ascii?Q?QXkE+Vs+wB1PSA6o3RW+Ayfh4yIeG2L2+IvPtMGpyZdXbmNH+Vf1Ic9U9DKn?= =?us-ascii?Q?1+8cOwkthYzDpsw5Zekk6LHylO+VmP0i5+ig+KkvaJs692s9B1ForL18BBWX?= =?us-ascii?Q?HiO26RbzMdNc82mm6GolXBayMIl1kcVnYhWzAGem29XD65BAdqMAtVQYYC+w?= =?us-ascii?Q?nxIYYKKBQm/pgFU/uaufMvI5dTNfP2oxTDzx6rv+p+AC9gov6xYry4tlFWcp?= =?us-ascii?Q?E8HxnJMd3R+ZX5Bm8d3x2cdFIHhEVBnbHtJP8b13S3q4m6Jk2sY2QQryMx1X?= =?us-ascii?Q?ghwB6s91g5uAhDSHRQPistcLoZY4M3kj4/2Br5u234pOBu/eXXkaoVfnTshY?= =?us-ascii?Q?uZXyb+p9JK6ieDRPfohqccmutRwUrytHuXkJzSeDzYJPLbkq9h1iQCVhnRQu?= =?us-ascii?Q?MUrbciXvGYSd/bmmz+SmyJjcojtO7RN8Ire9p7OX66vIqjyjKSETWOqrfhG4?= =?us-ascii?Q?qSAuw0GP+vhZZrz2ceaa/d4l3RNkNxzlnlfCTqADdi2UsYIbD8XBdeZMvEMU?= =?us-ascii?Q?5hXq5GOmBDNg6d8F8hPPOlwQ0+KKCMBkoaTh0EbPRpJnUPvNnVs6VE6jvwDX?= =?us-ascii?Q?cZOG7xZ6pWurY1tAGCzm/Y5yg80JAHRVdzNFAH9l+P/vqFyXycLKUvpS90sB?= =?us-ascii?Q?4keDDciZVToA5frC6bCwzsX9Frf0eT0h1xL+E3rChdUuHWbUlRbaYfUwAu8w?= =?us-ascii?Q?PmhLtnX2T1hoIph3c7z614cpsUXjmsorld6UAPR/ybY8d4LILhKLxgxHUKTn?= =?us-ascii?Q?fC4e+caPy4IipyN60z0G/5Dqx1VufYQHB6NsftDxRIBXxYn8ueiPBLqLeM5N?= =?us-ascii?Q?KQ60Eom18YMj0IBd51Gwg/diYCJrd4WPESwIiA1+go/H/Dgngg8gHijXge4Y?= =?us-ascii?Q?6DcSHGt42GXNuEQIf2iBdCSnOZpteonab6TPa37SgcNnQRSjXJufvI+xP2nF?= =?us-ascii?Q?EyNtmBEsqrXpctlBK67Epv8/waUIH5pZq0fFCFPuo1OaVSDpQTB2E7E05kPw?= =?us-ascii?Q?yarpc3D41fhn2Egz4JGQ+H8k2zEHxBldi86rIUt+4MlvnWxMuSWKo88WVYPo?= =?us-ascii?Q?D6czmxHPSNO/TJst+t5F1oBKrp1QFiDidr8u0UxZ25maLuR8DBM3U0JJOxEs?= =?us-ascii?Q?uRB8cIUSyKcfmVkgyLokV9AUAgxJjgCd6s+RAeYT+B/HlO3PK3l5yCPOjzZL?= =?us-ascii?Q?c9lNqT+C4idUO3dqJGClmwWnHx0ZlWewU/0uWQiIot5g5dSLhe0JlwYxnGKT?= =?us-ascii?Q?SRfSIvWjHDY+z0PdJi4WmeOVqUaUkWE//hGzi4UVx9zdSM6R3vGM+22lFjgB?= =?us-ascii?Q?N7ETqGMioMdTG943l+cc+A3qVHi5leennX8AUEnrh8zvf/ZKWx8/mCcRO3B2?= =?us-ascii?Q?0KqArHMQ4nH1B84Uxzco6ht+uc4cKBadKKQVS7fcgYuMdZd9cr8u8hYaeA/x?= =?us-ascii?Q?x/HMBRgnu+9g6tnzVctCfIxjZdc9vW9v5fRqddvDS4w76QENNjL3fpzPzEKh?= =?us-ascii?Q?an8smjoOHInoQr4u7S0iFFrPxHRe+Z9hTUlqyrnRxkapN6cgI+JuW1HNpr+D?= =?us-ascii?Q?b4mGQAdTtO9qLvSJgKF5HYXGA8waKwdAbdN6BpwFERUGdGnBh3+h/D/i1S/V?= =?us-ascii?Q?iH2T1tFqYA=3D=3D?= X-OriginatorOrg: altera.com X-MS-Exchange-CrossTenant-Network-Message-Id: 684347aa-119e-4409-17fd-08dee23a45a9 X-MS-Exchange-CrossTenant-AuthSource: CO1PR03MB5937.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2026 06:28:36.5313 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LkoqzzbZipP0syRITi83EVQhMlXnkkReu/Nb0WBvjtKH7CEAfYptbSWroZ5dqsvU7KxfFIL2sEjZ8Bo7PTsIfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PR03MB989111 Content-Type: text/plain; charset="utf-8" From: Tze Yee Ng Add asynchronous Stratix 10 service layer support for hardware monitor temperature and voltage read commands in stratix10_svc_async_send() and stratix10_svc_async_prepare_response(). Register a socfpga-hwmon platform device from the service layer driver when hardware monitor support is enabled, similar to the RSU device. Signed-off-by: Nazim Amirul Signed-off-by: Tze Yee Ng --- Changes in v5: - No functional changes from v4 Changes in v3: - No functional changes from v2 Changes in v2: - Extend patch scope beyond async SMC support: register socfpga-hwmon platform device from stratix10-svc when CONFIG_SENSORS_ALTERA_SOCFPGA_HWM= ON is enabled - Follow RSU-style registration; RSU probe error handling is unchanged - Add err_unregister_clients to unregister hwmon and RSU on populate failure - Unregister hwmon platform device in stratix10-svc remove() --- drivers/firmware/stratix10-svc.c | 46 ++++++++++++++++++-- include/linux/firmware/intel/stratix10-smc.h | 38 ++++++++++++++++ 2 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index 5e20057ee344..bb6c02cd1f81 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -45,6 +45,7 @@ =20 /* stratix10 service layer clients */ #define STRATIX10_RSU "stratix10-rsu" +#define SOCFPGA_HWMON "socfpga-hwmon" =20 /* Maximum number of SDM client IDs. */ #define MAX_SDM_CLIENT_IDS 16 @@ -104,9 +105,11 @@ struct stratix10_svc_chan; /** * struct stratix10_svc - svc private data * @stratix10_svc_rsu: pointer to stratix10 RSU device + * @stratix10_svc_hwmon: pointer to stratix10 HWMON device */ struct stratix10_svc { struct platform_device *stratix10_svc_rsu; + struct platform_device *stratix10_svc_hwmon; }; =20 /** @@ -1329,6 +1332,14 @@ int stratix10_svc_async_send(struct stratix10_svc_ch= an *chan, void *msg, args.a0 =3D INTEL_SIP_SMC_ASYNC_RSU_NOTIFY; args.a2 =3D p_msg->arg[0]; break; + case COMMAND_HWMON_READTEMP: + args.a0 =3D INTEL_SIP_SMC_ASYNC_HWMON_READTEMP; + args.a2 =3D p_msg->arg[0]; + break; + case COMMAND_HWMON_READVOLT: + args.a0 =3D INTEL_SIP_SMC_ASYNC_HWMON_READVOLT; + args.a2 =3D p_msg->arg[0]; + break; default: dev_err(ctrl->dev, "Invalid command ,%d\n", p_msg->command); ret =3D -EINVAL; @@ -1422,6 +1433,10 @@ static int stratix10_svc_async_prepare_response(stru= ct stratix10_svc_chan *chan, */ data->kaddr1 =3D (void *)&handle->res; break; + case COMMAND_HWMON_READTEMP: + case COMMAND_HWMON_READVOLT: + data->kaddr1 =3D (void *)&handle->res.a2; + break; =20 default: dev_alert(ctrl->dev, "Invalid command\n ,%d", p_msg->command); @@ -2016,16 +2031,38 @@ static int stratix10_svc_drv_probe(struct platform_= device *pdev) if (ret) goto err_put_device; =20 + if (IS_ENABLED(CONFIG_SENSORS_ALTERA_SOCFPGA_HWMON)) { + svc->stratix10_svc_hwmon =3D + platform_device_alloc(SOCFPGA_HWMON, 0); + if (!svc->stratix10_svc_hwmon) { + dev_err(dev, "failed to allocate %s device\n", + SOCFPGA_HWMON); + } else { + svc->stratix10_svc_hwmon->dev.parent =3D dev; + + ret =3D platform_device_add(svc->stratix10_svc_hwmon); + if (ret) { + dev_err(dev, "failed to add %s device: %d\n", + SOCFPGA_HWMON, ret); + platform_device_put(svc->stratix10_svc_hwmon); + svc->stratix10_svc_hwmon =3D NULL; + } + } + } + ret =3D of_platform_default_populate(dev_of_node(dev), NULL, dev); if (ret) - goto err_unregister_rsu_dev; + goto err_unregister_clients; =20 pr_info("Intel Service Layer Driver Initialized\n"); =20 return 0; =20 -err_unregister_rsu_dev: - platform_device_unregister(svc->stratix10_svc_rsu); +err_unregister_clients: + if (svc->stratix10_svc_hwmon) + platform_device_unregister(svc->stratix10_svc_hwmon); + if (svc->stratix10_svc_rsu) + platform_device_unregister(svc->stratix10_svc_rsu); goto err_free_fifos; err_put_device: platform_device_put(svc->stratix10_svc_rsu); @@ -2049,6 +2086,9 @@ static void stratix10_svc_drv_remove(struct platform_= device *pdev) struct stratix10_svc_controller *ctrl =3D platform_get_drvdata(pdev); struct stratix10_svc *svc =3D ctrl->svc; =20 + if (svc->stratix10_svc_hwmon) + platform_device_unregister(svc->stratix10_svc_hwmon); + platform_device_unregister(svc->stratix10_svc_rsu); =20 stratix10_svc_async_exit(ctrl); diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/f= irmware/intel/stratix10-smc.h index 9224974fffc4..706176cc5c6a 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -701,6 +701,44 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_= CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_ASYNC_POLL \ INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL) =20 +/** + * Request INTEL_SIP_SMC_ASYNC_HWMON_READTEMP + * Async call to request temperature + * + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_HWMON_READTEMP + * a1 transaction job id + * a2 Temperature Channel + * a3-a17 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_REJECTED + * or INTEL_SIP_SMC_STATUS_BUSY + * a1-a17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_HWMON_READTEMP 0xE8 +#define INTEL_SIP_SMC_ASYNC_HWMON_READTEMP \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_HWMON_READTEMP) + +/** + * Request INTEL_SIP_SMC_ASYNC_HWMON_READVOLT + * Async call to request voltage + * + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_HWMON_READVOLT + * a1 transaction job id + * a2 Voltage Channel + * a3-a17 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_REJECTED + * or INTEL_SIP_SMC_STATUS_BUSY + * a1-a17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_HWMON_READVOLT 0xE9 +#define INTEL_SIP_SMC_ASYNC_HWMON_READVOLT \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_HWMON_READVOLT) + /** * Request INTEL_SIP_SMC_ASYNC_RSU_GET_SPT * Async call to get RSU SPT from SDM. --=20 2.43.7 From nobody Sat Jul 25 18:05:55 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013017.outbound.protection.outlook.com [40.93.196.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFEB82FD69A; Wed, 15 Jul 2026 06:28:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.196.17 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096930; cv=fail; b=gTQJ/vhtHb1h7auFWB2P81uqk+hxyuVOsSX+VO/edDUUTxGvbzGesNc12rn3IvLjnkqHvUDiFlf05F8jXPArmW7n59ibmjsLYNDQh3ETTcT9Lv/yeY20twK44Vzdf56+r852n/Tyi8vXZouYWFP1PKrWuHnh3ViAcPxeSARD2uY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096930; c=relaxed/simple; bh=lYYgknSonAxpVSlcWp3FD5+BG4QlPSBjNChZ/IeH7Q0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=I5CqvQIKUQMFFY8DbEVbBdOOglbFGYT5R9Q+1qgcxq3+G9f5lNDzmAGwesmEaEZugsUw1vTaiNQHVAx1xm8o/pwzETSLmVJFCoND2K+9+Tdes9H/yuPpYauf2skD38DLa7idJ28jLlanOtwMef3889npQyZe9KcDjYW5tLv/5Nw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=altera.com; spf=pass smtp.mailfrom=altera.com; dkim=pass (2048-bit key) header.d=altera.com header.i=@altera.com header.b=afrJ0wNL; arc=fail smtp.client-ip=40.93.196.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=altera.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=altera.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=altera.com header.i=@altera.com header.b="afrJ0wNL" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=w0GVlbdLqcAr3R3Y0OH8PdQGst4DLKK7+HoQZiZK3h7LmWZuPqcQogmOnF/vfV4zzKrEMbHzfmo8kWj18IR13PQiPRXo5/X2D3UjmpVqlxI4jnDSMZLynHhWzehBHUEntly4Oq4UwDwFXEd/fhcQhwmo706mh0HMQw1QlWJYC6ZniSKEoMtQS0zbfqKGqtylPjgFFrDQboCC0VAwwOagexF3Fl0r9L5g+3kZ6q4o3VAvG2vRktWwAM4gRZukn0dkNdsakPIPJ7Juo4JInVZJjNHNqS9H91Z0AVdYgTG6/q1LMRDVTp49hTkIBUUzA8cF94NF0khC1F+tANCatp13yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=egUHE/zWQEm27atmaUeQH0v/XWRZI45wpnaQhhfT8cY=; b=fvJ/eibILvMY6pD7G3I1OSI6gO24mikdIAWKN1oeVnpjZNpsi+ro7qLZehfQCWAZ2peMgQLTmN12pbSrR6Xh57FXdgXdTJ1oMXCkrlvmdcfznzL4QW+lrSWsJ1KAr5WY8NfSKZzINiUb/pvKcPL2SxqjQisKhv8CBLyp9bvhhE5m4hGfhNS7EF3RwfUIvPyQJ6PRfIfZoyeWnjj00So2jKz28wCZ1/61t1gn+J2relCKbHE1GwNrZjVwo1JpzD8SICiVA8CvuU6djm8nKQX2z/YrG2fcEYdJ0OWuwltvvFJqcADQDxN/oGuwVwepL6E8FRFG9MqNFj5ubQJhIe7EWQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=altera.com; dmarc=pass action=none header.from=altera.com; dkim=pass header.d=altera.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=egUHE/zWQEm27atmaUeQH0v/XWRZI45wpnaQhhfT8cY=; b=afrJ0wNLPyvExhyLPkiDuZSfvflo9cdJxrnXTD3jBImlfE6WTGIVR1H2lE2ds0gx54CFtKh2r8ZS0AEVWgM3tnA8sRdEsXe8BMRqJsxkQW634Fb3w1+8W2JQ78XgRI/QGA4b0uDKrx/CVgnh8M9hVEeO/1L4Af/zYiFdbw4pfPyIGE1bdGYbj5WzaeMLnMTmGucHjBcjgnpBK5ItlHC+LmHjy7G+XI+xT/g/BGcIYwqu9Xs1UXZP8wuuqQcwJ9BGLC02oGBAIonbze/w3VxZ/fN7KFQ9ztDas4mN1WueQ0nvexcXqJhd9MHqvq2zi3EazRMwd3Q3kXHG44PiWvJbzQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=altera.com; Received: from CO1PR03MB5937.namprd03.prod.outlook.com (2603:10b6:303:6e::18) by SA5PR03MB989111.namprd03.prod.outlook.com (2603:10b6:806:4d6::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.202.18; Wed, 15 Jul 2026 06:28:45 +0000 Received: from CO1PR03MB5937.namprd03.prod.outlook.com ([fe80::f970:684e:8c80:91c3]) by CO1PR03MB5937.namprd03.prod.outlook.com ([fe80::f970:684e:8c80:91c3%6]) with mapi id 15.21.0223.011; Wed, 15 Jul 2026 06:28:45 +0000 From: tze.yee.ng@altera.com To: Dinh Nguyen , linux-kernel@vger.kernel.org, Guenter Roeck , Jonathan Corbet , Shuah Khan , linux-hwmon@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v5 2/2] hwmon: add Altera SoC FPGA hardware monitoring driver Date: Tue, 14 Jul 2026 23:28:02 -0700 Message-ID: <484efc0ef86ba378e903366a39e04e4e19531845.1784096224.git.tze.yee.ng@altera.com> X-Mailer: git-send-email 2.43.7 In-Reply-To: References: Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY1P220CA0007.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:59d::13) To CO1PR03MB5937.namprd03.prod.outlook.com (2603:10b6:303:6e::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PR03MB5937:EE_|SA5PR03MB989111:EE_ X-MS-Office365-Filtering-Correlation-Id: 4818ffcc-8a6d-432b-5211-08dee23a5157 X-MS-Exchange-AtpMessageProperties: SA X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|366016|1800799024|6133799003|56012099006|22082099003|18002099003|55112099003|5023799004|11063799006; X-Microsoft-Antispam-Message-Info: uBg5rdne5IuYr+Hfyx6zCxhWkhTRhVkbgfKya6u7L53Q/P5tPCu/dvLOhB55pYE6E6zNOVUXhRx0TqJbq3sRwHjsdwwuY0gvhYpavVjFmkcQAgqW80avWlHynQc3/+uDCUVmtMG+n2bw0IEXwtQYAG4GK0E84oZhoRkMTO310u5Nli/SWsMBfWWAcbzy9dOsptZAoy1iWpTnG1mSTy2dOMk4jE2uXKHWunCjK22/ibLmpA3XhJkcN3iFqPEkCsgvX/ty71FX6et3WnOi4GNDmVesixsCzSNR0UlCfV4f64W7YxYtclzUltWHotB2zxmCApx3iJkwy8KwdpwQKr0SLnZl+iMdiUZXgBMxZMtqBD3fDPmRDy/O8nVCcD+Y/Fq63J7Kk6SXPDDQtkoIRfbDnqH56S+oStB9SwDKRdkXVl91Wy0I/FGbbi5yirPBwfDTTrzcEavvqCJUgDqvLFYe7KFqxcdB6pX1sWyXzPJ45DaRdFOkofU0Ll9mUtOdCvIbSB7pB3FbN1RWJE0KWK4DY7bwA3C16LZjUSYkpXBjl7HEqs4nz/fUifRhS1PQw3GYctmwLD4n4QxI/hGZMFE+BABt7cn52vhpr65zfkESdsLHSEwpHy+YnQitCU26BRf12UoP9A1E2QtWxI/3hvRWkBJHFb3CMqEhQ+ByxuU1dew= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO1PR03MB5937.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(23010399003)(376014)(366016)(1800799024)(6133799003)(56012099006)(22082099003)(18002099003)(55112099003)(5023799004)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?+fGO8EtOnWao2+4w6zbq8/NFsSLJOhKPlfLH3bLw/aGR/RZpVknP7JVfHU8Q?= =?us-ascii?Q?ER6YrWNvoNc1ZQ9cgMUXw1r/6LMKW6TrSX5Fjcmi+sGzpZ5gOpuPl33FYDxI?= =?us-ascii?Q?D388Mtd2P0kHvxjyajxb/15tLCXdx1UQGw07Y3agj1q79d/MPJHGk+qlTIRs?= =?us-ascii?Q?lOdzV32IXEE63SYsbJmvZVDDLClxlGlZ4fvhxqNjHLeZEnYzE8MdwfqWnccR?= =?us-ascii?Q?f/FpmRswcWAUZ3JTUD2UPFf8HC32jteVzQ/kTahkmo9hGXDINRQ4Z0vQHUjw?= =?us-ascii?Q?0fOGtaeXfRLAMZNZolIDq5bIWh4l6qahP8XlUeyeNgUpvjMURuUDpbXCZH8q?= =?us-ascii?Q?c1P7mYbDAQLjtYOizrVNpFa8JT6gEEHGOuGRRbYswJ6obRKmBfnO9TbX5pID?= =?us-ascii?Q?IVrjldJLHgA5LrfihKuWJxfTD5yQ8T1wqOapCk9N5k91EvFUTaKJvf38vv1u?= =?us-ascii?Q?46hbf8+FfzdogkkrlPIq5Srhq/R5biq8Nc3b+D0iYJK9g1uClK2i8KKWM1S1?= =?us-ascii?Q?qFNJ85MpqoxQE3/BiCP1b8SyVXoji1TdNeooR57CoSbs+4MY5StSBfR+ue5T?= =?us-ascii?Q?R4IGRmglJ4Ja5uvAQEvbDbexXCv9UnnB2JGGnrzDJIfJiJIwSzukfjGQifzt?= =?us-ascii?Q?M4jUGT8ZVbOxx9OZy7/sHR6JEajQT/YcFHTpaYA5H6wTHLmgYGwwpWcx/TbM?= =?us-ascii?Q?9XjNVKgluPqlxSvcqX49D4KpcXZYbrlpO2SPLQNRw7ttXQzJ4uu0F0ZJwS5Q?= =?us-ascii?Q?r7xFZWbIU/+Q72rvwNm2wnlAplx2M3onmS4p2kl7pRw7LhqtLq8LNmjSH3qb?= =?us-ascii?Q?Ph6v45IswoU33AohDaV99DLFjD0hpnazvD7wMUxp0VhEndU3uQqWWoWedms7?= =?us-ascii?Q?98kk/oY5/7CIxf84tqtrgS5oMLGvRipv00h8pV8Qj5ad9HzVY4CZw+VFBpxv?= =?us-ascii?Q?aSZYjQNdeLIustrXSArE6Hem1nVlhGFrSdBglzak6PiVS08kd1ELSZZDGNe8?= =?us-ascii?Q?pJ8ZmEp28J2T/C8wnrV5DiI1+f/X4W2QoLnnZtBvZEQLdb1/be6poFaG450/?= =?us-ascii?Q?us1e3MfD/7BGNMs1zJFvH1RHIanwub3Is9YEJVMbQgSCtUjhDsw/gfLU/N0v?= =?us-ascii?Q?1rQz/HkHGSK6l5/D5G8novGC03xkOC4/VbkgxhvZ7sbMni9GjOeMGiXRsD6T?= =?us-ascii?Q?wIH+bH0Ir15DkQBf+qoFAGvKMa28M/4D+GsVe0akJg+OCTUVYL8HstZPqJUT?= =?us-ascii?Q?ZWnitKcnrTJJFbvntm8sufoT+WZ4iKRCM0w5ZVRqLn4Z33957vTUAV+1Zbw+?= =?us-ascii?Q?AanyfxF6jdXKpEtVbA0FvaWm77tsZPcrNdZIKJqdCLrxqXbsx+V5b0+0yP9T?= =?us-ascii?Q?YiBIn0DO7db1LXoW1H38zEqUMDYDYXbCEiKnkHKB1XE2R+2h3buG/wjBnWRg?= =?us-ascii?Q?4cUTD7xV22wJvaR+Haz/I+Jk9qFj8bRhmPKRy9xrOQEs+SfvFunug170RlvK?= =?us-ascii?Q?fAbrjEV/wv/GFHicVGf/H/nmO5C9NHWoAVsBwVvgd+Ll4Z6plnNGzlRpa0Qg?= =?us-ascii?Q?iohGBZRu/LrC5hzLKaiFQ495y8pXJgV7yMB/06HFaYt2vD6sQeM/1M0SGRI3?= =?us-ascii?Q?S/JiYr0EBSVFaJkKmJ48OyYLyr+SAwiElHhjCsZHwocWaMQU9YijNrZCvM84?= =?us-ascii?Q?5X1qDROwTRwAzQULIixL/wur81L5vGDHKZQrrSEUqpFwrQZJkma+aovE/Peg?= =?us-ascii?Q?g//NqLKjZg=3D=3D?= X-OriginatorOrg: altera.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4818ffcc-8a6d-432b-5211-08dee23a5157 X-MS-Exchange-CrossTenant-AuthSource: CO1PR03MB5937.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2026 06:28:45.6981 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IKPw1PFki/0YEcfEyUu8Q1e8C9og+Ik6xzMe+YfOWCHXURE8Psien5sv/xTWK4oJhJ+/2vsHhL8Y3tP+nqDvTw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PR03MB989111 Content-Type: text/plain; charset="utf-8" From: Tze Yee Ng Add a hardware monitor driver for Altera SoC FPGA devices using the Stratix 10 service layer. Sensor channels are selected based on the service layer compatible string. Signed-off-by: Nazim Amirul Signed-off-by: Tze Yee Ng --- Changes in v5: - Poll async responses until HWMON_TIMEOUT (2 s) instead of a fixed 3-iteration retry loop (~3 ms), fixing premature timeouts observed on silicon - Add MODULE_ALIAS("platform:socfpga-hwmon") Changes in v4: - Register devm_add_action_or_reset() before devm_hwmon_device_register_with_info(); drop manual channel cleanup on hwmon registration failure - Remove unreferenced async completion and pre-poll wait_for_completion_io_timeout(); poll directly after async_send() with the existing retry loop Changes in v3: - Fix 16-bit signed Q8.8 temperature conversion (cast through s16) - Remove unused async callback; pass NULL to stratix10_svc_async_send() - Keep wait_for_completion_io_timeout() before polling with comment explaining the service layer never invokes the callback but firmware needs time to complete the transaction (RSU pattern) - Align async poll loop with RSU (retry on failure instead of aborting) - Use wait_for_completion_timeout() for synchronous reads - Handle -EINVAL and -EOPNOTSUPP when async client registration fails - Defer SVC channel/async cleanup via devm_add_action_or_reset(); drop .remove() Changes in v2: - Drop altr,stratix10-hwmon OF compatible and DT channel parsing - Select channels from hardcoded tables using parent SVC compatible (intel,stratix10-svc or intel,agilex-svc) - Rename driver from stratix10-hwmon to socfpga-hwmon - Rename Kconfig symbol to CONFIG_SENSORS_ALTERA_SOCFPGA_HWMON - Add Agilex voltage and temperature channel tables - Convert SDM Q8.8 degrees Celsius to hwmon millidegrees - Convert SDM Q16 volts to hwmon millivolts - Use socfpga_hwmon as hwmon sysfs device name - Add last_err for synchronous SVC read error propagation - Update Documentation/hwmon and MAINTAINERS accordingly --- Documentation/hwmon/index.rst | 1 + Documentation/hwmon/socfpga-hwmon.rst | 34 ++ MAINTAINERS | 8 + drivers/hwmon/Kconfig | 10 + drivers/hwmon/Makefile | 1 + drivers/hwmon/socfpga-hwmon.c | 579 ++++++++++++++++++++++++++ 6 files changed, 633 insertions(+) create mode 100644 Documentation/hwmon/socfpga-hwmon.rst create mode 100644 drivers/hwmon/socfpga-hwmon.c diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index 29130df44d12..3299417a24b8 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -254,6 +254,7 @@ Hardware Monitoring Kernel Drivers sparx5-temp spd5118 stpddc60 + socfpga-hwmon surface_fan sy7636a-hwmon tc654 diff --git a/Documentation/hwmon/socfpga-hwmon.rst b/Documentation/hwmon/so= cfpga-hwmon.rst new file mode 100644 index 000000000000..e5da42556a62 --- /dev/null +++ b/Documentation/hwmon/socfpga-hwmon.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver socfpga-hwmon +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +Supported chips: + + * Altera Stratix 10 SoC FPGA + * Altera Agilex SoC FPGA + +Authors: + - Nazim Amirul + - Tze Yee Ng + +Description +----------- + +This driver supports hardware monitoring for Altera SoC +FPGA devices through the Secure Device Manager and Stratix 10 service laye= r. + +The following sensor types are supported: + + * temperature + * voltage + +Usage Notes +----------- + +The stratix10-svc driver registers a socfpga-hwmon platform device when +hardware monitor support is enabled. Sensor channels are selected in the +driver based on the service layer compatible string: + + * intel,stratix10-svc + * intel,agilex-svc diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..2b0ee6d5c6ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -965,6 +965,14 @@ L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-altera.c =20 +ALTERA SoC FPGA HWMON DRIVER +M: Nazim Amirul +M: Tze Yee Ng +L: linux-hwmon@vger.kernel.org +S: Maintained +F: Documentation/hwmon/socfpga-hwmon.rst +F: drivers/hwmon/socfpga-hwmon.c + ALTERA TRIPLE SPEED ETHERNET DRIVER M: Boon Khai Ng L: netdev@vger.kernel.org diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 5c2d3ff5fce8..54ce630c7de6 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2157,6 +2157,16 @@ config SENSORS_SMSC47M192 This driver can also be built as a module. If so, the module will be called smsc47m192. =20 +config SENSORS_ALTERA_SOCFPGA_HWMON + tristate "Altera SoC FPGA hardware monitoring features" + depends on INTEL_STRATIX10_SERVICE + help + If you say yes here you get support for the temperature and + voltage sensors of Altera SoC FPGA devices. + + This driver can also be built as a module. If so, the module + will be called socfpga-hwmon. + config SENSORS_SMSC47B397 tristate "SMSC LPC47B397-NC" depends on HAS_IOPORT diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 63effc0ab8d1..aeedee80e1f0 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -221,6 +221,7 @@ obj-$(CONFIG_SENSORS_SMPRO) +=3D smpro-hwmon.o obj-$(CONFIG_SENSORS_SMSC47B397)+=3D smsc47b397.o obj-$(CONFIG_SENSORS_SMSC47M1) +=3D smsc47m1.o obj-$(CONFIG_SENSORS_SMSC47M192)+=3D smsc47m192.o +obj-$(CONFIG_SENSORS_ALTERA_SOCFPGA_HWMON) +=3D socfpga-hwmon.o obj-$(CONFIG_SENSORS_SPARX5) +=3D sparx5-temp.o obj-$(CONFIG_SENSORS_SPD5118) +=3D spd5118.o obj-$(CONFIG_SENSORS_STTS751) +=3D stts751.o diff --git a/drivers/hwmon/socfpga-hwmon.c b/drivers/hwmon/socfpga-hwmon.c new file mode 100644 index 000000000000..72418201b65d --- /dev/null +++ b/drivers/hwmon/socfpga-hwmon.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Altera SoC FPGA hardware monitoring driver + * + * Copyright (c) 2026 Altera Corporation + * + * Authors: + * Nazim Amirul + * Tze Yee Ng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HWMON_TIMEOUT msecs_to_jiffies(SVC_HWMON_REQUEST_TIMEOUT_MS) +#define HWMON_RETRY_SLEEP_MS 1U +#define HWMON_ASYNC_MSG_RETRY 3U +#define SOCFPGA_HWMON_MAXSENSORS 16 +#define SOCFPGA_HWMON_CHANNEL_MASK GENMASK(15, 0) +#define SOCFPGA_HWMON_PAGE_SHIFT 16 +#define SOCFPGA_HWMON_CHAN(page, channel) \ + (((page) << SOCFPGA_HWMON_PAGE_SHIFT) | \ + ((channel) & SOCFPGA_HWMON_CHANNEL_MASK)) +#define SOCFPGA_HWMON_ATTR_VISIBLE 0444 +/* Temperature from SDM is signed Q8.8 degrees Celsius (8 fractional bits)= . */ +#define SOCFPGA_HWMON_TEMP_FRAC_BITS 8 +#define SOCFPGA_HWMON_TEMP_FRAC_DIV BIT(SOCFPGA_HWMON_TEMP_FRAC_BITS) +#define SOCFPGA_HWMON_TEMP_MDEG_SCALE 1000 +/* Voltage from SDM is unsigned Q16 volts (16 fractional bits). */ +#define SOCFPGA_HWMON_VOLT_FRAC_BITS 16 +#define SOCFPGA_HWMON_VOLT_FRAC_DIV BIT(SOCFPGA_HWMON_VOLT_FRAC_BITS) +#define SOCFPGA_HWMON_VOLT_MV_SCALE 1000 + +#define ETEMP_INACTIVE 0x80000000U +#define ETEMP_TOO_OLD 0x80000001U +#define ETEMP_NOT_PRESENT 0x80000002U +#define ETEMP_TIMEOUT 0x80000003U +#define ETEMP_CORRUPT 0x80000004U +#define ETEMP_BUSY 0x80000005U +#define ETEMP_NOT_INITIALIZED 0x800000FFU + +struct socfpga_hwmon_channel { + u32 reg; + const char *label; +}; + +struct socfpga_hwmon_board_data { + const struct socfpga_hwmon_channel *temp; + unsigned int num_temp; + const struct socfpga_hwmon_channel *volt; + unsigned int num_volt; +}; + +struct socfpga_hwmon_priv { + struct stratix10_svc_chan *chan; + struct stratix10_svc_client client; + struct completion completion; + struct mutex lock; /* protect SVC calls */ + bool async; + int last_err; /* sync-mode SVC result; 0 on success */ + u32 temperature; + u32 voltage; + int temperature_channels; + int voltage_channels; + const char *temp_chan_names[SOCFPGA_HWMON_MAXSENSORS]; + const char *volt_chan_names[SOCFPGA_HWMON_MAXSENSORS]; + u32 temp_chan[SOCFPGA_HWMON_MAXSENSORS]; + u32 volt_chan[SOCFPGA_HWMON_MAXSENSORS]; +}; + +static umode_t socfpga_hwmon_is_visible(const void *dev, + enum hwmon_sensor_types type, + u32 attr, int chan) +{ + const struct socfpga_hwmon_priv *priv =3D dev; + + switch (type) { + case hwmon_temp: + if (chan < priv->temperature_channels) + return SOCFPGA_HWMON_ATTR_VISIBLE; + return 0; + case hwmon_in: + if (chan < priv->voltage_channels) + return SOCFPGA_HWMON_ATTR_VISIBLE; + return 0; + default: + return 0; + } +} + +static void socfpga_hwmon_readtemp_cb(struct stratix10_svc_client *client, + struct stratix10_svc_cb_data *data) +{ + struct socfpga_hwmon_priv *priv =3D client->priv; + + priv->last_err =3D -EIO; + if (data->status =3D=3D BIT(SVC_STATUS_OK)) { + priv->last_err =3D 0; + priv->temperature =3D (u32)*(unsigned long *)data->kaddr1; + } else if (data->kaddr1) { + dev_err(client->dev, "%s failed with status 0x%x, value 0x%lx\n", + __func__, data->status, + *(unsigned long *)data->kaddr1); + } else { + dev_err(client->dev, "%s failed with status 0x%x\n", + __func__, data->status); + } + + complete(&priv->completion); +} + +static void socfpga_hwmon_readvolt_cb(struct stratix10_svc_client *client, + struct stratix10_svc_cb_data *data) +{ + struct socfpga_hwmon_priv *priv =3D client->priv; + + priv->last_err =3D -EIO; + if (data->status =3D=3D BIT(SVC_STATUS_OK)) { + priv->last_err =3D 0; + priv->voltage =3D (u32)*(unsigned long *)data->kaddr1; + } else if (data->kaddr1) { + dev_err(client->dev, "%s failed with status 0x%x, value 0x%lx\n", + __func__, data->status, + *(unsigned long *)data->kaddr1); + } else { + dev_err(client->dev, "%s failed with status 0x%x\n", + __func__, data->status); + } + + complete(&priv->completion); +} + +static int socfpga_hwmon_parse_temp(long *val, u32 temperature) +{ + switch (temperature) { + case ETEMP_INACTIVE: + case ETEMP_NOT_PRESENT: + case ETEMP_CORRUPT: + case ETEMP_NOT_INITIALIZED: + return -EOPNOTSUPP; + case ETEMP_TIMEOUT: + case ETEMP_BUSY: + case ETEMP_TOO_OLD: + return -EAGAIN; + default: + /* SDM returns a 16-bit signed Q8.8 value in the low 16 bits. */ + *val =3D (long)(s16)(temperature & SOCFPGA_HWMON_CHANNEL_MASK) * + SOCFPGA_HWMON_TEMP_MDEG_SCALE / SOCFPGA_HWMON_TEMP_FRAC_DIV; + return 0; + } +} + +static int socfpga_hwmon_encode_temp_arg(u32 reg, u64 *arg) +{ + u32 page =3D (reg >> SOCFPGA_HWMON_PAGE_SHIFT) & SOCFPGA_HWMON_CHANNEL_MA= SK; + u32 channel =3D reg & SOCFPGA_HWMON_CHANNEL_MASK; + + if (channel >=3D SOCFPGA_HWMON_MAXSENSORS) + return -EINVAL; + + *arg =3D (1ULL << channel) | ((u64)page << SOCFPGA_HWMON_PAGE_SHIFT); + return 0; +} + +static int socfpga_hwmon_encode_volt_arg(u32 reg, u64 *arg) +{ + u32 channel =3D reg & SOCFPGA_HWMON_CHANNEL_MASK; + + if (channel >=3D SOCFPGA_HWMON_MAXSENSORS) + return -EINVAL; + + *arg =3D 1ULL << channel; + return 0; +} + +static int socfpga_hwmon_async_read(struct device *dev, + enum hwmon_sensor_types type, + struct stratix10_svc_client_msg *msg) +{ + struct socfpga_hwmon_priv *priv =3D dev_get_drvdata(dev); + struct stratix10_svc_cb_data data =3D {}; + unsigned long deadline =3D jiffies + HWMON_TIMEOUT; + void *handle =3D NULL; + int status, index, ret; + + for (index =3D 0; index < HWMON_ASYNC_MSG_RETRY; index++) { + status =3D stratix10_svc_async_send(priv->chan, msg, &handle, + NULL, NULL); + if (status =3D=3D 0) + break; + dev_warn(dev, "Failed to send async message: %d\n", status); + msleep(HWMON_RETRY_SLEEP_MS); + } + + if (status && !handle) { + dev_err(dev, "Failed to send async message after %u retries: %d\n", + HWMON_ASYNC_MSG_RETRY, status); + return status; + } + + ret =3D -ETIMEDOUT; + while (!time_after(jiffies, deadline)) { + status =3D stratix10_svc_async_poll(priv->chan, handle, &data); + if (status =3D=3D -EAGAIN) { + dev_dbg(dev, "Async message is still in progress\n"); + } else if (status < 0) { + dev_alert(dev, "Failed to poll async message: %d\n", status); + ret =3D -ETIMEDOUT; + } else if (status =3D=3D 0) { + ret =3D 0; + break; + } + msleep(HWMON_RETRY_SLEEP_MS); + } + + if (ret) { + dev_err(dev, "Failed to get async response\n"); + goto done; + } + + if (data.status) { + dev_err(dev, "%s returned 0x%x from SDM\n", __func__, + data.status); + ret =3D -EFAULT; + goto done; + } + + if (type =3D=3D hwmon_temp) + priv->temperature =3D (u32)*(unsigned long *)data.kaddr1; + else + priv->voltage =3D (u32)*(unsigned long *)data.kaddr1; + + ret =3D 0; + +done: + stratix10_svc_async_done(priv->chan, handle); + return ret; +} + +static int socfpga_hwmon_sync_read(struct device *dev, + enum hwmon_sensor_types type, + struct stratix10_svc_client_msg *msg) +{ + struct socfpga_hwmon_priv *priv =3D dev_get_drvdata(dev); + int ret; + + reinit_completion(&priv->completion); + + if (type =3D=3D hwmon_temp) + priv->client.receive_cb =3D socfpga_hwmon_readtemp_cb; + else + priv->client.receive_cb =3D socfpga_hwmon_readvolt_cb; + + ret =3D stratix10_svc_send(priv->chan, msg); + if (ret < 0) + goto status_done; + + ret =3D wait_for_completion_timeout(&priv->completion, HWMON_TIMEOUT); + if (!ret) { + dev_err(priv->client.dev, "timeout waiting for SMC call\n"); + ret =3D -ETIMEDOUT; + goto status_done; + } + + ret =3D priv->last_err; + +status_done: + stratix10_svc_done(priv->chan); + return ret; +} + +static int socfpga_hwmon_read(struct device *dev, enum hwmon_sensor_types = type, + u32 attr, int chan, long *val) +{ + struct socfpga_hwmon_priv *priv =3D dev_get_drvdata(dev); + struct stratix10_svc_client_msg msg =3D {0}; + int ret; + + if (chan >=3D SOCFPGA_HWMON_MAXSENSORS) + return -EOPNOTSUPP; + + switch (type) { + case hwmon_temp: + ret =3D socfpga_hwmon_encode_temp_arg(priv->temp_chan[chan], + &msg.arg[0]); + if (ret) + return ret; + msg.command =3D COMMAND_HWMON_READTEMP; + break; + case hwmon_in: + ret =3D socfpga_hwmon_encode_volt_arg(priv->volt_chan[chan], + &msg.arg[0]); + if (ret) + return ret; + msg.command =3D COMMAND_HWMON_READVOLT; + break; + default: + return -EOPNOTSUPP; + } + + guard(mutex)(&priv->lock); + if (priv->async) + ret =3D socfpga_hwmon_async_read(dev, type, &msg); + else + ret =3D socfpga_hwmon_sync_read(dev, type, &msg); + if (ret) + return ret; + + if (type =3D=3D hwmon_temp) + ret =3D socfpga_hwmon_parse_temp(val, priv->temperature); + else + /* SDM returns Q16 volts; convert to hwmon millivolts. */ + *val =3D (long)priv->voltage * SOCFPGA_HWMON_VOLT_MV_SCALE / + SOCFPGA_HWMON_VOLT_FRAC_DIV; + return ret; +} + +static int socfpga_hwmon_read_string(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int chan, const char **str) +{ + struct socfpga_hwmon_priv *priv =3D dev_get_drvdata(dev); + + switch (type) { + case hwmon_in: + *str =3D priv->volt_chan_names[chan]; + return 0; + case hwmon_temp: + *str =3D priv->temp_chan_names[chan]; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static const struct hwmon_ops socfpga_hwmon_ops =3D { + .is_visible =3D socfpga_hwmon_is_visible, + .read =3D socfpga_hwmon_read, + .read_string =3D socfpga_hwmon_read_string, +}; + +static const struct hwmon_channel_info *socfpga_hwmon_info[] =3D { + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + NULL +}; + +static const struct hwmon_chip_info socfpga_hwmon_chip_info =3D { + .ops =3D &socfpga_hwmon_ops, + .info =3D socfpga_hwmon_info, +}; + +static const struct socfpga_hwmon_channel s10_hwmon_volt_channels[] =3D { + { SOCFPGA_HWMON_CHAN(0, 2), "0.8V VCC" }, + { SOCFPGA_HWMON_CHAN(0, 3), "1.8V VCCIO_SDM" }, + { SOCFPGA_HWMON_CHAN(0, 6), "0.9V VCCERAM" }, +}; + +static const struct socfpga_hwmon_channel s10_hwmon_temp_channels[] =3D { + { SOCFPGA_HWMON_CHAN(0, 0), "Main Die SDM" }, +}; + +static const struct socfpga_hwmon_board_data s10_hwmon_board =3D { + .temp =3D s10_hwmon_temp_channels, + .num_temp =3D ARRAY_SIZE(s10_hwmon_temp_channels), + .volt =3D s10_hwmon_volt_channels, + .num_volt =3D ARRAY_SIZE(s10_hwmon_volt_channels), +}; + +static const struct socfpga_hwmon_channel agilex_hwmon_volt_channels[] =3D= { + { SOCFPGA_HWMON_CHAN(0, 2), "0.8V VCC" }, + { SOCFPGA_HWMON_CHAN(0, 3), "1.8V VCCIO_SDM" }, + { SOCFPGA_HWMON_CHAN(0, 4), "1.8V VCCPT" }, + { SOCFPGA_HWMON_CHAN(0, 5), "1.2V VCCCRCORE" }, + { SOCFPGA_HWMON_CHAN(0, 6), "0.9V VCCH" }, + { SOCFPGA_HWMON_CHAN(0, 7), "0.8V VCCL" }, +}; + +static const struct socfpga_hwmon_channel agilex_hwmon_temp_channels[] =3D= { + { SOCFPGA_HWMON_CHAN(0, 0), "Main Die SDM" }, + { SOCFPGA_HWMON_CHAN(1, 0), "Main Die corner bottom left max" }, + { SOCFPGA_HWMON_CHAN(2, 0), "Main Die corner top left max" }, + { SOCFPGA_HWMON_CHAN(3, 0), "Main Die corner bottom right max" }, + { SOCFPGA_HWMON_CHAN(4, 0), "Main Die corner top right max" }, +}; + +static const struct socfpga_hwmon_board_data agilex_hwmon_board =3D { + .temp =3D agilex_hwmon_temp_channels, + .num_temp =3D ARRAY_SIZE(agilex_hwmon_temp_channels), + .volt =3D agilex_hwmon_volt_channels, + .num_volt =3D ARRAY_SIZE(agilex_hwmon_volt_channels), +}; + +static const struct socfpga_hwmon_board_data * +socfpga_hwmon_get_board(struct device *dev) +{ + struct device_node *np =3D dev->of_node; + + if (!np) + return NULL; + + if (of_device_is_compatible(np, "intel,stratix10-svc")) + return &s10_hwmon_board; + if (of_device_is_compatible(np, "intel,agilex-svc")) + return &agilex_hwmon_board; + + return NULL; +} + +static int socfpga_hwmon_init_channels(struct device *dev, + const struct socfpga_hwmon_board_data *board, + struct socfpga_hwmon_priv *priv) +{ + unsigned int i; + + if (board->num_temp > SOCFPGA_HWMON_MAXSENSORS || + board->num_volt > SOCFPGA_HWMON_MAXSENSORS) + return -EINVAL; + + for (i =3D 0; i < board->num_temp; i++) { + priv->temp_chan_names[i] =3D board->temp[i].label; + priv->temp_chan[i] =3D board->temp[i].reg; + } + priv->temperature_channels =3D board->num_temp; + + for (i =3D 0; i < board->num_volt; i++) { + priv->volt_chan_names[i] =3D board->volt[i].label; + priv->volt_chan[i] =3D board->volt[i].reg; + } + priv->voltage_channels =3D board->num_volt; + + return 0; +} + +static void socfpga_hwmon_release_svc(void *data) +{ + struct socfpga_hwmon_priv *priv =3D data; + + if (priv->async) + stratix10_svc_remove_async_client(priv->chan); + stratix10_svc_free_channel(priv->chan); +} + +static int socfpga_hwmon_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device *parent =3D dev->parent; + const struct socfpga_hwmon_board_data *board; + struct socfpga_hwmon_priv *priv; + struct device *hwmon_dev; + int ret; + + if (!parent || !parent->of_node) { + dev_err(dev, "missing parent device node\n"); + return -ENODEV; + } + + board =3D socfpga_hwmon_get_board(parent); + if (!board) { + dev_err(dev, "unsupported service layer compatible\n"); + return -ENODEV; + } + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->client.dev =3D dev; + priv->client.priv =3D priv; + init_completion(&priv->completion); + mutex_init(&priv->lock); + + ret =3D socfpga_hwmon_init_channels(dev, board, priv); + if (ret) + return ret; + + priv->chan =3D stratix10_svc_request_channel_byname(&priv->client, + SVC_CLIENT_HWMON); + if (IS_ERR(priv->chan)) { + ret =3D PTR_ERR(priv->chan); + if (ret =3D=3D -EPROBE_DEFER) + dev_dbg(dev, "service channel %s not ready, deferring probe\n", + SVC_CLIENT_HWMON); + else + dev_err(dev, "couldn't get service channel %s: %d\n", + SVC_CLIENT_HWMON, ret); + return ret; + } + + ret =3D stratix10_svc_add_async_client(priv->chan, false); + switch (ret) { + case 0: + priv->async =3D true; + break; + case -EINVAL: + case -EOPNOTSUPP: + /* + * stratix10_svc_add_async_client() returns -EINVAL when the + * async controller is not initialized; fall back to sync mode. + */ + dev_dbg(dev, "async operations not supported, using sync mode\n"); + priv->async =3D false; + break; + default: + dev_err(dev, "failed to add async client: %d\n", ret); + stratix10_svc_free_channel(priv->chan); + return ret; + } + + ret =3D devm_add_action_or_reset(dev, socfpga_hwmon_release_svc, priv); + if (ret) + return ret; + + hwmon_dev =3D devm_hwmon_device_register_with_info(dev, "socfpga_hwmon", + priv, + &socfpga_hwmon_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + platform_set_drvdata(pdev, priv); + return 0; +} + +static struct platform_driver socfpga_hwmon_driver =3D { + .probe =3D socfpga_hwmon_probe, + .driver =3D { + .name =3D "socfpga-hwmon", + }, +}; +module_platform_driver(socfpga_hwmon_driver); + +MODULE_AUTHOR("Nazim Amirul "); +MODULE_AUTHOR("Tze Yee Ng "); +MODULE_DESCRIPTION("Altera SoC FPGA hardware monitoring driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:socfpga-hwmon"); --=20 2.43.7