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Unal" , "David S. Miller" , Andrew Lunn , AngeloGioacchino Del Regno , Conor Dooley , DENG Qingfang , Daniel Golle , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Landen Chao , Matthias Brugger , Paolo Abeni , Rob Herring , Russell King , Sean Wang , Vladimir Oltean , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Ahmed Naseef Subject: [PATCH net-next v2 1/2] dt-bindings: net: dsa: mediatek,mt7530: add econet,en7528-switch Date: Sat, 11 Jul 2026 15:41:00 +0400 Message-Id: <2133035bb22eacc8a0e21f86c0c800a45023ee01.1783770059.git.naseefkm@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The EcoNet EN7528 MIPS SoC integrates an MT7530 Gigabit switch, memory-mapped in the SoC register space like the built-in switches of the MediaTek MT7988 and Airoha EN7581/AN7583 SoCs. Its four user ports are connected to integrated Gigabit PHYs and its CPU port is connected internally to the SoC Ethernet MAC. Those three switches are MT7531-based, whereas the EN7528 has a genuine MT7530 switch core (its chip revision register reads 0x7530). The two generations differ in their register programming - for example the CPU port is selected through the MT7530-style MFC register rather than the MT7531 CFC register - so the EN7528 is not compatible with the existing switch compatibles and cannot fall back to one of them. Add the econet,en7528-switch compatible, with the same constraints as the other built-in switches. Signed-off-by: Ahmed Naseef Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 815a90808901..90b3582b7619 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -100,6 +100,10 @@ properties: Built-in switch of the Airoha AN7583 SoC const: airoha,an7583-switch =20 + - description: + Built-in switch of the EcoNet EN7528 SoC + const: econet,en7528-switch + reg: maxItems: 1 =20 @@ -318,6 +322,7 @@ allOf: - mediatek,mt7988-switch - airoha,en7581-switch - airoha,an7583-switch + - econet,en7528-switch then: $ref: "#/$defs/builtin-dsa-port" properties: --=20 2.34.1 From nobody Sat Jul 25 23:41:31 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA2B23C10B9 for ; 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Sat, 11 Jul 2026 04:41:31 -0700 (PDT) Received: from DESKTOP-TIT0J8O.dm.ae ([49.47.198.15]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-311935fd091sm32390087eec.24.2026.07.11.04.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jul 2026 04:41:30 -0700 (PDT) From: Ahmed Naseef To: netdev@vger.kernel.org Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , "Chester A. Unal" , "David S. Miller" , Andrew Lunn , AngeloGioacchino Del Regno , Conor Dooley , DENG Qingfang , Daniel Golle , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Landen Chao , Matthias Brugger , Paolo Abeni , Rob Herring , Russell King , Sean Wang , Vladimir Oltean , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Ahmed Naseef Subject: [PATCH net-next v2 2/2] net: dsa: mt7530: add EN7528 support Date: Sat, 11 Jul 2026 15:41:01 +0400 Message-Id: <8c7dfabd860ab0a6dd771c2bac7b7599eb369a4f.1783770059.git.naseefkm@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The EcoNet EN7528 SoC integrates an MT7530 switch (the chip revision register reads 0x7530), memory-mapped in the SoC register space and reached through the same MMIO glue used for the built-in switches of the MediaTek MT7988 and Airoha EN7581/AN7583 SoCs. Its reset sequence and its PHY indirect access registers are the same as on those switches, so add an ID_EN7528 variant bound with the "econet,en7528-switch" compatible, reusing mt7988_setup() and the indirect PHY accessors. The switch core, however, is an MT7530 and not an MT7531 derivative: the CPU port to trap frames to is set through the MT7530-style CPU_EN / CPU_PORT fields of the MFC register rather than the MT7531 CFC register, so add it to the MT7530 handling in mt753x_conduit_state_change(). For the same reason the MT7530 mirror and force-mode register layouts already apply to it as the default of the MT753X_*() macros. The four user ports (1-4) are connected to integrated Gigabit PHYs at MDIO addresses 9-12 of the switch internal MDIO bus. The CPU port (port 6) is connected to the SoC Ethernet MAC at a fixed 1000 Mbps full duplex link, so the port capabilities cannot be shared with the MT7988 and EN7581 switches, whose CPU ports run at 10 Gbps. The LAN GPHYs advertise EEE by default, but negotiating EEE with some link partners results in an unstable link with dropped frames. Leave the LPI capabilities empty for the EN7528 so that phylink disables EEE on these PHYs and refuses to enable it from userspace. Signed-off-by: Ahmed Naseef --- drivers/net/dsa/mt7530-mmio.c | 1 + drivers/net/dsa/mt7530.c | 58 ++++++++++++++++++++++++++++++----- drivers/net/dsa/mt7530.h | 1 + 3 files changed, 52 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mt7530-mmio.c index 1dc8b93fb51a..1065671bcdd1 100644 --- a/drivers/net/dsa/mt7530-mmio.c +++ b/drivers/net/dsa/mt7530-mmio.c @@ -13,6 +13,7 @@ static const struct of_device_id mt7988_of_match[] =3D { { .compatible =3D "airoha,an7583-switch", .data =3D &mt753x_table[ID_AN75= 83], }, { .compatible =3D "airoha,en7581-switch", .data =3D &mt753x_table[ID_EN75= 81], }, + { .compatible =3D "econet,en7528-switch", .data =3D &mt753x_table[ID_EN75= 28], }, { .compatible =3D "mediatek,mt7988-switch", .data =3D &mt753x_table[ID_MT= 7988], }, { /* sentinel */ }, }; diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 3c2a3029b10c..6c8ed00ee9e7 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2912,6 +2912,30 @@ static void en7581_mac_port_get_caps(struct dsa_swit= ch *ds, int port, } } =20 +static void en7528_mac_port_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + switch (port) { + /* Ports which are connected to switch PHYs. There is no MII pinout. */ + case 1 ... 4: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + + config->mac_capabilities |=3D MAC_10 | MAC_100 | MAC_1000FD; + break; + + /* Port 6 is connected to SoC's GMAC at 1000 Mbps full duplex. There + * is no MII pinout. + */ + case 6: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + + config->mac_capabilities |=3D MAC_1000FD; + break; + } +} + static void mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -3101,17 +3125,24 @@ static void mt753x_phylink_get_caps(struct dsa_swit= ch *ds, int port, struct phylink_config *config) { struct mt7530_priv *priv =3D ds->priv; - u32 eeecr; =20 config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE; =20 - config->lpi_capabilities =3D MAC_100FD | MAC_1000FD | MAC_2500FD; - - eeecr =3D mt7530_read(priv, MT753X_PMEEECR_P(port)); - /* tx_lpi_timer should be in microseconds. The time units for - * LPI threshold are unspecified. + /* The EN7528 GPHYs report EEE capability, but negotiating EEE with + * common link partners (e.g. Realtek GbE NICs) results in an unstable + * link with dropped frames. Leave the LPI capabilities empty so that + * phylink disables EEE on these PHYs and refuses to enable it from + * userspace. */ - config->lpi_timer_default =3D FIELD_GET(LPI_THRESH_MASK, eeecr); + if (priv->id !=3D ID_EN7528) { + u32 eeecr =3D mt7530_read(priv, MT753X_PMEEECR_P(port)); + + config->lpi_capabilities =3D MAC_100FD | MAC_1000FD | MAC_2500FD; + /* tx_lpi_timer should be in microseconds. The time units for + * LPI threshold are unspecified. + */ + config->lpi_timer_default =3D FIELD_GET(LPI_THRESH_MASK, eeecr); + } =20 priv->info->mac_port_get_caps(ds, port, config); } @@ -3254,7 +3285,8 @@ mt753x_conduit_state_change(struct dsa_switch *ds, * forwarded to the numerically smallest CPU port whose conduit * interface is up. */ - if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621) + if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621 && + priv->id !=3D ID_EN7528) return; =20 mask =3D BIT(cpu_dp->index); @@ -3459,6 +3491,16 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c45 =3D mt7531_ind_c45_phy_write, .mac_port_get_caps =3D en7581_mac_port_get_caps, }, + [ID_EN7528] =3D { + .id =3D ID_EN7528, + .pcs_ops =3D &mt7530_pcs_ops, + .sw_setup =3D mt7988_setup, + .phy_read_c22 =3D mt7531_ind_c22_phy_read, + .phy_write_c22 =3D mt7531_ind_c22_phy_write, + .phy_read_c45 =3D mt7531_ind_c45_phy_read, + .phy_write_c45 =3D mt7531_ind_c45_phy_write, + .mac_port_get_caps =3D en7528_mac_port_get_caps, + }, }; EXPORT_SYMBOL_GPL(mt753x_table); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index dd33b0df3419..5f1e841f42c0 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -21,6 +21,7 @@ enum mt753x_id { ID_MT7988 =3D 3, ID_EN7581 =3D 4, ID_AN7583 =3D 5, + ID_EN7528 =3D 6, }; =20 #define NUM_TRGMII_CTRL 5 --=20 2.34.1