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charset="utf-8" Some SPI controllers allow multiple CS lines to be toggled at the same time. The existing code always used CS index 0 when tracking the last active CS in spi_set_cs(), and unconditionally set cs_index_mask to BIT(0) when parsing DT, both forcing the single CS usage. Modify spi_set_cs() to iterate last_cs[] using each logical CS index instead of always reading index 0. Modify of_spi_parse_dt() to build cs_index_mask from all parsed CS entries rather than hardcoding BIT(0), so the controller correctly identifies which CS lines belong to a device when asserting them simultaneously. Signed-off-by: Jonathan Santos Acked-by: Nuno S=C3=A1 --- drivers/spi/spi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index d9e6b4b87c89..55fb96fea243 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1090,7 +1090,7 @@ static void spi_set_cs(struct spi_device *spi, bool e= nable, bool force) spi->controller->last_cs_index_mask =3D spi->cs_index_mask; for (idx =3D 0; idx < SPI_DEVICE_CS_CNT_MAX; idx++) { if (enable && idx < spi->num_chipselect) - spi->controller->last_cs[idx] =3D spi_get_chipselect(spi, 0); + spi->controller->last_cs[idx] =3D spi_get_chipselect(spi, idx); else spi->controller->last_cs[idx] =3D SPI_INVALID_CS; } @@ -2594,10 +2594,11 @@ static int of_spi_parse_dt(struct spi_controller *c= tlr, struct spi_device *spi, spi_set_chipselect(spi, idx, cs[idx]); =20 /* - * By default spi->chip_select[0] will hold the physical CS number, - * so set bit 0 in spi->cs_index_mask. + * Set cs_index_mask to indicate which logical CS indices are active. + * Each bit corresponds to a logical CS index in the spi->chip_select arr= ay. */ - spi->cs_index_mask =3D BIT(0); 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charset="utf-8" Multi-CS devices assert all their chip selects simultaneously by default via cs_index_mask. Some use cases require selecting a subset of those CS lines per transfer (e.g. routing data to one of several subdevices sharing the bus). Add a cs_select_mask field to spi_transfer. When the mask is set and the controller has SPI_CONTROLLER_MULTI_CS, spi_set_cs() builds a temporary spi_device whose chip_select[] and cs_gpiod[] arrays contain only the lines indicated by the mask, then delegates to the renamed _spi_set_cs(). When cs_select_mask is 0 or the controller does not support multi-CS, the device default (cs_index_mask) is used unchanged. Update spi_transfer_one_message() to pass the relevant spi_transfer to every spi_set_cs() call so CS transitions between transfers with different masks are handled correctly. Signed-off-by: Jonathan Santos --- drivers/spi/spi.c | 88 +++++++++++++++++++++++++++++++++++------ include/linux/spi/spi.h | 4 ++ 2 files changed, 81 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 55fb96fea243..6d644adf8445 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1071,7 +1071,7 @@ static void spi_toggle_csgpiod(struct spi_device *spi= , u8 idx, bool enable, bool spi_delay_exec(&spi->cs_inactive, NULL); } =20 -static void spi_set_cs(struct spi_device *spi, bool enable, bool force) +static void _spi_set_cs(struct spi_device *spi, bool enable, bool force) { bool activate =3D enable; u8 idx; @@ -1129,6 +1129,61 @@ static void spi_set_cs(struct spi_device *spi, bool = enable, bool force) } } =20 +static void spi_set_cs(struct spi_device *spi, + struct spi_transfer *xfer, + bool enable, bool force) +{ + struct spi_controller *ctlr =3D spi->controller; + struct spi_device temp_spi; + u8 cs_mask, cs_count, idx; + + /* + * If no transfer-specific CS mask, or device does not support multi-CS, + * fall back to device default + */ + if (!xfer || !(ctlr->flags & SPI_CONTROLLER_MULTI_CS)) + goto out_default_cs; + + if (!xfer->cs_select_mask) + goto out_default_cs; + + /* + * Handle multi-CS controller path. + * For multi-CS controllers, we need to create a temporary spi_device + * structure that reflects the transfer's CS selection + */ + cs_mask =3D xfer->cs_select_mask & spi->cs_index_mask; + temp_spi =3D *spi; + cs_count =3D 0; + + temp_spi.cs_index_mask =3D 0; + for (idx =3D 0; idx < spi->num_chipselect; idx++) { + if (cs_mask & BIT(idx)) { + temp_spi.chip_select[cs_count] =3D spi->chip_select[idx]; + if (spi->cs_gpiod[idx]) + temp_spi.cs_gpiod[cs_count] =3D spi->cs_gpiod[idx]; + temp_spi.cs_index_mask |=3D BIT(cs_count); + cs_count++; + } + } + temp_spi.num_chipselect =3D cs_count; + + _spi_set_cs(&temp_spi, enable, force); + + /* + * Copy the last CS state from temp device back to original controller + * to keep the tracking. + */ + ctlr->last_cs_index_mask =3D temp_spi.controller->last_cs_index_mask; + ctlr->last_cs_mode_high =3D temp_spi.controller->last_cs_mode_high; + memcpy(ctlr->last_cs, temp_spi.controller->last_cs, sizeof(ctlr->last_cs)= ); + + return; + +out_default_cs: + _spi_set_cs(spi, enable, force); +} + #ifdef CONFIG_HAS_DMA static int spi_map_buf_attrs(struct spi_controller *ctlr, struct device *d= ev, struct sg_table *sgt, void *buf, size_t len, @@ -1612,7 +1667,7 @@ static int spi_transfer_one_message(struct spi_contro= ller *ctlr, struct spi_statistics __percpu *stats =3D msg->spi->pcpu_statistics; =20 xfer =3D list_first_entry(&msg->transfers, struct spi_transfer, transfer_= list); - spi_set_cs(msg->spi, !xfer->cs_off, false); + spi_set_cs(msg->spi, xfer, !xfer->cs_off, false); =20 SPI_STATISTICS_INCREMENT_FIELD(statm, messages); SPI_STATISTICS_INCREMENT_FIELD(stats, messages); @@ -1680,28 +1735,39 @@ static int spi_transfer_one_message(struct spi_cont= roller *ctlr, =20 spi_transfer_delay_exec(xfer); =20 + struct spi_transfer *next_xfer =3D list_next_entry(xfer, transfer_list); if (xfer->cs_change) { if (list_is_last(&xfer->transfer_list, &msg->transfers)) { keep_cs =3D true; } else { if (!xfer->cs_off) - spi_set_cs(msg->spi, false, false); + spi_set_cs(msg->spi, xfer, false, false); _spi_transfer_cs_change_delay(msg, xfer); - if (!list_next_entry(xfer, transfer_list)->cs_off) - spi_set_cs(msg->spi, true, false); + if (!next_xfer->cs_off) + spi_set_cs(msg->spi, next_xfer, true, false); } } else if (!list_is_last(&xfer->transfer_list, &msg->transfers) && - xfer->cs_off !=3D list_next_entry(xfer, transfer_list)->cs_off) { - spi_set_cs(msg->spi, xfer->cs_off, false); + xfer->cs_off !=3D next_xfer->cs_off) { + spi_set_cs(msg->spi, next_xfer, xfer->cs_off, false); + } else if (!list_is_last(&xfer->transfer_list, &msg->transfers) && + xfer->cs_select_mask !=3D next_xfer->cs_select_mask) { + /* disable the current xfer CS before enabling the next xfer CS */ + spi_set_cs(msg->spi, xfer, false, false); + spi_set_cs(msg->spi, next_xfer, true, false); } =20 msg->actual_length +=3D xfer->len; } =20 out: - if (ret !=3D 0 || !keep_cs) - spi_set_cs(msg->spi, false, false); + if (ret !=3D 0 || !keep_cs) { + /* Use the last transfer's CS configuration for proper cleanup */ + struct spi_transfer *last_xfer =3D list_last_entry(&msg->transfers, + struct spi_transfer, + transfer_list); + spi_set_cs(msg->spi, last_xfer, false, false); + } =20 if (msg->status =3D=3D -EINPROGRESS) msg->status =3D ret; @@ -4138,10 +4204,10 @@ static int __spi_setup(struct spi_device *spi, bool= initial_setup) */ status =3D 0; =20 - spi_set_cs(spi, false, true); + spi_set_cs(spi, NULL, false, true); pm_runtime_put_autosuspend(spi->controller->dev.parent); } else { - spi_set_cs(spi, false, true); + spi_set_cs(spi, NULL, false, true); } =20 mutex_unlock(&spi->controller->io_mutex); diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 4c285d3ede1d..a9988db3fe2f 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -993,6 +993,9 @@ struct spi_res { * for this transfer. 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charset="utf-8" The AXI SPI Engine controller hardcoded CS index 0 when generating assert commands, so only the first chip select was being toggled even when a device declared multiple CS lines in the device tree. Modify spi_engine_gen_cs() to accept a cs_select_mask argument and iterate all bits set in the effective mask (the intersection of xfer->cs_select_mask with spi->cs_index_mask, falling back to spi->cs_index_mask when the transfer mask is 0). Update spi_engine_compile_message() to pass each transfer's cs_select_mask at every CS transition, including cs_change and cs_select_mask change boundaries between consecutive transfers. Likewise, modify spi_engine_setup() replacing the single-index CS assert with a for_each_set_bit() loop over cs_index_mask. Set SPI_CONTROLLER_MULTI_CS flag in the probe path so the core multi-CS path in spi_set_cs() is activated for this controller. Signed-off-by: Jonathan Santos --- drivers/spi/spi-axi-spi-engine.c | 44 ++++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index 02bbc5d0cfc5..f2d0a6dd593b 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -46,6 +46,7 @@ #define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec =20 #define SPI_ENGINE_MAX_NUM_OFFLOADS 32 +#define SPI_ENGINE_MAX_CS 8 =20 #define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + SPI_ENGINE_MAX_NUM_OFFLOA= DS * (x)) #define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + SPI_ENGINE_MAX_NUM_OFFLO= ADS * (x)) @@ -279,12 +280,17 @@ static void spi_engine_gen_sleep(struct spi_engine_pr= ogram *p, bool dry, } =20 static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry, - struct spi_device *spi, bool assert) + struct spi_device *spi, bool assert, unsigned long xfer_cs_mask) { + unsigned long cs_index_mask =3D !xfer_cs_mask + ? spi->cs_index_mask + : spi->cs_index_mask & xfer_cs_mask; unsigned int mask =3D 0xff; + unsigned int cs_bit; =20 if (assert) - mask ^=3D BIT(spi_get_chipselect(spi, 0)); + for_each_set_bit(cs_bit, &cs_index_mask, SPI_ENGINE_MAX_CS) + mask ^=3D BIT(spi_get_chipselect(spi, cs_bit)); =20 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(0, mask)); } @@ -406,7 +412,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, } =20 xfer =3D list_first_entry(&msg->transfers, struct spi_transfer, transfer_= list); - spi_engine_gen_cs(p, dry, spi, !xfer->cs_off); + spi_engine_gen_cs(p, dry, spi, !xfer->cs_off, xfer->cs_select_mask); =20 list_for_each_entry(xfer, &msg->transfers, transfer_list) { if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || @@ -451,28 +457,33 @@ static void spi_engine_compile_message(struct spi_mes= sage *msg, bool dry, spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 + struct spi_transfer *next_xfer =3D list_next_entry(xfer, transfer_list); if (xfer->cs_change) { if (list_is_last(&xfer->transfer_list, &msg->transfers)) { keep_cs =3D true; } else { if (!xfer->cs_off) - spi_engine_gen_cs(p, dry, spi, false); + spi_engine_gen_cs(p, dry, spi, false, xfer->cs_select_mask); =20 spi_engine_gen_sleep(p, dry, spi_delay_to_ns( &xfer->cs_change_delay, xfer), inst_ns, xfer->effective_speed_hz); =20 - if (!list_next_entry(xfer, transfer_list)->cs_off) - spi_engine_gen_cs(p, dry, spi, true); + if (!next_xfer->cs_off) + spi_engine_gen_cs(p, dry, spi, true, + next_xfer->cs_select_mask); } } else if (!list_is_last(&xfer->transfer_list, &msg->transfers) && - xfer->cs_off !=3D list_next_entry(xfer, transfer_list)->cs_off) { - spi_engine_gen_cs(p, dry, spi, xfer->cs_off); + xfer->cs_off !=3D next_xfer->cs_off) { + spi_engine_gen_cs(p, dry, spi, xfer->cs_off, xfer->cs_select_mask); + } else if (!list_is_last(&xfer->transfer_list, &msg->transfers) && + xfer->cs_select_mask !=3D next_xfer->cs_select_mask) { + spi_engine_gen_cs(p, dry, spi, true, next_xfer->cs_select_mask); } } =20 if (!keep_cs) - spi_engine_gen_cs(p, dry, spi, false); + spi_engine_gen_cs(p, dry, spi, false, 0); =20 /* * Restore clockdiv to default so that future gen_sleep commands don't @@ -886,12 +897,18 @@ static int spi_engine_setup(struct spi_device *device) { struct spi_controller *host =3D device->controller; struct spi_engine *spi_engine =3D spi_controller_get_devdata(host); + unsigned long cs_index_mask =3D device->cs_index_mask; unsigned int reg; + u32 cs_bit; =20 - if (device->mode & SPI_CS_HIGH) - spi_engine->cs_inv |=3D BIT(spi_get_chipselect(device, 0)); - else - spi_engine->cs_inv &=3D ~BIT(spi_get_chipselect(device, 0)); + for_each_set_bit(cs_bit, &cs_index_mask, SPI_ENGINE_MAX_CS) { + if (device->mode & SPI_CS_HIGH) + spi_engine->cs_inv |=3D BIT(spi_get_chipselect(device, + cs_bit)); + else + spi_engine->cs_inv &=3D ~BIT(spi_get_chipselect(device, + cs_bit)); + } =20 writel_relaxed(SPI_ENGINE_CMD_SYNC(0), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); @@ -1222,6 +1239,7 @@ static int spi_engine_probe(struct platform_device *p= dev) host->unoptimize_message =3D spi_engine_unoptimize_message; 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charset="utf-8" Document that when either rx_lane_mask or tx_lane_mask is non-zero, STRIPE operates only over the active lanes indicated by the mask. The transfer buffer must be sized as a multiple of the active lane count rather than the total lane count. To maintain backwards compatibility, when both masks are zero, the default behavior is to enable all lanes. Signed-off-by: Jonathan Santos --- Documentation/spi/multiple-data-lanes.rst | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/spi/multiple-data-lanes.rst b/Documentation/spi/= multiple-data-lanes.rst index 69cb532d052f..578a6a8e4380 100644 --- a/Documentation/spi/multiple-data-lanes.rst +++ b/Documentation/spi/multiple-data-lanes.rst @@ -200,6 +200,36 @@ The possible values for this field have the following = semantics: After the transfer, ``rx_buf[0] =3D=3D 0x11`` (word from SDO 0) and ``rx_buf[1] =3D=3D 0x88`` (word from SDO 1). =20 + When ``rx_lane_mask`` or ``tx_lane_mask`` is set, STRIPE operates over + active lanes only. Buffer size must be sized as a multiple of the numb= er + of active lanes, not the total number of lanes. The mask must be a sub= set + of the total lanes, bits that correspond to lanes not defined for the = device + are ignored. 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charset="utf-8" In SPI_MULTI_LANE_MODE_STRIPE mode, a transfer currently activates all available lanes, but some use cases require operating over a subset of lanes per transfer. Enable dynamic lane selection for tx and rx by adding new fields to the spi_transfer struct. Controllers that support multi-lane selection must parse the transfer struct to update the rx and tx mask lane-wise. Peripherals need to set values to the new fields only if multi_lane_mode is set to SPI_MULTI_LANE_MODE_STRIPE and they need to enable at least one lane, not necessary for enabling all lanes. Signed-off-by: Jonathan Santos Acked-by: Nuno S=C3=A1 --- include/linux/spi/spi.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index a9988db3fe2f..f4473d53b6b5 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -986,6 +986,12 @@ struct spi_res { * (SPI_NBITS_SINGLE) is used. * @multi_lane_mode: How to serialize data on multiple lanes. One of the * SPI_MULTI_LANE_MODE_* values. + * @rx_lane_mask: Bitmask of lanes to use for receive in + * SPI_MULTI_LANE_MODE_STRIPE mode. Each set bit enables the correspo= nding + * lane. If 0 all available lanes are used. + * @tx_lane_mask: Bitmask of lanes to use for transmit in + * SPI_MULTI_LANE_MODE_STRIPE mode. Each set bit enables the correspo= nding + * lane. If 0 all available lanes are used. * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. 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charset="utf-8" In SPI_MULTI_LANE_MODE_STRIPE mode, a transfer currently activates all available lanes. Some use cases require operating over a subset of lanes per transfer. Make use of the rx_lane_mask and tx_lane_mask to allow setting the multi-lane configuration transfer-wise. Rename rx_all_lanes_mask and tx_all_lanes_mask in spi_engine_offload to rx_lanes_mask and tx_lanes_mask, as these fields now hold the active lane mask for the message rather than all available lanes. Signed-off-by: Jonathan Santos Acked-by: Nuno S=C3=A1 --- drivers/spi/spi-axi-spi-engine.c | 62 ++++++++++++++++++++++++++------ 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index f2d0a6dd593b..d6c5264fee9a 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -115,6 +115,10 @@ #define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 #define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 =20 +/* Extending lane_mask values for optimizing messages. */ +#define SPI_ENGINE_LANE_MASK_UNKNOWN -1 +#define SPI_ENGINE_LANE_MASK_CONFLICTING -2 + struct spi_engine_program { unsigned int length; uint16_t instructions[] __counted_by(length); @@ -155,8 +159,8 @@ struct spi_engine_offload { unsigned int multi_lane_mode; u8 rx_primary_lane_mask; u8 tx_primary_lane_mask; - u8 rx_all_lanes_mask; - u8 tx_all_lanes_mask; + u8 rx_lanes_mask; + u8 tx_lanes_mask; u8 bits_per_word; }; =20 @@ -312,6 +316,8 @@ static int spi_engine_precompile_message(struct spi_mes= sage *msg) unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_hz; struct spi_transfer *xfer; int multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; + int rx_lane_mask =3D SPI_ENGINE_LANE_MASK_UNKNOWN; + int tx_lane_mask =3D SPI_ENGINE_LANE_MASK_UNKNOWN; u8 min_bits_per_word =3D U8_MAX; u8 max_bits_per_word =3D 0; =20 @@ -339,11 +345,21 @@ static int spi_engine_precompile_message(struct spi_m= essage *msg) return -EINVAL; } =20 - /* If all xfers have the same multi-lane mode, we can optimize. */ + /* If all xfers have the same multi-lane mode and mask, we can optimize= . */ if (multi_lane_mode =3D=3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN) multi_lane_mode =3D xfer->multi_lane_mode; else if (multi_lane_mode !=3D xfer->multi_lane_mode) multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING; + + if (rx_lane_mask =3D=3D SPI_ENGINE_LANE_MASK_UNKNOWN) + rx_lane_mask =3D xfer->rx_lane_mask; + else if (xfer->rx_lane_mask !=3D rx_lane_mask) + rx_lane_mask =3D SPI_ENGINE_LANE_MASK_CONFLICTING; + + if (tx_lane_mask =3D=3D SPI_ENGINE_LANE_MASK_UNKNOWN) + tx_lane_mask =3D xfer->tx_lane_mask; + else if (xfer->tx_lane_mask !=3D tx_lane_mask) + tx_lane_mask =3D SPI_ENGINE_LANE_MASK_CONFLICTING; } } =20 @@ -364,8 +380,13 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) &priv->rx_primary_lane_mask, &priv->tx_primary_lane_mask); spi_engine_all_lanes_flags(msg->spi, - &priv->rx_all_lanes_mask, - &priv->tx_all_lanes_mask); + &priv->rx_lanes_mask, + &priv->tx_lanes_mask); + if (rx_lane_mask > 0) + priv->rx_lanes_mask &=3D rx_lane_mask; + + if (tx_lane_mask > 0) + priv->tx_lanes_mask &=3D tx_lane_mask; } =20 return 0; @@ -380,6 +401,9 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, struct spi_transfer *xfer; int clk_div, new_clk_div, inst_ns; int prev_multi_lane_mode =3D SPI_MULTI_LANE_MODE_SINGLE; + int prev_rx_lane_mask =3D 0; + int prev_tx_lane_mask =3D 0; + u8 num_rx_active_lanes; bool keep_cs =3D false; u8 bits_per_word =3D 0; =20 @@ -405,6 +429,8 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, */ bits_per_word =3D priv->bits_per_word; prev_multi_lane_mode =3D priv->multi_lane_mode; + prev_rx_lane_mask =3D priv->rx_lanes_mask; + prev_tx_lane_mask =3D priv->tx_lanes_mask; } else { spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, @@ -417,15 +443,27 @@ static void spi_engine_compile_message(struct spi_mes= sage *msg, bool dry, list_for_each_entry(xfer, &msg->transfers, transfer_list) { if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { - if (xfer->multi_lane_mode !=3D prev_multi_lane_mode) { + num_rx_active_lanes =3D spi->num_rx_lanes; + + if (xfer->multi_lane_mode !=3D prev_multi_lane_mode || + xfer->rx_lane_mask !=3D prev_rx_lane_mask || + xfer->tx_lane_mask !=3D prev_tx_lane_mask) { u8 tx_lane_flags, rx_lane_flags; =20 - if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { spi_engine_all_lanes_flags(spi, &rx_lane_flags, &tx_lane_flags); - else + if (xfer->rx_lane_mask) { + rx_lane_flags &=3D xfer->rx_lane_mask; + num_rx_active_lanes =3D hweight8(rx_lane_flags); + } + + if (xfer->tx_lane_mask) + tx_lane_flags &=3D xfer->tx_lane_mask; + } else { spi_engine_primary_lane_flag(spi, &rx_lane_flags, &tx_lane_flags); + } =20 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, @@ -435,6 +473,8 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, tx_lane_flags)); } prev_multi_lane_mode =3D xfer->multi_lane_mode; + prev_rx_lane_mask =3D xfer->rx_lane_mask; + prev_tx_lane_mask =3D xfer->tx_lane_mask; } =20 new_clk_div =3D host->max_speed_hz / xfer->effective_speed_hz; @@ -453,7 +493,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, bits_per_word)); } =20 - spi_engine_gen_xfer(p, dry, xfer, spi->num_rx_lanes); + spi_engine_gen_xfer(p, dry, xfer, num_rx_active_lanes); spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 @@ -1034,10 +1074,10 @@ static int spi_engine_trigger_enable(struct spi_off= load *offload) =20 if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, - priv->rx_all_lanes_mask), + priv->rx_lanes_mask), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, - priv->tx_all_lanes_mask), + priv->tx_lanes_mask), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); } =20 --=20 2.34.1