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Piccoli" , Conor Dooley Subject: [PATCH v3 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62 Date: Fri, 10 Jul 2026 19:43:07 +0200 Message-ID: <10775b12b801255546c9cdefdb153e421aedf910.1783689915.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Acked-by: Conor Dooley From: Stefano Radaelli Add devicetree bindings for Variscite VAR-SOM-AM62 System on Module and its carrier boards. Signed-off-by: Stefano Radaelli --- v2->v3: -=20 v1->v2: -=20 Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index 69b5441cbf1a..b9da6e62ab79 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -104,6 +104,12 @@ properties: - const: tq,am625-tqma6254 - const: ti,am625 =20 + - description: K3 AM625 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62-symphony + - const: variscite,var-som-am62 + - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boar= ds items: - enum: --=20 2.47.3 From nobody Sun Jul 26 00:19:22 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A69376A06 for ; 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Fri, 10 Jul 2026 10:43:20 -0700 (PDT) Received: from GLaDOS.station ([185.81.127.246]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47a9de1d91bsm67170201f8f.4.2026.07.10.10.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 10:43:19 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, matthias.p@variscite.com, Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Subject: [PATCH v3 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62 Date: Fri, 10 Jul 2026 19:43:08 +0200 Message-ID: X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite VAR-SOM-AM62 system on module. This SOM is designed to be used with various carrier boards. The module includes: - AM62x Sitara MPU processor - Up to 4GB of DDR4-3733 memory - Up to 128GB eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices - Audio codec wm8904 - Resistive touch panel interface controller - I2C, UART and SPI interfaces - Bluetooth 5.2 + WiFi single or dual band Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am= 62/ Signed-off-by: Stefano Radaelli --- v2->v3: - Add audio_refclk1 clock - Removed pinctrl_vdd_mmc2 v1->v2: - Fix AM62X_MCU_IOPAD macro - Fix OPP table comment - Remove reg_vdd_mmc2 regulator arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi | 483 +++++++++++++++++++ 1 file changed, 483 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi b/arch/arm64/boot= /dts/ti/k3-am625-var-som.dtsi new file mode 100644 index 000000000000..c2daa56c35e1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for Variscite VAR-SOM-AM62 + * + * Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-so= m-am62/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * Copyright (C) 2026 Stefano Radaelli + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible =3D "variscite,var-som-am62", "ti,am625"; + + memory@80000000 { + /* 2G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type =3D "memory"; + bootph-pre-ram; + }; + + mmc_pwrseq: mmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc_pwrseq>; + reset-gpios =3D <&main_gpio0 49 GPIO_ACTIVE_LOW>; + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ramoops@9ca00000 { + compatible =3D "ramoops"; + reg =3D <0x00 0x9ca00000 0x00 0x00100000>; + record-size =3D <0x8000>; + console-size =3D <0x8000>; + ftrace-size =3D <0x00>; + pmsg-size =3D <0x8000>; + }; + + /* global cma region */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x00 0x8000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + alignment =3D <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment =3D <0x1000>; + no-map; + }; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "On-module +V1.8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "On-module +V3.3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_phy: regulator-3v3-phy { + compatible =3D "regulator-fixed"; + regulator-name =3D "On-module +V3.3_PHY"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eth_phy>; + gpios =3D <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,format =3D "dsp_b"; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,name =3D "wm8904-audio"; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,routing =3D + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets =3D + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai =3D <&mcasp1>; + }; + }; +}; + +&audio_refclk1 { + assigned-clock-rates =3D <12000000>; +}; + +&cpsw3g { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rgmii1>; + status =3D "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mdio1>; + status =3D "okay"; + + cpsw3g_phy0: ethernet-phy@4 { + compatible =3D "ethernet-phy-id0283.bc30"; + reg =3D <4>; + bootph-all; + reset-gpios =3D <&main_gpio0 46 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <20000>; + }; +}; + +&cpsw_port1 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <&cpsw3g_phy0>; + status =3D "okay"; +}; + +&main_i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <400000>; + status =3D "okay"; + + wm8904: audio-codec@1a { + compatible =3D "wlf,wm8904"; + reg =3D <0x1a>; + #sound-dai-cells =3D <0>; + clocks =3D <&audio_refclk1>; + clock-names =3D "mclk"; + AVDD-supply =3D <®_1v8>; + CPVDD-supply =3D <®_1v8>; + DBVDD-supply =3D <®_3v3>; + DCVDD-supply =3D <®_1v8>; + MICVDD-supply =3D <®_1v8>; + wlf,drc-cfg-names =3D "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP =3D 0, KNEE_OP =3D 0, HI_COMP =3D 1, LO_COMP =3D 1 + * KNEE_IP =3D -24, KNEE_OP =3D -6, HI_COMP =3D 1/4, LO_COMP =3D 1 + * KNEE_IP =3D -42, KNEE_OP =3D -3, HI_COMP =3D 0, LO_COMP =3D 1 + * KNEE_IP =3D -45, KNEE_OP =3D -9, HI_COMP =3D 1/8, LO_COMP =3D 1 + * KNEE_IP =3D -30, KNEE_OP =3D -10.5, HI_COMP =3D 1/4, LO_COMP =3D 1 + */ + wlf,drc-cfg-regs =3D /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 =3D DMIC_CLK, don't touch others */ + wlf,gpio-cfg =3D <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&main_i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&main_pmx0 { + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ + AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ + >; + }; + + pinctrl_mcasp1: main-mcasp1-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX = */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1= */ + >; + }; + + pinctrl_mdio1: main-mdio1-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x160, PIN_INPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + pinctrl_mmc_pwrseq: pinmux-mmc-pwrseq-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (Y25) VOUT0_DATA4.GPIO0_49 */ + >; + }; + + pinctrl_mmc0: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + pinctrl_mmc2: main-mmc2-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x120, PIN_INPUT_PULLUP, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT_PULLDOWN, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT_PULLUP, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT_PULLUP, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT_PULLUP, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT_PULLUP, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT_PULLUP, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + pinctrl_restouch: main-restouch-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (W24) VOUT0_DATA3.GPIO0_48 = */ + >; + }; + + pinctrl_rgmii1: main-rgmii1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_INPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_INPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_INPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_INPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_INPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_INPUT, 0) /* (AD19) RGMII1_TX_CTL */ + AM62X_IOPAD(0x00bc, PIN_INPUT, 7) /* (V24) VOUT0_DATA1.GPIO0_46 */ + >; + }; + + pinctrl_eth_phy: main-eth-phy-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x00b8, PIN_INPUT, 7) /* (U22) VOUT0_DATA0.GPIO0_45 */ + >; + }; + + pinctrl_spi0: main-spi0-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */ + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */ + AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 */ + AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */ + >; + }; + + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x00ec, PIN_INPUT, 4) /* (AA24) VOUT0_DATA13.UART5_CTSn */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AB25) VOUT0_DATA12.UART5_RTSn */ + AM62X_IOPAD(0x00d0, PIN_INPUT, 4) /* (Y23) VOUT0_DATA6.UART5_RXD */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AA25) VOUT0_DATA7.UART5_TXD */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_wkup_clkout0: wkup-clkout0-default-pins { + pinctrl-single,pins =3D < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ + >; + }; +}; + +&main_spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi0>; + ti,pindir-d0-out-d1-in; + status =3D "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible =3D "ti,ads7846"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_restouch>; + interrupt-parent =3D <&main_gpio0>; + interrupts =3D <48 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency =3D <1500000>; + pendown-gpio =3D <&main_gpio0 48 GPIO_ACTIVE_LOW>; + ti,x-min =3D /bits/ 16 <125>; + ti,x-max =3D /bits/ 16 <4008>; + ti,y-min =3D /bits/ 16 <282>; + ti,y-max =3D /bits/ 16 <3864>; + ti,x-plate-ohms =3D /bits/ 16 <180>; + ti,pressure-max =3D /bits/ 16 <255>; + ti,debounce-max =3D /bits/ 16 <10>; + ti,debounce-tol =3D /bits/ 16 <3>; + ti,debounce-rep =3D /bits/ 16 <1>; + ti,settle-delay-usec =3D /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +/* On-module Bluetooth */ +&main_uart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>; + uart-has-rtscts; + status =3D "okay"; +}; + +&mcasp1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mcasp1>; + op-mode =3D <0>; /* MCASP_IIS_MODE */ + serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots =3D <2>; + #sound-dai-cells =3D <0>; + status =3D "okay"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc0>; + bootph-all; + disable-wp; + mmc-pwrseq =3D <&mmc_pwrseq>; + non-removable; + status=3D"okay"; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc2>, <&pinctrl_wkup_clkout0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + assigned-clocks =3D <&k3_clks 157 158>; /* wkup_clkout_sel_out0 */ + assigned-clock-parents =3D <&k3_clks 157 164>; /* clk_32k_rc_sel_out0 */ + bus-width =3D <4>; + disable-wp; + non-removable; + cap-power-off-card; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + }; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usbss1 { + ti,vbus-divider; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status =3D "reserved"; +}; + +&mcu_gpio_intr { + status =3D "reserved"; +}; + +&wkup_rtc0 { + status =3D "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status =3D "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status =3D "reserved"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status =3D "reserved"; +}; + +#include "k3-am62-ti-ipc-firmware.dtsi" --=20 2.47.3 From nobody Sun Jul 26 00:19:22 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2FD2377543 for ; Fri, 10 Jul 2026 17:43:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 10 Jul 2026 10:43:21 -0700 (PDT) Received: from GLaDOS.station ([185.81.127.246]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47a9de1d91bsm67170201f8f.4.2026.07.10.10.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 10:43:21 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, matthias.p@variscite.com, Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Subject: [PATCH v3 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board Date: Fri, 10 Jul 2026 19:43:09 +0200 Message-ID: <3f58a10e07d9a353c7c18f7d3ec8ea1f4c08f4f0.1783689915.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62 system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - OV5640 Camera support - GPIO Expander and TPM - CAN, I2C and general purpose interfaces - Capacitive touch controller Link: https://www.variscite.it/product/single-board-computers/symphony-boar= d/ Signed-off-by: Stefano Radaelli --- v2->v3: - Fix reg_sdhc1_vmmc regulator - Add missing properties on pca9534 node v1->v2: - Fix reg_sdhc1_vmmc pinctrl - Add reg_ov5640_buf_en pinctrl arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am625-var-som-symphony.dts | 555 ++++++++++++++++++ 2 files changed, 556 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 371f9a043fe5..e33c4d0363a9 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-beagleplay-csi2-tevi-= ov5640.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-tqma62xx-mba62xx.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-dev-mezzanine-can.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-dev-mezzanine-panel-cap-touch-1= 0inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-dev-nau8822-btl.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts b/arch/ar= m64/boot/dts/ti/k3-am625-var-som-symphony.dts new file mode 100644 index 000000000000..e2fba95d9b94 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Variscite Symphony carrier board for VAR-SOM-AM62 + * + * Link: https://www.variscite.it/product/single-board-computers/symphony-= board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * Copyright (C) 2026 Stefano Radaelli + * + */ + +/dts-v1/; + +#include "k3-am625-var-som.dtsi" + +/ { + model =3D "Variscite VAR-SOM-AM62 on Symphony-Board"; + compatible =3D "variscite,var-som-am62-symphony", "variscite,var-som-am62= ", "ti,am625"; + + aliases { + ethernet0 =3D &cpsw_port1; + ethernet1 =3D &cpsw_port2; + mmc0 =3D &sdhci0; + mmc1 =3D &sdhci1; + mmc2 =3D &sdhci2; + serial0 =3D &main_uart0; + serial2 =3D &main_uart2; + serial5 =3D &main_uart5; + serial6 =3D &main_uart6; + spi5 =3D &main_spi2; + usb0 =3D &usb0; + usb1 =3D &usb1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clk_ov5640_fixed: clock-24000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-back { + label =3D "Back"; + linux,code =3D ; + gpios =3D <&pca9534 1 GPIO_ACTIVE_LOW>; + }; + + button-home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&pca9534 2 GPIO_ACTIVE_LOW>; + }; + + button-menu { + label =3D "Menu"; + linux,code =3D ; + gpios =3D <&pca9534 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-heartbeat { + label =3D "Heartbeat"; + linux,default-trigger =3D "heartbeat"; + gpios =3D <&pca9534 0 GPIO_ACTIVE_LOW>; + }; + }; + + reg_2p8v: regulator-2p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "2P8V"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P5V"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + }; + + reg_sdhc1_vmmc: regulator-sdhc1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V3.3_SD"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sd1_vmmc>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible =3D "regulator-gpio"; + regulator-name =3D "+V3.3_SD_VQMMC"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sd1_vqmmc>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio0 56 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + reg_ov5640_buf_en: regulator-camera-buf-en { + compatible =3D "regulator-fixed"; + regulator-name =3D "ov5640_buf_en"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ov5640_buf>; + gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + connector { + compatible =3D "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_extcon>; + label =3D "USB-C"; + id-gpios =3D <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + port { + usb_con_hs: endpoint { + remote-endpoint =3D <&typec_hs>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cpsw3g { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rgmii1>, + <&pinctrl_rgmii2>; + status =3D "okay"; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps =3D <2 1>; + }; +}; + +&cpsw3g_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mdio1>; + status =3D "okay"; + + cpsw3g_phy1: ethernet-phy@5 { + compatible =3D "ethernet-phy-id0283.bc30"; + reg =3D <5>; + reset-gpios =3D <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + }; +}; + +&cpsw_port2 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the Symphony PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <&cpsw3g_phy1>; + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&epwm1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_epwm1>; +}; + +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c0>; + clock-frequency =3D <400000>; + status =3D "okay"; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible =3D "nxp,pca9534"; + reg =3D <0x20>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pca9534>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <30 IRQ_TYPE_EDGE_FALLING>; + + usb3-sel-hog { + gpio-hog; + gpios =3D <4 0>; + output-low; + line-name =3D "usb3_sel"; + }; + + eth-som-vselect-hog { + gpio-hog; + gpios =3D <6 0>; + output-low; + line-name =3D "eth-vselect"; + }; + + eth-mdio-enable-hog { + gpio-hog; + gpios =3D <7 0>; + output-high; + line-name =3D "eth-mdio-enable"; + }; + }; + + ov5640: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_1p5v>; + powerdown-gpios =3D <&main_gpio0 10 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&main_gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ov5640>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + clock-frequency =3D <400000>; + status =3D "okay"; + + pcal6408: gpio@21 { + compatible =3D "nxp,pcal6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "lvds_brg_en"; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible =3D "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + label =3D "tpm"; + reg =3D <0x2e>; + reset-gpios =3D <&pcal6408 4 GPIO_ACTIVE_LOW>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible =3D "edt,edt-ft5206"; + reg =3D <0x38>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_captouch_pins>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <16 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x =3D <800>; + touchscreen-size-y =3D <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + }; +}; + +&main_mcan0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mcan0>; + phys =3D <&transceiver1>; + status =3D "okay"; +}; + +&main_pmx0 { + pinctrl_captouch_pins: main-captouch-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01b8, PIN_INPUT, 7) /* (C13) SPI0_CS1.GPIO1_16 */ + >; + }; + + pinctrl_epwm1: main-epwm1-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + >; + }; + + pinctrl_extcon: main-extcon-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + pinctrl_i2c0: main-i2c0-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + pinctrl_i2c1: main-i2c1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + pinctrl_mcan0: main-mcan0-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + pinctrl_mmc1: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + + pinctrl_ov5640: main-ov5640-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0028, PIN_OUTPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ + AM62X_IOPAD(0x0058, PIN_OUTPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ + >; + }; + + pinctrl_ov5640_buf: main-ov5640-buf-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0054, PIN_OUTPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + pinctrl_pca9534: main-pca9534-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01f0, PIN_INPUT, 7) /* (A18) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + pinctrl_rgmii2: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_INPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_INPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_INPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_INPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_INPUT_PULLDOWN, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_INPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + pinctrl_sd1_vmmc: main-sd1-vmmc-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ + >; + }; + + pinctrl_sd1_vqmmc: main-sd1-vqmmc-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AA23) VOUT0_DATA11.GPIO0_56 */ + >; + }; + + pinctrl_spi2: main_spi2-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ + AM62X_IOPAD(0x0194, PIN_OUTPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ + AM62X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (E19) MCASP0_AFSR.GPIO1_13 */ + >; + }; + + pinctrl_uart0: main-uart0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD, change muxmode fro= m 0 to 7 to deactivate Debug UART RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (R24) GPMC0_AD8.UART2_RXD */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 2) /* (R25) GPMC0_AD9.UART2_TXD */ + >; + }; + + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x009c, PIN_INPUT, 3) /* (V25) GPMC0_WAIT1.UART6_RXD */ + AM62X_IOPAD(0x0244, PIN_OUTPUT, 1) /* (C17) MMC1_SDWP.UART6_TXD */ + >; + }; + + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; +}; + +&main_spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2>; + ti,pindir-d0-out-d1-in; + cs-gpios =3D <&main_gpio1 13 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart0>; + status =3D "okay"; +}; + +&main_uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&main_uart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart6>; + status =3D "okay"; +}; + +&sdhci1 { + /* SD Card */ + vmmc-supply =3D <®_sdhc1_vmmc>; + vqmmc-supply =3D <®_sdhc1_vqmmc>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc1>; + disable-wp; + bootph-all; + status =3D "okay"; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&usb0 { + usb-role-switch; + status =3D "okay"; + + port { + typec_hs: endpoint { + remote-endpoint =3D <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode =3D "host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1>; + status =3D "okay"; +}; + +&usbss0 { + status =3D "okay"; +}; + +&usbss1 { + status =3D "okay"; +}; --=20 2.47.3