From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A41037881E; Fri, 12 Jun 2026 21:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298136; cv=none; b=h3nfXDTaNl8+AzXDxpQeEzaI8X7xtogim8fIC2PxWOwmGpXUikTDnNBmJ5PNVaHCI5IqMnFFVbl9Gnwx5hF/LTMa4GVrhtq6R5Q4GZd+rkmT90MX1mQfdU+rMSswXwxtjLNdxsfJl72Rxxg5mHsNOWxnfbQcq7DLxER5lWHIFtQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298136; c=relaxed/simple; bh=ryk3p1QXgvdltDJCO5wT0v7qAlVZkkgL5g+SuvOtqHw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LinnDzfB5BRdLh/SbE1CE5TfKMBDnRNaZ+lkm1rednqHwWCazDbrVB2IDy8+DGkIWIVhABMbWgXy2CzXoxjqV75U1iU3w/TX30qUDg5hct2p3CPDrJSjr4ra4XzihROlssPYKDzT/ZhHj9q3aZJTEfBpIt7pk/jrPPc02luJnSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=G4AtpZpV; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="G4AtpZpV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298136; x=1812834136; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ryk3p1QXgvdltDJCO5wT0v7qAlVZkkgL5g+SuvOtqHw=; b=G4AtpZpVWWWUg/K9WUHVTRaSEiFFtkOjTtUug4eZHoPRI6Ovf2uzNUBn wEsDFeYT5FIoAgH2asUKxpslS0jkPQJpRK7I6HElHKWQLkWAqSTQhdbX4 f52Xb42HiyeiFRugx6CVSa2McN8o3QlW2hKFzp6HYcwyJkrw4nGB/wXzL XoJ6VhFLgmo0GmSAjEwLAZvrSvlqZddI0pcLhKlJf3lZUCJ/ezYjJttKL YceKdGcb/dxYyA1RWfb8e0IQQ3bF+fdyiqhiDq/difRHhVzWrpOXvLFZi gC6QwIxeUjoEpm35EFJgKUzyNQZCTEC2ADjL780BOWGefDArM+LnfrX/l Q==; X-CSE-ConnectionGUID: KR7bfJK1SZGNS/GUJSza9w== X-CSE-MsgGUID: rl5XIgh7QBaqkmUv5s9HqA== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037970" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037970" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 X-CSE-ConnectionGUID: 2dB+7sF3QJyttPo7MARGcQ== X-CSE-MsgGUID: Nm2lz0OeQUS2rlJKBg4Qog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832858" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 01/15] platform/x86/intel/pmt: Add pre/post decode hooks around header parsing Date: Fri, 12 Jun 2026 14:01:42 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add optional pre- and post-decode callbacks to the PMT class so namespaces can perform setup and cleanup steps around header parsing. - Add pmt_pre_decode() and pmt_post_decode() to struct intel_pmt_namespace. - Update intel_pmt_dev_create() to invoke, in order: pre =E2=86=92 header_decode() =E2=86=92 post. - Keep the existing pmt_header_decode() callback unchanged. No functional changes. This adds flexibility for upcoming decoders while preserving current behavior. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/class.c | 12 ++++++++++++ drivers/platform/x86/intel/pmt/class.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index b4c9964df807..9b315334a69b 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -381,10 +381,22 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entr= y, struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); =20 + if (ns->pmt_pre_decode) { + ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); + if (ret) + return ret; + } + ret =3D ns->pmt_header_decode(entry, dev); if (ret) return ret; =20 + if (ns->pmt_post_decode) { + ret =3D ns->pmt_post_decode(intel_vsec_dev, entry); + if (ret) + return ret; + } + ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); if (ret) return ret; diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 1ae56a5baad2..ff39014b208c 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -62,6 +62,10 @@ struct intel_pmt_namespace { struct xarray *xa; int (*pmt_header_decode)(struct intel_pmt_entry *entry, struct device *dev); + int (*pmt_pre_decode)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); + int (*pmt_post_decode)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); int (*pmt_add_endpoint)(struct intel_vsec_device *ivdev, struct intel_pmt_entry *entry); }; --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41ADE35F60E; Fri, 12 Jun 2026 21:02:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298135; cv=none; b=TkrrN+rXuvPul7EWZXJAjCSnl6Qhu7MR836ZEYk6q8Kwec0b+TDjnQAytpAYux2a71/AN/xTbeshMg8eqzvhVzI2WfwNtz1kht5pYY4A1b0XWQYHArPXCRnSQXnfV0jI/89TLRNhmkAEact6vJ9NYDkJGeCCL5eoYr5A0g+NL/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298135; c=relaxed/simple; bh=w0YSAiVj+aWjGy+IG/RhPCofXurhZu/fY6mWIwej0ec=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XIPk0rhYRxsYbdTnKN6tb2SLHj09L5mCecBRqggO+4I9Dsq7f9TiOS+/JM8mrYqzxI5r+03STjgVf2/WD6nHEcmkaW99A58VNUwRI7xoeFnsPAtSvURNUZMZrGP3SUbXZk9wad4mHRoRgnCFL/GiaB1bLbRrzXqE7d2KmR45Bqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ESRKjlwy; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ESRKjlwy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298135; x=1812834135; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w0YSAiVj+aWjGy+IG/RhPCofXurhZu/fY6mWIwej0ec=; b=ESRKjlwyJG+4/zYWUf5uMiCzk2avxkyslGMMR8w+4b6QETp4qyYROyu7 FFZEE152VmRFzwdsMYR7nEpb0QHRgZ1v93Wh3Hd3HeA6rMIrUwZb2MShA FGnX1Be8T1e2K5rEf0hXCylleUI5xOBq7asr39ai3jKKQHE3YUeva5/gy gUyq8kcsSLGWFe8TZX1cG8i+sdBHHj1M32N+Ee1jfWeIDEWxXelZ+f4AF IFuBVRjOiG3UuwQUgye7g9fhelYEjSgCidCCtfI7Lnmil1HyMTDLV1fI6 wKWCV3+kywIOaB1XmJI1faKTRbxqqt7FzCYO2DFtGB0Wp7LcuWHqW5Vd9 g==; X-CSE-ConnectionGUID: x78mWO2pQoO/Nq06dSeS4Q== X-CSE-MsgGUID: d4rgHFquS7CVEbSGuDMbnQ== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037973" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037973" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 X-CSE-ConnectionGUID: jqtWjboqS6mFVSXmofDejw== X-CSE-MsgGUID: wEwzG8S9QZeZuPp+3Sf14g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832859" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 02/15] platform/x86/intel/pmt/crashlog: Split init into pre-decode Date: Fri, 12 Jun 2026 14:01:43 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor crashlog initialization to use the PMT namespace pre-decode hook: - Add pmt_crashlog_pre_decode() to parse type/version, select the crashlog_info, initialize the control mutex, and set entry->attr_grp. - Simplify pmt_crashlog_header_decode() to only read header fields from the discovery table. - Wire the namespace with .pmt_pre_decode =3D pmt_crashlog_pre_decode. This separates structural initialization from header parsing, aligning crashlog with the PMT class pre/post decode flow. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/crashlog.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x= 86/intel/pmt/crashlog.c index b0393c9c5b4b..f936daf99e4d 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -496,11 +496,9 @@ static const struct crashlog_info *select_crashlog_inf= o(u32 type, u32 version) return &crashlog_type1_ver2; } =20 -static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, - struct device *dev) +static int pmt_crashlog_pre_decode(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) { - void __iomem *disc_table =3D entry->disc_table; - struct intel_pmt_header *header =3D &entry->header; struct crashlog_entry *crashlog; u32 version; u32 type; @@ -513,6 +511,16 @@ static int pmt_crashlog_header_decode(struct intel_pmt= _entry *entry, mutex_init(&crashlog->control_mutex); =20 crashlog->info =3D select_crashlog_info(type, version); + entry->attr_grp =3D crashlog->info->attr_grp; + + return 0; +} + +static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, + struct device *dev) +{ + void __iomem *disc_table =3D entry->disc_table; + struct intel_pmt_header *header =3D &entry->header; =20 header->access_type =3D GET_ACCESS(readl(disc_table)); header->guid =3D readl(disc_table + GUID_OFFSET); @@ -521,8 +529,6 @@ static int pmt_crashlog_header_decode(struct intel_pmt_= entry *entry, /* Size is measured in DWORDS, but accessor returns bytes */ header->size =3D GET_SIZE(readl(disc_table + SIZE_OFFSET)); =20 - entry->attr_grp =3D crashlog->info->attr_grp; - return 0; } =20 @@ -530,6 +536,7 @@ static DEFINE_XARRAY_ALLOC(crashlog_array); static struct intel_pmt_namespace pmt_crashlog_ns =3D { .name =3D "crashlog", .xa =3D &crashlog_array, + .pmt_pre_decode =3D pmt_crashlog_pre_decode, .pmt_header_decode =3D pmt_crashlog_header_decode, }; =20 --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B96533A717; 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X-CSE-ConnectionGUID: 4QlEQaBzRn28U21kAa0DTw== X-CSE-MsgGUID: M1sKXbi1QhaSbF8hEQh7Dw== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037976" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037976" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 X-CSE-ConnectionGUID: YeUhuK6WSpyGMuzOqyVYRw== X-CSE-MsgGUID: mq6DPVQ2QqyR6RLFOJic5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832861" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 03/15] platform/x86/intel/pmt/telemetry: Move overlap check to post-decode hook Date: Fri, 12 Jun 2026 14:01:44 -0700 Message-ID: <2f5e429a38e22eb45fcfaaca4e037fa395d4f199.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the telemetry namespace to use the new PMT class pre/post decode interface. The overlap check, which previously occurred during header decode, is now performed in the post-decode hook once header fields are populated. This preserves existing behavior while reusing the same header decode logic across PMT drivers. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 24 ++++++++++++++-------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index ff39014b208c..8a0db0ef58c1 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -37,6 +37,7 @@ struct intel_pmt_header { u32 size; u32 guid; u8 access_type; + u8 telem_type; }; =20 struct intel_pmt_entry { diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/= x86/intel/pmt/telemetry.c index bdc7c24a3678..d22f633638be 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -58,14 +58,9 @@ struct pmt_telem_priv { struct intel_pmt_entry entry[]; }; =20 -static bool pmt_telem_region_overlaps(struct intel_pmt_entry *entry, - struct device *dev) +static bool pmt_telem_region_overlaps(struct device *dev, u32 guid, u32 ty= pe) { - u32 guid =3D readl(entry->disc_table + TELEM_GUID_OFFSET); - if (intel_pmt_is_early_client_hw(dev)) { - u32 type =3D TELEM_TYPE(readl(entry->disc_table)); - if ((type =3D=3D TELEM_TYPE_PUNIT_FIXED) || (guid =3D=3D TELEM_CLIENT_FIXED_BLOCK_GUID)) return true; @@ -80,15 +75,25 @@ static int pmt_telem_header_decode(struct intel_pmt_ent= ry *entry, void __iomem *disc_table =3D entry->disc_table; struct intel_pmt_header *header =3D &entry->header; =20 - if (pmt_telem_region_overlaps(entry, dev)) - return 1; - header->access_type =3D TELEM_ACCESS(readl(disc_table)); header->guid =3D readl(disc_table + TELEM_GUID_OFFSET); header->base_offset =3D readl(disc_table + TELEM_BASE_OFFSET); =20 /* Size is measured in DWORDS, but accessor returns bytes */ header->size =3D TELEM_SIZE(readl(disc_table)); + header->telem_type =3D TELEM_TYPE(readl(entry->disc_table)); + + return 0; +} + +static int pmt_telem_post_decode(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) +{ + struct intel_pmt_header *header =3D &entry->header; + struct device *dev =3D &ivdev->auxdev.dev; + + if (pmt_telem_region_overlaps(dev, header->guid, header->telem_type)) + return 1; =20 /* * Some devices may expose non-functioning entries that are @@ -131,6 +136,7 @@ static struct intel_pmt_namespace pmt_telem_ns =3D { .name =3D "telem", .xa =3D &telem_array, .pmt_header_decode =3D pmt_telem_header_decode, + .pmt_post_decode =3D pmt_telem_post_decode, .pmt_add_endpoint =3D pmt_telem_add_endpoint, }; =20 --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7ECA378D7B; Fri, 12 Jun 2026 21:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298137; cv=none; b=e0RLA1GH9KOkRh4ylhlOl/5hFMk7dasUQzh0iLV1dED3Dn1qv9XJG/Q470ptBJeUDpftL9Vf4QrcQPD/dG8VOQLmokw6+GJCVzeCQ9n2CfW92bAk87/GHr4qbqu2Yl0glG8oHEMRxIlOMR3qoirw80fNnyXd1SAWjDT5y3YVc00= ARC-Message-Signature: i=1; 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d="scan'208";a="250832862" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 04/15] platform/x86/intel/pmt: Pass discovery index instead of resource Date: Fri, 12 Jun 2026 14:01:45 -0700 Message-ID: <8e785902c6a3ac1b5a9c3f0f65096553dc5acd4f.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change PMT class code to pass a discovery index rather than a direct struct resource when creating entries. This allows the class to identify the discovery source generically without assuming PCI BAR resources. For PCI devices, the index still resolves to a resource in the intel_vsec_device. Other discovery sources, such as ACPI, can use the same index without needing a struct resource. Signed-off-by: David E. Box --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 changes: - Rebased after dropping the previous "Move header decode into common helper" patch - Adjusted the intel_pmt_populate_entry() call path to match the restored intel_pmt_dev_create() flow - Did not apply Ilpo V2 signoff due to these changes. V2 - No changes drivers/platform/x86/intel/pmt/class.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 9b315334a69b..7da8279b54f8 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -206,11 +206,12 @@ EXPORT_SYMBOL_GPL(intel_pmt_class); =20 static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, struct intel_vsec_device *ivdev, - struct resource *disc_res) + int idx) { struct pci_dev *pci_dev =3D to_pci_dev(ivdev->dev); struct device *dev =3D &ivdev->auxdev.dev; struct intel_pmt_header *header =3D &entry->header; + struct resource *disc_res; u8 bir; =20 /* @@ -235,6 +236,7 @@ static int intel_pmt_populate_entry(struct intel_pmt_en= try *entry, * For access_type LOCAL, the base address is as follows: * base address =3D end of discovery region + base offset */ + disc_res =3D &ivdev->resource[idx]; entry->base_addr =3D disc_res->end + 1 + header->base_offset; =20 /* @@ -397,7 +399,7 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry,= struct intel_pmt_namespa return ret; } =20 - ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); + ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, idx); if (ret) return ret; =20 --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AD9736B05C; Fri, 12 Jun 2026 21:02:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298135; cv=none; b=oYWkpwbfGFK5hoCwrPR7FzDb2sI9dQYBUS6MpiULj2BBPJ7H1ODM6h/FwLRa7gW7Qk2pRDz4cUPeYVS7/ZXp+XEHox+qjpgZfRWuStWRcowbHvkVSrEBc/9r7GKyQHJN82vnteCQnTbWx6bGT2oRSgJbY9aKGTWalxGU5uCM3YI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298135; c=relaxed/simple; bh=LjNy/YZPcDwJpyqNlLJ9U2Z8d+VkxHR3kucZxxmAp3E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QF5wJZ8eTdRQrrVRGHCwuMkmDgSIMQ/8wJ/RXHxZlJVC0dC765RF3o9atNE6uO9b/tk8PRcq1DPg/lLe9UV+vZX4bIx0LFrPufvmfnPUMsCnvpr0MyvVEeyi1aJ0gHiFf5e8Ba3GNOp6ueLTdk5+kYQgXCq1NgP48yrBt0BLhgE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A9TJJaFI; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A9TJJaFI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298135; x=1812834135; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LjNy/YZPcDwJpyqNlLJ9U2Z8d+VkxHR3kucZxxmAp3E=; b=A9TJJaFInvbuMgO1a6XgTHYOeA7WJ0sN3D1l6dTcJiSYVuHehUwsxuDE uMv8KWX7qvxHfo4qgBYy2TnWWED0teBj8yAA/YzZcQREbRn0ynbmkfLrG j8UJjK/qp4qOPz8LXUPhm8tID4pRwX30dEN+h9+jdgbP11H/Er0LqPCLK +l96c6Iqq+d1dB5o7ffP4iGLmY0b3QVunEHN6KGc58249BtKlfAPDKs3w Yixh3rW9iEq5p+fLhuRdGU+/bhRitMNb7GVC/aUqAqN+EN6o5SJLeaS6Q zfG3UUEyVfFQTXwm+7fQZ8yz/MocW5Jlob4Kd3Z4uzT72jYEiDrq1hsLH A==; X-CSE-ConnectionGUID: zpIoKGPfQC2Iw1sQrowxFQ== X-CSE-MsgGUID: hlwUrKc6SvGJc1vO9YIpEQ== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037983" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037983" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 X-CSE-ConnectionGUID: QYRXcyotSNSLPH0ke3nr2A== X-CSE-MsgGUID: 5SfyGVuKQxOEPBWaQWy2aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832863" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 05/15] platform/x86/intel/pmt: Cache the telemetry discovery header Date: Fri, 12 Jun 2026 14:01:46 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pmt_telem_header_decode() only needs the discovery header dwords, but it currently decodes them by reading directly from entry->disc_table. Cache the discovery header in intel_pmt_entry when the device is created and have telemetry decode use the cached values instead of performing MMIO reads at decode time. The DVSEC discovery resource for a namespace is sized by its per-entry entry_size (in dwords), which can be less than the 4-dword cache (e.g. telemetry uses entry_size =3D 3, i.e. 12 bytes). Cap the memcpy_fromio() to resource_size(disc_res) so the new cache does not read past the mapped region. Any unread dwords stay zero from the zero-initialized allocation of the containing struct. This keeps the telemetry header decode path independent of how the discovery data is backed and avoids baking a direct MMIO assumption into the feature-specific decode logic. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V8 - No changes V7 changes: - Replaced min_t(size_t, ...) with min() because both operands are size_t (Ilpo). V6 changes: - Added #include for min_t() macro used in memcpy_fromio() size calculation (Ilpo). V5 changes: - Cap memcpy_fromio() of the cached discovery header to resource_size(disc_res) so the newly introduced cache does not over-read namespaces whose DVSEC entry_size is smaller than the cache (e.g. telemetry has entry_size =3D 3, 12 bytes). V4 - No changes V3 changes: - New patch split out from PMT header-fetch rework to cache discovery header data before downstream decode/population. - Added to carry the post-v3 bug fix while preserving the original series ordering intent. drivers/platform/x86/intel/pmt/class.c | 11 +++++++++++ drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 12 ++++++------ 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 7da8279b54f8..8d27f59d5bff 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -383,6 +384,16 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry= , struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); =20 + /* + * The mapped discovery resource may be smaller than disc_header (its + * size is the namespace's DVSEC entry_size in dwords, which can be + * less than 4). Cap the copy to the actual resource size to avoid + * reading past the mapped region; any unread dwords stay zero from + * the zero-initialized allocation of the containing struct. + */ + memcpy_fromio(entry->disc_header, entry->disc_table, + min(sizeof(entry->disc_header), resource_size(disc_res))); + if (ns->pmt_pre_decode) { ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); if (ret) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 8a0db0ef58c1..84202fc7920c 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -44,6 +44,7 @@ struct intel_pmt_entry { struct telem_endpoint *ep; struct pci_dev *pcidev; struct intel_pmt_header header; + u32 disc_header[4]; struct bin_attribute pmt_bin_attr; const struct attribute_group *attr_grp; struct kobject *kobj; diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/= x86/intel/pmt/telemetry.c index d22f633638be..953f35b6daec 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -72,16 +72,16 @@ static bool pmt_telem_region_overlaps(struct device *de= v, u32 guid, u32 type) static int pmt_telem_header_decode(struct intel_pmt_entry *entry, struct device *dev) { - void __iomem *disc_table =3D entry->disc_table; struct intel_pmt_header *header =3D &entry->header; + u32 *disc_header =3D entry->disc_header; =20 - header->access_type =3D TELEM_ACCESS(readl(disc_table)); - header->guid =3D readl(disc_table + TELEM_GUID_OFFSET); - header->base_offset =3D readl(disc_table + TELEM_BASE_OFFSET); + header->access_type =3D TELEM_ACCESS(disc_header[0]); + header->guid =3D disc_header[1]; + header->base_offset =3D disc_header[2]; =20 /* Size is measured in DWORDS, but accessor returns bytes */ - header->size =3D TELEM_SIZE(readl(disc_table)); - header->telem_type =3D TELEM_TYPE(readl(entry->disc_table)); + header->size =3D TELEM_SIZE(disc_header[0]); + header->telem_type =3D TELEM_TYPE(disc_header[0]); =20 return 0; } --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C78D379EE7; Fri, 12 Jun 2026 21:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="86037986" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037986" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 X-CSE-ConnectionGUID: eIk0xP8xTDi43W1a8efm+Q== X-CSE-MsgGUID: lS7pQ9qnSZ2IZTb98Jzs5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832864" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 06/15] platform/x86/intel/pmt: Unify header fetch and add ACPI source Date: Fri, 12 Jun 2026 14:01:47 -0700 Message-ID: <4b33b04ffaf0943b67d330f48b5d1dfcb6d1be5d.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the PMT class to read discovery headers from either PCI MMIO or ACPI-provided entries, depending on the discovery source. The new source-aware fetch helper caches the canonical discovery header for both paths, capping PCI MMIO reads to the mapped resource size, while keeping the mapped PCI discovery table available for users such as crashlog. Split intel_pmt_populate_entry() into source-specific resolvers: - pmt_resolve_access_pci(): handles both ACCESS_LOCAL and ACCESS_BARID for PCI-backed devices and sets entry->pcidev. Same existing functionality. - pmt_resolve_access_acpi(): handles only ACCESS_BARID for ACPI-backed devices, rejecting ACCESS_LOCAL which has no valid semantics without a physical discovery resource. This maintains existing PCI behavior and makes no functional changes for PCI devices. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V8 - No changes V7 changes: - Updated header copy size handling to use min() for size_t operands and aligned local style per review feedback (Ilpo). V6 changes: - Removed unneeded headers parameter from pmt_get_headers() (Ilpo). - Added memset() to zero-initialize disc_header before copying to avoid uninitialized data in entry reuse scenarios (Ilpo/Sashiko). V5 changes: - Bounded memcpy_fromio() to resource_size() of the mapped DVSEC entry to avoid over-reading namespaces with smaller entry_size. - Documented that entry->disc_table =3D NULL in the ACPI branch is intentional and that consumers must only be wired to INTEL_VSEC_DISC_PCI namespaces if they dereference disc_table. V4 - Replaced local raw ACPI discovery pointer type u32 (*)[4] with acpi_disc_t for consistency with exported PMC helper types. V3 - No changes V2 changes: - Replaced intermediate header-decode helper with inline ACPI path - Removed separate disc_acpi resource - Moved ACPI fetch directly into intel_pmt_dev_create drivers/platform/x86/intel/pmt/class.c | 151 +++++++++++++++++++++---- drivers/platform/x86/intel/pmt/class.h | 2 +- include/linux/intel_vsec.h | 5 +- 3 files changed, 136 insertions(+), 22 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 8d27f59d5bff..d0ab8e33c62a 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -205,9 +205,9 @@ struct class intel_pmt_class =3D { }; EXPORT_SYMBOL_GPL(intel_pmt_class); =20 -static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, - struct intel_vsec_device *ivdev, - int idx) +static int pmt_resolve_access_pci(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev, + int idx) { struct pci_dev *pci_dev =3D to_pci_dev(ivdev->dev); struct device *dev =3D &ivdev->auxdev.dev; @@ -287,6 +287,81 @@ static int intel_pmt_populate_entry(struct intel_pmt_e= ntry *entry, } =20 entry->pcidev =3D pci_dev; + + return 0; +} + +static int pmt_resolve_access_acpi(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev) +{ + struct pci_dev *pci_dev =3D NULL; + struct device *dev =3D &ivdev->auxdev.dev; + struct intel_pmt_header *header =3D &entry->header; + u8 bir; + + if (dev_is_pci(ivdev->dev)) + pci_dev =3D to_pci_dev(ivdev->dev); + + /* + * The base offset should always be 8 byte aligned. + * + * For non-local access types the lower 3 bits of base offset + * contains the index of the base address register where the + * telemetry can be found. + */ + bir =3D GET_BIR(header->base_offset); + + switch (header->access_type) { + case ACCESS_BARID: + /* ACPI platform drivers use base_addr */ + if (ivdev->base_addr) { + entry->base_addr =3D ivdev->base_addr + + GET_ADDRESS(header->base_offset); + break; + } + + /* If base_addr is not provided, then this is an ACPI companion device */ + if (!pci_dev) { + dev_err(dev, "ACCESS_BARID requires PCI BAR resources or base_addr\n"); + return -EINVAL; + } + + entry->base_addr =3D pci_resource_start(pci_dev, bir) + + GET_ADDRESS(header->base_offset); + break; + default: + dev_err(dev, "Unsupported access type %d for ACPI based PMT\n", + header->access_type); + return -EINVAL; + } + + return 0; +} + +static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev, + int idx) +{ + struct intel_pmt_header *header =3D &entry->header; + struct device *dev =3D &ivdev->auxdev.dev; + int ret; + + switch (ivdev->src) { + case INTEL_VSEC_DISC_PCI: + ret =3D pmt_resolve_access_pci(entry, ivdev, idx); + if (ret) + return ret; + break; + case INTEL_VSEC_DISC_ACPI: + ret =3D pmt_resolve_access_acpi(entry, ivdev); + if (ret) + return ret; + break; + default: + dev_err(dev, "Unknown discovery source: %d\n", ivdev->src); + return -EINVAL; + } + entry->guid =3D header->guid; entry->size =3D header->size; entry->cb =3D ivdev->priv_data; @@ -371,28 +446,66 @@ static int intel_pmt_dev_register(struct intel_pmt_en= try *entry, return ret; } =20 +static int pmt_get_headers(struct intel_vsec_device *ivdev, int idx, + struct intel_pmt_entry *entry) +{ + struct device *dev =3D &ivdev->auxdev.dev; + size_t header_bytes =3D sizeof(entry->disc_header); + + switch (ivdev->src) { + case INTEL_VSEC_DISC_PCI: { + struct resource *disc_res =3D &ivdev->resource[idx]; + void __iomem *disc_table; + + disc_table =3D devm_ioremap_resource(dev, disc_res); + if (IS_ERR(disc_table)) + return PTR_ERR(disc_table); + + /* + * The mapped resource is sized by the namespace's DVSEC + * entry_size (in dwords), which can be less than the default + * size (e.g. telemetry uses entry_size =3D 3, 12 bytes). Cap the + * copy to resource_size() to avoid reading past the mapped + * region. + */ + memset(entry->disc_header, 0, header_bytes); + memcpy_fromio(entry->disc_header, disc_table, + min(header_bytes, resource_size(disc_res))); + + /* Used by crashlog driver */ + entry->disc_table =3D disc_table; + + return 0; + } + case INTEL_VSEC_DISC_ACPI: { + memcpy(entry->disc_header, &ivdev->acpi_disc[idx][0], header_bytes); + /* + * No MMIO mapping exists on the ACPI source path; the cached + * headers are the only view of the discovery record. Consumers + * that dereference disc_table (e.g. crashlog) must therefore + * only be wired to namespaces backed by INTEL_VSEC_DISC_PCI. + */ + entry->disc_table =3D NULL; + + return 0; + } + default: + dev_err(dev, "Unknown discovery source type: %d\n", ivdev->src); + break; + } + + return -EINVAL; +} + int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_n= amespace *ns, struct intel_vsec_device *intel_vsec_dev, int idx) { struct device *dev =3D &intel_vsec_dev->auxdev.dev; - struct resource *disc_res; int ret; =20 - disc_res =3D &intel_vsec_dev->resource[idx]; - - entry->disc_table =3D devm_ioremap_resource(dev, disc_res); - if (IS_ERR(entry->disc_table)) - return PTR_ERR(entry->disc_table); - - /* - * The mapped discovery resource may be smaller than disc_header (its - * size is the namespace's DVSEC entry_size in dwords, which can be - * less than 4). Cap the copy to the actual resource size to avoid - * reading past the mapped region; any unread dwords stay zero from - * the zero-initialized allocation of the containing struct. - */ - memcpy_fromio(entry->disc_header, entry->disc_table, - min(sizeof(entry->disc_header), resource_size(disc_res))); + ret =3D pmt_get_headers(intel_vsec_dev, idx, entry); + if (ret) + return ret; =20 if (ns->pmt_pre_decode) { ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 84202fc7920c..a0ece4fc3837 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -44,7 +44,7 @@ struct intel_pmt_entry { struct telem_endpoint *ep; struct pci_dev *pcidev; struct intel_pmt_header header; - u32 disc_header[4]; + u32 disc_header[PMT_DISC_DWORDS]; struct bin_attribute pmt_bin_attr; const struct attribute_group *attr_grp; struct kobject *kobj; diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 07ea563f524e..843cda8f8644 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -28,6 +28,7 @@ #define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) #define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) #define TABLE_OFFSET_SHIFT 3 +#define PMT_DISC_DWORDS 4 =20 struct device; struct pci_dev; @@ -122,7 +123,7 @@ struct intel_vsec_platform_info { struct device *parent; struct intel_vsec_header **headers; const struct vsec_feature_dependency *deps; - u32 (*acpi_disc)[4]; + u32 (*acpi_disc)[PMT_DISC_DWORDS]; enum intel_vsec_disc_source src; void *priv_data; unsigned long caps; @@ -153,7 +154,7 @@ struct intel_vsec_platform_info { struct intel_vsec_device { struct auxiliary_device auxdev; struct device *dev; - u32 (*acpi_disc)[4]; + u32 (*acpi_disc)[PMT_DISC_DWORDS]; enum intel_vsec_disc_source src; struct ida *ida; int num_resources; --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 044F537CD41; Fri, 12 Jun 2026 21:02:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298138; cv=none; b=mN1RKq8synNXev7c547LfrluruBjtZx28y+YW+mGG8Gxnef2QFZmP1fUU5pRW6ynoq9ilYmO7j51MO8WxD1ugwTduykL3h8q0CCtQd8Eanorh5qz6aDGAlIi/T84fmqRVopqiBvekR2xXK4TT5O1vvk1hL9R6Prt8Yu61+fXZr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298138; c=relaxed/simple; bh=gCGq2m2rNffR04xAjs4JT6Z+nzMKn81SMaR9yM/ABMw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JxZeUphwqeWVzOSEjrjAoDvHzJkqIGQvNNhG2+eBnIr95HbpehGNahtqKEz3sZ0OLUpOYYqlCZ1ZNGDXCJ1W2BbiXB10lHVXbDLL0JN7ECuybP/Sfu3zeYRwgbkFsm4Zl4lUdFad9EUuQ8Q3CuluZSEmW51c1c1tn+6Ly6FD7ZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HP3X0kCz; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HP3X0kCz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298138; x=1812834138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gCGq2m2rNffR04xAjs4JT6Z+nzMKn81SMaR9yM/ABMw=; b=HP3X0kCzlNAB4w329oIKhg+5HP2xn7r5SqJwbFJTR+XeknbSrjos+KoE K76RKig/nVYaomAa9YgNlco/zfbRV6oaAEHVpejewUMwucpMqS0gjXI5v Aaf23gQBghReDyQ6EFquy2QUBm3cEgN9rs+/UGRjV9g4q5ps2moKyggrO tBhUkeX/xajudm/W8slNq5Xxf4xuX74YeS7tEVayEUu2qBi/JirqkT+zv f4yL7SgQouqezJVtyWsCmRxhfuSvciCn1u29yoo9vVO8qEB68yglAWDpc Gm1Cf60L9M/FU1vrIX/C4HaukqY9zRRu7Mylg0y7Vp07aq6JoiYRUM+gO Q==; X-CSE-ConnectionGUID: x4QEklBzTFOOukZ+e1It+w== X-CSE-MsgGUID: QE7hVB8ISFaHfDwe3Dp8jg== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037989" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037989" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: +HHSI1F8TpSWoQUnyR1Mwg== X-CSE-MsgGUID: +AKaD6HeRHKR3pmuVUMCrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832865" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 07/15] platform/x86/intel/pmc: Add PMC SSRAM Kconfig description Date: Fri, 12 Jun 2026 14:01:48 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a proper description for the intel_pmc_ssram driver. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/= intel/pmc/Kconfig index c6ef0bcf76af..e9012b703918 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -28,3 +28,14 @@ config INTEL_PMC_CORE =20 config INTEL_PMC_SSRAM_TELEMETRY tristate + help + This driver discovers PMC SSRAM telemetry regions through the PMC's + MMIO interface (PCI) or ACPI _DSD properties and registers them with + the Intel VSEC framework as Intel PMT telemetry devices. + + It probes the PMC SSRAM device, extracts DVSEC information from MMIO, + reads device IDs and base addresses for multiple PMCs (main, IOE, PCH), + and exposes the discovered telemetry through Intel PMT interfaces + (including sysfs). + + This option is selected by INTEL_PMC_CORE. --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F6E38D3F6; Fri, 12 Jun 2026 21:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298141; cv=none; b=WPNE0E9QSSMVKVwEtWy2rozCSl54IEmE64o35NFUbFVgvYfr4FyC3+ncUSBbMb2j3QGuyIHIK8/3q1zDrOt5lBG9XUdIJFc1yCHdPPWgw7aau1/VnTElmbUfZxJ7rw6BQ+6zmqUW8Dif3XAI1Ac14msZzQI6TbXy7QjWjyugdJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298141; c=relaxed/simple; bh=hTe0XYv99TBUeklhSp/dGFdY7Rya6TYtxQqJN2i8GX8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fSPqeU2rvHsb7vKDBq0uMemIfRDa4PotD7M8pU7mIQS/bzQN6M7wtAjRGl/1WcG3IKx9TJE8vjwmXhCifGIisEjmL9ZJwhulpeccnMXE0QL8oXs8gF8fCWfw1XXZmJecjOGuNQattLTtFaGw+3i49xrMakwjrkT+c6HqCLTar34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y0detIr0; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y0detIr0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298139; x=1812834139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hTe0XYv99TBUeklhSp/dGFdY7Rya6TYtxQqJN2i8GX8=; b=Y0detIr0o7EaG9ePLsc5VgeuXLxaNYaEXa8EL9wYUGWlt/Uy8NYp++Zr mHZLgPJj0j6o8r0v+VaSAIYVI5Y2neK9FN+ktqV9e59FmgPAthB5ttFxC UQo/4qsBSjqXxE28iQGqIWCgqZJ/uSubm15xnuiwM9hBv0UCQYUdAgIvM uCHnP9A8NShuCwZELiMKY9DTiYMB6GGLVVyXWifvIeESYbdMmXJvIGpbl X+NqTAKD7le0ldG6ZdZ5hcOCyPtHOdFuZKl2BetoQ7GOhCqZG3RcoUed7 wkzDLanLYDZxf125H/TBGem9g0kC21J3QS0Pf0MGxewwirzop7h01031D Q==; X-CSE-ConnectionGUID: fsVAgMZhT6adW0YhM4u36g== X-CSE-MsgGUID: 6VuxxOpGQc2Lkrcs1Cbvsg== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037992" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037992" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: ywJViDz4TU20u6pn/9gSOg== X-CSE-MsgGUID: qE+02IzkRwi5+SIGygrslA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832866" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:11 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 08/15] platform/x86/intel/pmc: Add ACPI PWRM telemetry driver for Nova Lake S Date: Fri, 12 Jun 2026 14:01:49 -0700 Message-ID: <09b8211d8a5a79fa019ee2397137a6a43cf19430.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an ACPI-based PMC PWRM telemetry driver for Nova Lake S. The driver locates PMT discovery data in _DSD under the Intel VSEC UUID, parses it, and registers telemetry regions with the PMT/VSEC framework so PMC telemetry is exposed via existing PMT interfaces. Export pmc_parse_telem_dsd() and pmc_find_telem_guid() to support ACPI discovery in other PMC drivers (e.g., ssram_telemetry) without duplicating ACPI parsing logic. Also export acpi_disc_t typedef from core.h for callers to properly declare discovery table arrays. Selected by INTEL_PMC_CORE. Existing PCI functionality is preserved. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V8 - No changes V7 changes: - Fixed ACPI discovery offset parsing to preserve the masked (unshifted) DISC_TBL encoding instead of using FIELD_GET() right-shift semantics (Ilpo). V6 - No changes V5 changes: - Added #include for U16_MAX (Ilpo). - Split acpi_handle declaration from ACPI_HANDLE() assignment and placed the assignment immediately before the !handle check (Ilpo). - Reordered local variables in pmc_pwrm_acpi_probe() in reverse-xmas-tree order (Ilpo). V4 changes: - These changes were supposed to be in V3 - Updated pmc_parse_telem_dsd() in pwrm_telemetry.c to use acpi_disc_t in the function return type for consistency with the exported typedef - In pmc_parse_telem_dsd(), change acpi_disc declaration to happen at the allocation site as specified by cleanup.h - Style, readability and cleanup-path refinement based on review feedback V2 changes: - Added explicit include for guid_t type availability in core.h - Added explicit include in pwrm_telemetry.c for GENMASK() - Added and converted goto based cleanup to __free() attributes per Ilpo's feedback - Combined u64 hdr0 and u64 hdr1 into single declaration - Converted pmc_parse_telem_dsd() to return acpi_disc directly with ERR_PTR() for failures - Added braces around _DSD evaluation failure path drivers/platform/x86/intel/pmc/Kconfig | 14 ++ drivers/platform/x86/intel/pmc/Makefile | 2 + drivers/platform/x86/intel/pmc/core.h | 16 ++ .../platform/x86/intel/pmc/pwrm_telemetry.c | 216 ++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 drivers/platform/x86/intel/pmc/pwrm_telemetry.c diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/= intel/pmc/Kconfig index e9012b703918..561d46634ab2 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -9,6 +9,7 @@ config INTEL_PMC_CORE depends on ACPI depends on INTEL_PMT_TELEMETRY select INTEL_PMC_SSRAM_TELEMETRY + select INTEL_PMC_PWRM_TELEMETRY help The Intel Platform Controller Hub for Intel Core SoCs provides access to Power Management Controller registers via various interfaces. This @@ -39,3 +40,16 @@ config INTEL_PMC_SSRAM_TELEMETRY (including sysfs). =20 This option is selected by INTEL_PMC_CORE. + +config INTEL_PMC_PWRM_TELEMETRY + tristate + help + This driver discovers PMC PWRM telemetry regions described in ACPI + _DSD and registers them with the Intel VSEC framework as Intel PMT + telemetry devices. + + It validates the ACPI discovery data and publishes the discovered + regions so they can be accessed through the Intel PMT telemetry + interfaces (including sysfs). + + This option is selected by INTEL_PMC_CORE. diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86= /intel/pmc/Makefile index 23853e867c91..5b595176f812 100644 --- a/drivers/platform/x86/intel/pmc/Makefile +++ b/drivers/platform/x86/intel/pmc/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_INTEL_PMC_CORE) +=3D intel_pmc_core_pltdrv.o # Intel PMC SSRAM driver intel_pmc_ssram_telemetry-y +=3D ssram_telemetry.o obj-$(CONFIG_INTEL_PMC_SSRAM_TELEMETRY) +=3D intel_pmc_ssram_telemetry.o +intel_pmc_pwrm_telemetry-y +=3D pwrm_telemetry.o +obj-$(CONFIG_INTEL_PMC_PWRM_TELEMETRY) +=3D intel_pmc_pwrm_telemetry.o diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 55cf567febe4..b4c7399f8369 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -14,10 +14,15 @@ =20 #include #include +#include +#include #include +#include =20 struct telem_endpoint; =20 +DEFINE_FREE(pmc_acpi_free, void *, if (_T) ACPI_FREE(_T)) + #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) =20 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 @@ -622,6 +627,8 @@ int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcdev= , struct pmc *pmc, extern const struct file_operations pmc_core_substate_req_regs_fops; extern const struct file_operations pmc_core_substate_blk_req_fops; =20 +extern const guid_t intel_vsec_guid; + #define pmc_for_each_mode(mode, pmc) \ for (unsigned int __i =3D 0, __cond; \ __cond =3D __i < (pmc)->num_lpm_modes, \ @@ -643,4 +650,13 @@ static const struct file_operations __name ## _fops = =3D { \ .release =3D single_release, \ } =20 +struct intel_vsec_header; +union acpi_object; + +/* Avoid checkpatch warning */ +typedef u32 (*acpi_disc_t)[PMT_DISC_DWORDS]; + +acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj, + struct intel_vsec_header *header); +union acpi_object *pmc_find_telem_guid(union acpi_object *dsd); #endif /* PMC_CORE_H */ diff --git a/drivers/platform/x86/intel/pmc/pwrm_telemetry.c b/drivers/plat= form/x86/intel/pmc/pwrm_telemetry.c new file mode 100644 index 000000000000..62b0e9fc7920 --- /dev/null +++ b/drivers/platform/x86/intel/pmc/pwrm_telemetry.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PMC PWRM ACPI driver + * + * Copyright (C) 2025, Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" + +#define ENTRY_LEN 5 + +/* DWORD2 */ +#define DVSEC_ID_MASK GENMASK(15, 0) +#define NUM_ENTRIES_MASK GENMASK(23, 16) +#define ENTRY_SIZE_MASK GENMASK(31, 24) + +/* DWORD3 */ +#define TBIR_MASK GENMASK(2, 0) +#define DISC_TBL_OFF_MASK GENMASK(31, 3) + +const guid_t intel_vsec_guid =3D + GUID_INIT(0x294903fb, 0x634d, 0x4fc7, 0xaf, 0x1f, 0x0f, 0xb9, + 0x56, 0xb0, 0x4f, 0xc1); + +static bool is_valid_entry(union acpi_object *pkg) +{ + int i; + + if (!pkg || pkg->type !=3D ACPI_TYPE_PACKAGE || pkg->package.count !=3D E= NTRY_LEN) + return false; + + if (pkg->package.elements[0].type !=3D ACPI_TYPE_STRING) + return false; + + for (i =3D 1; i < ENTRY_LEN; i++) + if (pkg->package.elements[i].type !=3D ACPI_TYPE_INTEGER) + return false; + + return true; +} + +acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj, + struct intel_vsec_header *header) +{ + union acpi_object *vsec_pkg; + union acpi_object *disc_pkg; + u64 hdr0, hdr1; + int num_regions; + int i; + + if (!header) + return ERR_PTR(-EINVAL); + + if (!obj || obj->type !=3D ACPI_TYPE_PACKAGE || obj->package.count !=3D 2) + return ERR_PTR(-EINVAL); + + /* First Package is DVSEC info */ + vsec_pkg =3D &obj->package.elements[0]; + if (!is_valid_entry(vsec_pkg)) + return ERR_PTR(-EINVAL); + + hdr0 =3D vsec_pkg->package.elements[3].integer.value; + hdr1 =3D vsec_pkg->package.elements[4].integer.value; + + header->id =3D FIELD_GET(DVSEC_ID_MASK, hdr0); + header->num_entries =3D FIELD_GET(NUM_ENTRIES_MASK, hdr0); + header->entry_size =3D FIELD_GET(ENTRY_SIZE_MASK, hdr0); + header->tbir =3D FIELD_GET(TBIR_MASK, hdr1); + header->offset =3D hdr1 & DISC_TBL_OFF_MASK; + + /* Second Package contains the discovery tables */ + disc_pkg =3D &obj->package.elements[1]; + if (disc_pkg->type !=3D ACPI_TYPE_PACKAGE || disc_pkg->package.count < 1) + return ERR_PTR(-EINVAL); + + num_regions =3D disc_pkg->package.count; + if (header->num_entries !=3D num_regions) + return ERR_PTR(-EINVAL); + + acpi_disc_t disc __free(kfree) =3D kmalloc_array(num_regions, sizeof(*dis= c), + GFP_KERNEL); + if (!disc) + return ERR_PTR(-ENOMEM); + + for (i =3D 0; i < num_regions; i++) { + union acpi_object *pkg; + u64 value; + int j; + + pkg =3D &disc_pkg->package.elements[i]; + if (!is_valid_entry(pkg)) + return ERR_PTR(-EINVAL); + + /* Element 0 is a descriptive string; DWORD values start at index 1. */ + for (j =3D 1; j < ENTRY_LEN; j++) { + value =3D pkg->package.elements[j].integer.value; + if (value > U32_MAX) + return ERR_PTR(-ERANGE); + + disc[i][j - 1] =3D value; + } + } + + return no_free_ptr(disc); +} +EXPORT_SYMBOL_NS_GPL(pmc_parse_telem_dsd, "INTEL_PMC_CORE"); + +union acpi_object *pmc_find_telem_guid(union acpi_object *dsd) +{ + int i; + + if (!dsd || dsd->type !=3D ACPI_TYPE_PACKAGE) + return NULL; + + for (i =3D 0; i + 1 < dsd->package.count; i +=3D 2) { + union acpi_object *uuid_obj, *data_obj; + guid_t uuid; + + uuid_obj =3D &dsd->package.elements[i]; + data_obj =3D &dsd->package.elements[i + 1]; + + if (uuid_obj->type !=3D ACPI_TYPE_BUFFER || + uuid_obj->buffer.length !=3D 16) + continue; + + memcpy(&uuid, uuid_obj->buffer.pointer, 16); + if (guid_equal(&uuid, &intel_vsec_guid)) + return data_obj; + } + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(pmc_find_telem_guid, "INTEL_PMC_CORE"); + +static int pmc_pwrm_acpi_probe(struct platform_device *pdev) +{ + struct intel_vsec_header header; + struct intel_vsec_header *headers[2] =3D { &header, NULL }; + struct acpi_buffer buf =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct intel_vsec_platform_info info =3D { }; + struct device *dev =3D &pdev->dev; + union acpi_object *dsd; + struct resource *res; + acpi_handle handle; + acpi_status status; + + handle =3D ACPI_HANDLE(&pdev->dev); + if (!handle) + return -ENODEV; + + status =3D acpi_evaluate_object(handle, "_DSD", NULL, &buf); + if (ACPI_FAILURE(status)) { + return dev_err_probe(dev, -ENODEV, "Could not evaluate _DSD: %s\n", + acpi_format_exception(status)); + } + + void *dsd_buf __free(pmc_acpi_free) =3D buf.pointer; + + dsd =3D pmc_find_telem_guid(dsd_buf); + if (!dsd) + return -ENODEV; + + acpi_disc_t acpi_disc __free(kfree) =3D pmc_parse_telem_dsd(dsd, &header); + if (IS_ERR(acpi_disc)) + return PTR_ERR(acpi_disc); + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, header.tbir); + if (!res) + return -EINVAL; + + info.headers =3D headers; + info.caps =3D VSEC_CAP_TELEMETRY; + info.acpi_disc =3D acpi_disc; + info.src =3D INTEL_VSEC_DISC_ACPI; + info.base_addr =3D res->start; + + return intel_vsec_register(&pdev->dev, &info); +} + +static const struct acpi_device_id pmc_pwrm_acpi_ids[] =3D { + { "INTC1122", 0 }, /* Nova Lake */ + { "INTC1129", 0 }, /* Nova Lake */ + { } +}; +MODULE_DEVICE_TABLE(acpi, pmc_pwrm_acpi_ids); + +static struct platform_driver pmc_pwrm_acpi_driver =3D { + .probe =3D pmc_pwrm_acpi_probe, + .driver =3D { + .name =3D "intel_pmc_pwrm_acpi", + .acpi_match_table =3D ACPI_PTR(pmc_pwrm_acpi_ids), + }, +}; +module_platform_driver(pmc_pwrm_acpi_driver); + +MODULE_AUTHOR("David E. Box "); +MODULE_DESCRIPTION("Intel PMC PWRM ACPI driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("INTEL_VSEC"); --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A82537EFEE; Fri, 12 Jun 2026 21:02:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298138; cv=none; b=rOyGnLBNq55DveSc/rSGeU3R7fJp2l073evk/+dqOSkt+U+zPnJi0+t/JGa9pK4lIrfO4hUyKwg5smOOM+h9Kot+hbFrCc0GZQnARyV7XDkkGHTrZ7CD8WoknuUzBI4G+f6QszECroVRPiVC7wVFxLKOLOIKV7bXrYSFJJoRq+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298138; c=relaxed/simple; bh=23FNr6jVvfK0ryQv1CWR6rz78krBF9LFVZXU0yprp/k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=miK9wRK5R/EyPqa7hQNyuZVh4cHQWShLTUxRxiBkrKZFEF9Q5Q6CXpDtY4hSOjYuiLyq8oop97JReh1bOUkBOAVVSjWtUhqy3NLIOoBSTtr7kQpkOL0XojwW2DTGdPyuEQ8s/ppTOO6VYEE6H3MoN9aPiNHyPpdCuucFS4rAq6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E8t154i+; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E8t154i+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298138; x=1812834138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=23FNr6jVvfK0ryQv1CWR6rz78krBF9LFVZXU0yprp/k=; b=E8t154i+g3XwFww4KdXE32hEfgCq8IgYmiZYpEWjKoHKO79QJaE4Ou22 IY6ORjBHM9AzNJBqoBBdINHtS13i4drLdct3dI3o53RprfV0wFUWHmzlx TZGkMJ+tOY2Q7ndgtxnxYEX+cwDqYfIOZwUJgXUh5EzV53LK08v5VQcm3 h430wFZY27/22ql4QZU5zAfwgL9NShV1Xk91TSQ0BcoXRvsxPBStCawCQ iRG6bNT44q4qlNVsgtBfTaK4RZJu6o+kB93xkYtXDwtG9ZGCWLeqC5u8n zZWmfNhoLziiGAoUVFHpFpxtVl8/PZOU99kBwzBqgjePVeFHKIyk9+BsT w==; X-CSE-ConnectionGUID: ZDdFPgMvR3S+vKfCKzwx1Q== X-CSE-MsgGUID: qdaS7CzWS7eD+50EjEzcQQ== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86037996" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037996" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: Zjt3rAKlT4yjCT98qc9RHA== X-CSE-MsgGUID: pAD+X2M8RMuva5Odu07ciA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832867" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 09/15] platform/x86/intel/pmc/ssram: Rename probe and PCI ID table for consistency Date: Fri, 12 Jun 2026 14:01:50 -0700 Message-ID: <6d3935858214fdd0f530f9a7c08a387fa4e5e8cd.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename intel_pmc_ssram_telemetry_probe() to pmc_ssram_telemetry_probe() and intel_pmc_ssram_telemetry_pci_ids[] to pmc_ssram_telemetry_pci_ids[], updating the MODULE_DEVICE_TABLE() and pci_driver wiring accordingly. This aligns the symbol names with the driver filename and module name, reduces redundant intel_ prefixes, and improves readability. No functional behavior changes are intended. Reviewed-by: Ilpo J=C3=A4rvinen Signed-off-by: David E. Box --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/ssram_telemetry.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 6f6e83e70fc5..1deb4d71da3f 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -149,7 +149,7 @@ int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_i= dx, } EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 -static int intel_pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const s= truct pci_device_id *id) +static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { int ret; =20 @@ -183,7 +183,7 @@ static int intel_pmc_ssram_telemetry_probe(struct pci_d= ev *pcidev, const struct return ret; } =20 -static const struct pci_device_id intel_pmc_ssram_telemetry_pci_ids[] =3D { +static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, @@ -193,14 +193,14 @@ static const struct pci_device_id intel_pmc_ssram_tel= emetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN) }, { } }; -MODULE_DEVICE_TABLE(pci, intel_pmc_ssram_telemetry_pci_ids); +MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids); =20 -static struct pci_driver intel_pmc_ssram_telemetry_driver =3D { +static struct pci_driver pmc_ssram_telemetry_driver =3D { .name =3D "intel_pmc_ssram_telemetry", - .id_table =3D intel_pmc_ssram_telemetry_pci_ids, - .probe =3D intel_pmc_ssram_telemetry_probe, + .id_table =3D pmc_ssram_telemetry_pci_ids, + .probe =3D pmc_ssram_telemetry_probe, }; -module_pci_driver(intel_pmc_ssram_telemetry_driver); +module_pci_driver(pmc_ssram_telemetry_driver); =20 MODULE_IMPORT_NS("INTEL_VSEC"); MODULE_AUTHOR("Xi Pardee "); --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 886AA39C64E; Fri, 12 Jun 2026 21:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="86037999" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86037999" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: oTfVhjbHQMSOHs5/R6JLkQ== X-CSE-MsgGUID: dY7CMcO8TzWysG5d2owBww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832868" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 10/15] platform/x86/intel/pmc/ssram: Add PCI platform data Date: Fri, 12 Jun 2026 14:01:51 -0700 Message-ID: <1c6180097b20dbe1337828bf6d3667854d63583a.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add per-device platform data for SSRAM telemetry PCI IDs and route probe through a method selector driven by id->driver_data. This is a preparatory refactor for follow-on discovery methods while preserving current behavior: all supported IDs continue to use the PCI initialization path. Signed-off-by: David E. Box --- V8 - No changes V7 changes: - Changed pmc_ssram_telemetry_pci_init() to return 0 in the tail success path after secondary PMC probing (Ilpo). V6 changes: - Reordered from v5 patch 12 to maintain logical flow before probe state refactoring. V5 - No changes V4 - No changes V3 - No changes V2 changes: - Added missing include for dev_dbg() usage in probe .../platform/x86/intel/pmc/ssram_telemetry.c | 71 +++++++++++++++---- 1 file changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 1deb4d71da3f..05f213aa108f 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -24,6 +25,18 @@ =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 +enum resource_method { + RES_METHOD_PCI, +}; + +struct ssram_type { + enum resource_method method; +}; + +static const struct ssram_type pci_main =3D { + .method =3D RES_METHOD_PCI, +}; + static struct pmc_ssram_telemetry *pmc_ssram_telems; static bool device_probed; =20 @@ -69,7 +82,7 @@ static inline u64 get_base(void __iomem *addr, u32 offset) } =20 static int -pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, unsigned int pmc_idx, = u32 offset) +pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; @@ -109,6 +122,20 @@ pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, un= signed int pmc_idx, u32 of return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); } =20 +static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev) +{ + int ret; + + ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_MAIN, 0); + if (ret) + return ret; + + pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); + pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + + return 0; +} + /** * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr info= rmation * @pmc_idx: Index of the PMC @@ -151,6 +178,8 @@ EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { + const struct ssram_type *ssram_type; + enum resource_method method; int ret; =20 pmc_ssram_telems =3D devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems)= * MAX_NUM_PMC, @@ -160,18 +189,25 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de goto probe_finish; } =20 + ssram_type =3D (const struct ssram_type *)id->driver_data; + if (!ssram_type) { + dev_dbg(&pcidev->dev, "missing driver data\n"); + ret =3D -EINVAL; + goto probe_finish; + } + + method =3D ssram_type->method; + ret =3D pcim_enable_device(pcidev); if (ret) { dev_dbg(&pcidev->dev, "failed to enable PMC SSRAM device\n"); goto probe_finish; } =20 - ret =3D pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_MAIN, 0); - if (ret) - goto probe_finish; - - pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); - pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + if (method =3D=3D RES_METHOD_PCI) + ret =3D pmc_ssram_telemetry_pci_init(pcidev); + else + ret =3D -EINVAL; =20 probe_finish: /* @@ -184,13 +220,20 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de } =20 static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN), + .driver_data =3D (kernel_ulong_t)&pci_main }, { } }; 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X-CSE-ConnectionGUID: YidymXkkTReJ3kwCty6JHA== X-CSE-MsgGUID: T5hzvP/0S3OHn+NE6jJS0w== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86038004" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86038004" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: FcNZuXiGSFStAMTdTW+WAA== X-CSE-MsgGUID: v/d+hMmGR3qd5tH8BYZGPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832869" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 11/15] platform/x86/intel/pmc/ssram: Refactor DEVID/PWRMBASE extraction into helper Date: Fri, 12 Jun 2026 14:01:52 -0700 Message-ID: <75ca738c88729f37f286f342c1fe8ff86f7eafe7.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move DEVID/PWRMBASE extraction into pmc_ssram_get_devid_pwrmbase(). This is a preparatory refactor to place functionality in a common helper for reuse by a subsequent patch. Additionally add missing bits.h include and define SSRAM_BASE_ADDR_MASK for the address extraction mask. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 changes: - Added missing include for GENMASK_ULL() used in get_base= () - Defined SSRAM_BASE_ADDR_MASK macro to replace magic mask constant GENMASK_ULL(63, 3) .../platform/x86/intel/pmc/ssram_telemetry.c | 33 ++++++++++++------- 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 05f213aa108f..211d842df449 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -22,6 +23,7 @@ #define SSRAM_PCH_OFFSET 0x60 #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 +#define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3) =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 @@ -40,6 +42,23 @@ static const struct ssram_type pci_main =3D { static struct pmc_ssram_telemetry *pmc_ssram_telems; static bool device_probed; =20 +static inline u64 get_base(void __iomem *addr, u32 offset) +{ + return lo_hi_readq(addr + offset) & SSRAM_BASE_ADDR_MASK; +} + +static void pmc_ssram_get_devid_pwrmbase(void __iomem *ssram, unsigned int= pmc_idx) +{ + u64 pwrm_base; + u16 devid; + + pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); + devid =3D readw(ssram + SSRAM_DEVID_OFFSET); + + pmc_ssram_telems[pmc_idx].devid =3D devid; + pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; +} + static int pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 ssram_base, void _= _iomem *ssram) { @@ -76,18 +95,12 @@ pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64= ssram_base, void __iomem return intel_vsec_register(&pcidev->dev, &info); } =20 -static inline u64 get_base(void __iomem *addr, u32 offset) -{ - return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); -} - static int pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; 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X-CSE-ConnectionGUID: 7v2YnnNZTCGEglB6ZD0xxA== X-CSE-MsgGUID: MtxjJQpRTDSInYW1o+L7dA== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86038008" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86038008" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: ADr9z0LPQB+yygOqlMQddg== X-CSE-MsgGUID: OlKovAh+TSCzbZr1wCLqJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832870" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 12/15] platform/x86/intel/pmc/ssram: Switch to static array with per-index probe state Date: Fri, 12 Jun 2026 14:01:53 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace devm-allocated pmc_ssram_telems pointer with a fixed-size static array and introduce per-index probe state tracking. This prepares the driver for later per-device probe handling where tying the PMC tracking storage to one probed PCI device is no longer suitable. The previous single global device_probed flag cannot describe the state of individual PMC indices when multiple devices can be probed independently. Replace it with per-index state (UNPROBED, PROBING, PRESENT, ABSENT) and a staging cache that publishes discovered values only after probe completes. This avoids races between probe/unbind and concurrent readers. Use marked state accesses with release/acquire ordering to prevent compiler and CPU reordering issues across concurrent probe/unbind cycles. This patch was substantially rewritten in later revisions. Originally developed from earlier work by Xi Pardee. Signed-off-by: David E. Box Assisted-by: Claude:claude-sonnet-4-5 --- V8 changes: - Added descriptive comments for per-index probe state tracking fields and publish logic. - Added kernel-doc state-flow description for pmc_ssram_telemetry_get_pmc_info(). - Updated commit message attribution note to acknowledge original v1 work while reflecting substantial rerolling. V7 changes: - Made PMC_SSRAM_UNPROBED explicitly =3D 0 for clarity. - Replace the explicit smp_wmb() / smp_rmb() pairing with smp_store_release() / smp_load_acquire() when publishing and consuming the per-index SSRAM state. V6 changes: - Squashed patch combining v5 patches 10 ("Use fixed-size static pmc array") and 13 ("Refactor memory barrier for reentrant probe"). Both patches addressed per-index probe state tracking and reentrant probe protection, so they were combined for better logical cohesion. - Added per-index probe state enum (UNPROBED, PROBING, PRESENT, ABSENT) to replace devid overload where devid was used as both payload and probe state indicator. This fixes stale data issues on reprobe, distinguishes between -EAGAIN (probe in progress) and -ENODEV (probe failed) error semantics, and prevents stale values from being visible after failed reprobe (Ilpo/Sashiko/Claude). - Added staging cache that publishes devid and base_addr only after probe completes successfully to avoid races between probe/unbind and concurrent readers. - Added .remove callback to handle proper state cleanup on driver unbind. - Used READ_ONCE/WRITE_ONCE for pmc_ssram_state[] accesses to prevent compiler optimizations from causing issues across concurrent probe/ unbind cycles. V5 - No changes (for both original patches) V4 - No changes (for both original patches) V3 - No changes (for both original patches) V2 changes (from original patch 10 "Use fixed-size static pmc array"): - Replaced hardcoded array size [3] with MAX_NUM_PMC constant V2 changes (from original patch 13 "Refactor memory barrier"): - Expanded commit message to explain synchronization rationale - Remove unused probe_finish label associated with the old global flag .../platform/x86/intel/pmc/ssram_telemetry.c | 218 ++++++++++++++---- 1 file changed, 176 insertions(+), 42 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 211d842df449..3349f65ae7bd 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -24,6 +25,7 @@ #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 #define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3) +#define SSRAM_PCI_PMC_MASK (BIT(PMC_IDX_MAIN) | BIT(PMC_IDX_IOE) | BIT(PMC= _IDX_PCH)) =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 @@ -39,15 +41,37 @@ static const struct ssram_type pci_main =3D { .method =3D RES_METHOD_PCI, }; =20 -static struct pmc_ssram_telemetry *pmc_ssram_telems; -static bool device_probed; +enum pmc_ssram_state { + PMC_SSRAM_UNPROBED =3D 0, + PMC_SSRAM_PROBING, + PMC_SSRAM_PRESENT, + PMC_SSRAM_ABSENT, +}; + +static enum pmc_ssram_state pmc_ssram_state[MAX_NUM_PMC]; +static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; + +struct pmc_ssram_probe_cache { + /* Per-index values staged by probe before publishing globally. */ + struct pmc_ssram_telemetry telems[MAX_NUM_PMC]; + /* PMCs this probe instance is responsible for publishing. */ + unsigned long owned_mask; + /* Subset of owned_mask that was discovered successfully. */ + unsigned long valid_mask; +}; + +struct pmc_ssram_drvdata { + /* PMCs published by this bound device; used to unpublish on remove. */ + unsigned long owned_mask; +}; =20 static inline u64 get_base(void __iomem *addr, u32 offset) { return lo_hi_readq(addr + offset) & SSRAM_BASE_ADDR_MASK; } =20 -static void pmc_ssram_get_devid_pwrmbase(void __iomem *ssram, unsigned int= pmc_idx) +static void pmc_ssram_get_devid_pwrmbase(struct pmc_ssram_probe_cache *pro= be_cache, + void __iomem *ssram, unsigned int pmc_idx) { u64 pwrm_base; u16 devid; @@ -55,8 +79,45 @@ static void pmc_ssram_get_devid_pwrmbase(void __iomem *s= sram, unsigned int pmc_i pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); devid =3D readw(ssram + SSRAM_DEVID_OFFSET); =20 - pmc_ssram_telems[pmc_idx].devid =3D devid; - pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; + probe_cache->telems[pmc_idx].base_addr =3D pwrm_base; + probe_cache->telems[pmc_idx].devid =3D devid; +} + +static void pmc_ssram_publish_absent(unsigned int pmc_idx) +{ + /* + * Publish only the state without modifying base_addr and devid. This + * lets a reader that already observed PRESENT finish copying the + * previous values even if unbind concurrently publishes ABSENT. Readers + * that observe ABSENT return -ENODEV without accessing data. + */ + smp_store_release(&pmc_ssram_state[pmc_idx], PMC_SSRAM_ABSENT); +} + +static void pmc_ssram_publish_present(struct pmc_ssram_probe_cache *probe_= cache, + unsigned int pmc_idx) +{ + /* + * The devid and base_addr fields are read from hardware MMIO registers + * whose values are stable for a given PMC index. A reader that observed + * PRESENT from an earlier probe can safely copy them while a concurrent + * rebind republishes those fields because both probes read the same + * hardware values. + */ + pmc_ssram_telems[pmc_idx] =3D probe_cache->telems[pmc_idx]; + /* + * Publish base_addr and devid before publishing PRESENT. Pairs with the + * acquire load in the reader that consumes them after observing PRESENT. + */ + smp_store_release(&pmc_ssram_state[pmc_idx], PMC_SSRAM_PRESENT); +} + +static void pmc_ssram_mark_probing(unsigned long mask) +{ + unsigned long bit; + + for_each_set_bit(bit, &mask, MAX_NUM_PMC) + WRITE_ONCE(pmc_ssram_state[bit], PMC_SSRAM_PROBING); } =20 static int @@ -96,11 +157,14 @@ pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u6= 4 ssram_base, void __iomem } =20 static int -pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) +pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache, + unsigned int pmc_idx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; u64 ssram_base; + int ret; =20 ssram_base =3D pci_resource_start(pcidev, 0); tmp_ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); @@ -125,22 +189,38 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcide= v, unsigned int pmc_idx, u3 ssram =3D no_free_ptr(tmp_ssram); } =20 - pmc_ssram_get_devid_pwrmbase(ssram, pmc_idx); + pmc_ssram_get_devid_pwrmbase(probe_cache, ssram, pmc_idx); =20 /* Find and register and PMC telemetry entries */ - return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); + ret =3D pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); + if (ret) + return ret; + + probe_cache->valid_mask |=3D BIT(pmc_idx); + + return 0; } =20 -static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev) +static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache) { int ret; =20 - ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_MAIN, 0); + ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_MAIN= , 0); if (ret) return ret; =20 - pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); - pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + /* + * If MAIN PMC enumeration is successful but either IOE or PCH fail, + * don't fail probe as the MAIN PMC is still useful as it provides the + * global reset and slp_s0 counter access. Failed or missing secondary + * PMCs are left out of valid_mask and published as absent. + */ + pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_IOE, + SSRAM_IOE_OFFSET); + + pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_PCH, + SSRAM_PCH_OFFSET); =20 return 0; } @@ -150,62 +230,106 @@ static int pmc_ssram_telemetry_pci_init(struct pci_d= ev *pcidev) * @pmc_idx: Index of the PMC * @pmc_ssram_telemetry: pmc_ssram_telemetry structure to store the PMC = information * + * State flow per PMC index: + * - PMC_SSRAM_UNPROBED: Probe has not started for this index. + * - PMC_SSRAM_PROBING: Probe is currently discovering data for this inde= x. + * - PMC_SSRAM_PRESENT: base_addr/devid were published and can be read. + * - PMC_SSRAM_ABSENT: No data is available for this index. + * + * Readers use an acquire load of the state. If state is PRESENT, reads of + * base_addr/devid are ordered after the state observation and pair with t= he + * writer's release-store when publishing PRESENT. + * * Return: * * 0 - Success * * -EAGAIN - Probe function has not finished yet. Try again. * * -EINVAL - Invalid pmc_idx - * * -ENODEV - PMC device is not available + * * -ENODEV - PMC device is not available (hardware absent or driver = failed to initialize) */ int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx, struct pmc_ssram_telemetry *pmc_ssram_telemetry) { + enum pmc_ssram_state state; + + if (pmc_idx >=3D MAX_NUM_PMC) + return -EINVAL; + /* * PMCs are discovered in probe function. If this function is called befo= re - * probe function complete, the result would be invalid. Use device_probed - * variable to avoid this case. Return -EAGAIN to inform the consumer to = call - * again later. + * probe function complete, the result would be invalid. Use per-PMC state + * to inform the consumer to call again later. */ - if (!device_probed) + state =3D smp_load_acquire(&pmc_ssram_state[pmc_idx]); + if (state =3D=3D PMC_SSRAM_UNPROBED || state =3D=3D PMC_SSRAM_PROBING) return -EAGAIN; =20 - /* - * Memory barrier is used to ensure the correct read order between - * device_probed variable and PMC info. - */ - smp_rmb(); - if (pmc_idx >=3D MAX_NUM_PMC) - return -EINVAL; - - if (!pmc_ssram_telems || !pmc_ssram_telems[pmc_idx].devid) + if (state =3D=3D PMC_SSRAM_ABSENT) return -ENODEV; =20 + /* + * Acquire semantics order reads of devid and base_addr after observing + * PRESENT and pair with the writer's release-store. + */ pmc_ssram_telemetry->devid =3D pmc_ssram_telems[pmc_idx].devid; pmc_ssram_telemetry->base_addr =3D pmc_ssram_telems[pmc_idx].base_addr; return 0; } EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 +static void pmc_ssram_publish_absent_mask(unsigned long mask) +{ + unsigned long bit; + + for_each_set_bit(bit, &mask, MAX_NUM_PMC) + pmc_ssram_publish_absent(bit); +} + +static void pmc_ssram_publish_telems(struct pmc_ssram_probe_cache *probe_c= ache, int ret) +{ + unsigned long bit; + + /* If probe failed, all owned indexes become absent for readers. */ + if (ret) { + pmc_ssram_publish_absent_mask(probe_cache->owned_mask); + return; + } + + /* Publish each owned index independently based on discovery result. */ + for_each_set_bit(bit, &probe_cache->owned_mask, MAX_NUM_PMC) { + if (probe_cache->valid_mask & BIT(bit)) + pmc_ssram_publish_present(probe_cache, bit); + else + pmc_ssram_publish_absent(bit); + } +} + static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { + struct pmc_ssram_probe_cache probe_cache =3D {}; + struct pmc_ssram_drvdata *drvdata; const struct ssram_type *ssram_type; enum resource_method method; int ret; =20 - pmc_ssram_telems =3D devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems)= * MAX_NUM_PMC, - GFP_KERNEL); - if (!pmc_ssram_telems) { - ret =3D -ENOMEM; - goto probe_finish; - } - ssram_type =3D (const struct ssram_type *)id->driver_data; if (!ssram_type) { dev_dbg(&pcidev->dev, "missing driver data\n"); - ret =3D -EINVAL; - goto probe_finish; + return -EINVAL; } =20 method =3D ssram_type->method; + if (method =3D=3D RES_METHOD_PCI) + probe_cache.owned_mask =3D SSRAM_PCI_PMC_MASK; + else + return -EINVAL; + + pmc_ssram_mark_probing(probe_cache.owned_mask); + + drvdata =3D devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) { + ret =3D -ENOMEM; + goto probe_finish; + } =20 ret =3D pcim_enable_device(pcidev); if (ret) { @@ -214,20 +338,29 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de } =20 if (method =3D=3D RES_METHOD_PCI) - ret =3D pmc_ssram_telemetry_pci_init(pcidev); + ret =3D pmc_ssram_telemetry_pci_init(pcidev, &probe_cache); else ret =3D -EINVAL; =20 + if (!ret) { + drvdata->owned_mask =3D probe_cache.owned_mask; + pci_set_drvdata(pcidev, drvdata); + } + probe_finish: - /* - * Memory barrier is used to ensure the correct write order between PMC i= nfo - * and device_probed variable. - */ - smp_wmb(); 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X-CSE-ConnectionGUID: /lI5ih+/QLmlVXVMDLMgXQ== X-CSE-MsgGUID: DP1YdYT/RR2QHC4ybB/72A== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86038009" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86038009" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: SS5SdM+nTealxkPA0Bg5NQ== X-CSE-MsgGUID: ufMqCyOgTxCtz5LaoVjGgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832871" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 13/15] platform/x86/intel/pmc/ssram: Add ACPI discovery scaffolding Date: Fri, 12 Jun 2026 14:01:54 -0700 Message-ID: <54850d175993ee38aef99707f954492d24684dcc.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the SSRAM telemetry driver for ACPI-based discovery by adding support for reading telemetry regions from ACPI _DSD properties. Add pmc_ssram_telemetry_acpi_init() to parse _DSD for telemetry discovery tables and register them with the Intel VSEC framework. Extend ssram_type with a p_index field to specify which PMC index each ACPI device owns (unlike PCI which discovers all three PMCs from one device). At this stage, no platform IDs are wired to use ACPI discovery - existing devices continue using the PCI path. Follow-on patches will add platform support. Assisted-by: Claude:claude-sonnet-4-5 Signed-off-by: Xi Pardee Signed-off-by: David E. Box --- V8 - No changes V7 - No changes V6 - No changes V5 changes: - Fix dsd_buf leak by moving the __free(pmc_acpi_free) declaration after acpi_evaluate_object() populates buf.pointer, and switched pmc_find_telem_guid(buf.pointer) to operate on dsd_buf so cleanup releases the actual allocation. - Split acpi_handle declaration from ACPI_HANDLE() assignment and placed the assignment immediately before the !handle check (Ilpo). - Reordered local variables in pmc_ssram_telemetry_acpi_init() in reverse-xmas-tree order (Ilpo). V4 - Replaced local raw ACPI discovery pointer type u32 (*)[4] with acpi_disc_t in SSRAM ACPI initialization path. V3 - No changes V2 changes: - Fixed cleanup patterns using __free() attributes - Addressed Ilpo's recommendations for safer cleanup.h patterns .../platform/x86/intel/pmc/ssram_telemetry.c | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 3349f65ae7bd..10462fa7ebbf 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -31,14 +32,17 @@ DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *= , if (_T) iounmap(_T)) =20 enum resource_method { RES_METHOD_PCI, + RES_METHOD_ACPI, }; =20 struct ssram_type { enum resource_method method; + enum pmc_index p_index; }; =20 static const struct ssram_type pci_main =3D { .method =3D RES_METHOD_PCI, + .p_index =3D PMC_IDX_MAIN, }; =20 enum pmc_ssram_state { @@ -225,6 +229,73 @@ static int pmc_ssram_telemetry_pci_init(struct pci_dev= *pcidev, return 0; } =20 +static int pmc_ssram_telemetry_get_pmc_acpi(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache, + unsigned int pmc_idx) +{ + u64 ssram_base; + + ssram_base =3D pci_resource_start(pcidev, 0); + if (!ssram_base) + return -ENODEV; + + void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D + ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + return -ENOMEM; + + pmc_ssram_get_devid_pwrmbase(probe_cache, ssram, pmc_idx); + probe_cache->valid_mask |=3D BIT(pmc_idx); + + return 0; +} + +static int pmc_ssram_telemetry_acpi_init(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache, + enum pmc_index index) +{ + struct intel_vsec_header header; + struct intel_vsec_header *headers[2] =3D { &header, NULL }; + struct acpi_buffer buf =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct intel_vsec_platform_info info =3D { }; + union acpi_object *dsd; + acpi_handle handle; + acpi_status status; + int ret; + + handle =3D ACPI_HANDLE(&pcidev->dev); + if (!handle) + return -ENODEV; + + status =3D acpi_evaluate_object(handle, "_DSD", NULL, &buf); + if (ACPI_FAILURE(status)) + return -ENODEV; + + void *dsd_buf __free(pmc_acpi_free) =3D buf.pointer; + + dsd =3D pmc_find_telem_guid(dsd_buf); + if (!dsd) + return -ENODEV; + + acpi_disc_t disc __free(kfree) =3D pmc_parse_telem_dsd(dsd, &header); + if (IS_ERR(disc)) + return PTR_ERR(disc); + + info.headers =3D headers; + info.caps =3D VSEC_CAP_TELEMETRY; + info.acpi_disc =3D disc; + info.src =3D INTEL_VSEC_DISC_ACPI; + + /* This is an ACPI companion device. PCI BAR will be used for base addr. = */ + info.base_addr =3D 0; + + ret =3D intel_vsec_register(&pcidev->dev, &info); + if (ret) + return ret; + + return pmc_ssram_telemetry_get_pmc_acpi(pcidev, probe_cache, index); +} + /** * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr info= rmation * @pmc_idx: Index of the PMC @@ -309,6 +380,7 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de struct pmc_ssram_drvdata *drvdata; const struct ssram_type *ssram_type; enum resource_method method; + enum pmc_index index; int ret; =20 ssram_type =3D (const struct ssram_type *)id->driver_data; @@ -317,9 +389,12 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *p= cidev, const struct pci_de return -EINVAL; } =20 + index =3D ssram_type->p_index; method =3D ssram_type->method; if (method =3D=3D RES_METHOD_PCI) probe_cache.owned_mask =3D SSRAM_PCI_PMC_MASK; + else if (method =3D=3D RES_METHOD_ACPI) + probe_cache.owned_mask =3D BIT(index); else return -EINVAL; =20 @@ -339,6 +414,8 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de =20 if (method =3D=3D RES_METHOD_PCI) ret =3D pmc_ssram_telemetry_pci_init(pcidev, &probe_cache); + else if (method =3D=3D RES_METHOD_ACPI) + ret =3D pmc_ssram_telemetry_acpi_init(pcidev, &probe_cache, index); else ret =3D -EINVAL; =20 @@ -389,6 +466,7 @@ static struct pci_driver pmc_ssram_telemetry_driver =3D= { module_pci_driver(pmc_ssram_telemetry_driver); =20 MODULE_IMPORT_NS("INTEL_VSEC"); +MODULE_IMPORT_NS("INTEL_PMC_CORE"); MODULE_AUTHOR("Xi Pardee "); MODULE_DESCRIPTION("Intel PMC SSRAM Telemetry driver"); MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F2003D5674; Fri, 12 Jun 2026 21:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298142; cv=none; b=LNsZRXnLSDZoe6hTT5BxwgL2F27nT5yzdreMs2TWsUQpsfHFIT5UHs9Ntuwe9AXnhHvrZ1Fr4yJDXKtov6QgGaeDKL+QbtsA7JDHiiNh9ZtmRL+TkKNplXS0P+Zwl7wPSxNTECz8v6CT68BIy3mBGKDmgQvtXkh4IFh7254000w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298142; c=relaxed/simple; bh=2LyoUp/u3z2V0L3Fugc+0ZewYUnR19ZCFL5d4L8X1Co=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pl7O1Nl0jNVAs7E6EcN/BKMVTdLepQLRMlzVdH+QttIPpzF8KYdrlRtkpmbE9NVsXZ8tjB6IjtFUYq5V3tTz+iRQ7lNuB3wnEQcuhFlkZDlnf2Q/0yWRAk0buaF7fDS8iPAY4Iu4pj4TFPSYSttXY1FGJ0sUYlBGye1eWcsyT4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YK9qUo0e; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YK9qUo0e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298142; x=1812834142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2LyoUp/u3z2V0L3Fugc+0ZewYUnR19ZCFL5d4L8X1Co=; b=YK9qUo0ecCWVhAhlP+iPIsuqecTs7JKuudvTNC7RqQrzep4lGoYiSimJ y93sZju1wvfG0Fa49V9/WFxnaCtbD0F+h04GIxM6kQ8s6R9jP1oSXnosf Z83qV4r8zcOdAxZ0+Mnxer9Q518SFuCeU0B+SR+jKDyRM8W2Vl4C/Lt3P t+MQ+kYVxlMj7rYvueVDPd07G3sAnUJop+FKE6+L8AJY1woq1O7imj9iG t1rZWP4pF/1Bp8FZVtgmaSsn+ymqH2agSCcWtlZ0XOpYr2FHJJAMqJkDr qT0JhypfYey3FrIJUhtQEN0xB0vQf2vsgR595hORvsBm82Jr2IlmQKp4t w==; X-CSE-ConnectionGUID: fN2qVLVFQemP+nhce4mumA== X-CSE-MsgGUID: dqha8QONSFCMcoRfeYtKAw== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86038014" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86038014" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: QsBCz5uTRwmMLZQ0UaH8hQ== X-CSE-MsgGUID: Kgg+gzFPTCa6vl2Oq9QmQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832872" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 14/15] platform/x86/intel/pmc/ssram: Make PMT registration optional Date: Fri, 12 Jun 2026 14:01:55 -0700 Message-ID: <4f4c324977951f6082bf2218c8b911e1ae7e0a7b.1781294741.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SSRAM telemetry driver extracts essential PMC device ID and power management base address information that intel_pmc_core depends on for core functionality. If PMT registration failure prevents this critical data from being available, intel_pmc_core operation would break entirely. Therefore, PMT registration failures must not block access to this data. Change the behavior to log a warning when PMT registration fails but continue with successful driver initialization, ensuring the primary telemetry data remains accessible to dependent drivers. Signed-off-by: David E. Box --- V8 - No changes V7 - No changes V6 - No changes V5 - No changes V4 - No changes V3 changes: - Dropped the standalone cleanup-pattern patch from this refreshed series retaining the simpler ssram pointer flow requested in review. - Folded PMT-registration-optional handling onto that simpler flow with no intended functional change. V2 changes: - Update commit message for clarity - Also apply the PCI telemetry path drivers/platform/x86/intel/pmc/ssram_telemetry.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 10462fa7ebbf..9a8922045ab7 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -198,7 +198,7 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, /* Find and register and PMC telemetry entries */ ret =3D pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); if (ret) - return ret; + dev_warn(&pcidev->dev, "could not register PMT\n"); =20 probe_cache->valid_mask |=3D BIT(pmc_idx); =20 @@ -291,7 +291,7 @@ static int pmc_ssram_telemetry_acpi_init(struct pci_dev= *pcidev, =20 ret =3D intel_vsec_register(&pcidev->dev, &info); if (ret) - return ret; + dev_warn(&pcidev->dev, "could not register PMT\n"); =20 return pmc_ssram_telemetry_get_pmc_acpi(pcidev, probe_cache, index); } --=20 2.43.0 From nobody Sun Jun 14 06:04:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FDCF3D5C3C; Fri, 12 Jun 2026 21:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298143; cv=none; b=b2vwKj7MDhEPkfvKWG7kq0qmbWIBYHXxsIyAVHKRtLg1aGbpaiz/IpjzArLGmVogtTONhV4/z+obcQTPJ6uu+ey3Enkx0HzxAhhede8vSaa/ZUsKbsL22De4v6koS3ijsD8gbZGfBAsWVXysCAuLHnDczN88eCKTPThIROqltfI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781298143; c=relaxed/simple; bh=G1wrUpghchBD3EDcxxUZFLMd8LelWaadof/b4g6/DlQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rzqko2paibeL6WmOGp2E17/lXqWOuaE5MUN7SeSeoxT/f/DzamSIIylWtyAzcAJLjs98YHdn9Cl65MDUFOfbv6XTto5d6i8cOrkgVXKpaoDv6O72PVjrqNpPTn546HY7zAuYmC7bgM4MGX2nU0zKTs4s3kTq5zj55pT7ka5JcR0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AxsFjHH4; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AxsFjHH4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781298142; x=1812834142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G1wrUpghchBD3EDcxxUZFLMd8LelWaadof/b4g6/DlQ=; b=AxsFjHH4OWDf88MuOXzG5sAYJWu9KzpxC7Sk+HrJZ0Yus7Csgdb0Wd8Y o67K980MTuOAlj1mvakfetfKqbLTnbGt5XatIchSIiVASZ+yKtn/KY+QR dIt8GehgxggGSnpMA5l1+A83h9kpBYWI+BWQH8fEsq1XIbTDdhR4HVkeo s8wqpEZkjxmELlQ4bz4A3FKvlJybC06L6BM++KSabrUVIC3FDr0oyr0v2 SHfCnEwYY6k0r+ri0RvjF8iZe+8kEsmVv6pZlcCmC1iLFhDsQcgoiInek wbDVDX5McRiZXhE4ilcF+QHq1kzmLt25R8T+dA1OeoMhGMkoiiVqsQRAH A==; X-CSE-ConnectionGUID: kuwVahGqTLq0v7RhV0qUeg== X-CSE-MsgGUID: bLVTqCJaTOaeMl0gvlnoJA== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="86038015" X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="86038015" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:13 -0700 X-CSE-ConnectionGUID: W6t+v9mQTFO2fq7rb6UfJQ== X-CSE-MsgGUID: tCKceSaVR4q6ZYIBLv6F3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,201,1774335600"; d="scan'208";a="250832874" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 14:02:12 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v8 15/15] platform/x86/intel/pmc: Add NVL PCI IDs for SSRAM telemetry discovery Date: Fri, 12 Jun 2026 14:01:56 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Nova Lake S PMC device IDs to enable binding of the SSRAM telemetry driver on NVL platforms, and map them to the ACPI-based discovery policy. Signed-off-by: David E. Box --- V8 - No changes V7 - No changes V6 - Dropped NVL product defines in core.h as they we already included in a prior patch from Xi. V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/ssram_telemetry.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 9a8922045ab7..8e280ec525a6 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -45,6 +45,16 @@ static const struct ssram_type pci_main =3D { .p_index =3D PMC_IDX_MAIN, }; =20 +static const struct ssram_type acpi_main =3D { + .method =3D RES_METHOD_ACPI, + .p_index =3D PMC_IDX_MAIN, +}; + +static const struct ssram_type acpi_pch =3D { + .method =3D RES_METHOD_ACPI, + .p_index =3D PMC_IDX_PCH, +}; + enum pmc_ssram_state { PMC_SSRAM_UNPROBED =3D 0, PMC_SSRAM_PROBING, @@ -453,6 +463,12 @@ static const struct pci_device_id pmc_ssram_telemetry_= pci_ids[] =3D { .driver_data =3D (kernel_ulong_t)&pci_main }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN), .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDH), + .driver_data =3D (kernel_ulong_t)&acpi_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDS), + .driver_data =3D (kernel_ulong_t)&acpi_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCHS), + .driver_data =3D (kernel_ulong_t)&acpi_pch }, { } }; MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids); --=20 2.43.0