From nobody Sun Jun 28 02:48:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E29B6425CF7; Wed, 10 Jun 2026 15:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781104203; cv=none; b=JQ8AnrurVRnGrz0FDxS1Y4YjNPNAA1ks4qqP98jVhPnXIwQaWnqXvsY/tN8DLp7GX0RJ1npRehFFqis2R4+s9Bl0o6VGbPE+C81SISVitP1ls6SWAb4eJ0lhKhmQ34FHpoilj7yAFIGHBOFu3qzDuuv15JgGtDR53HykU1xmKeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781104203; c=relaxed/simple; bh=MZjsy56YpmJ328jnl4Y1aT7yEkjn4FAnrY5uX3ibE3s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MEFGtBwJOAvcDV/BKIdVSeKXF73l+0SFTKTuWYXkrCQYc5evaao0wn+6BqxnwBYoY6Zln2iXOvEZczacKKrolMWJv6MT9b2Q/Q0VXjtavKPbHswzhySprJNOr923DT/sZumEuuqEILFWHtW/3UGk9TQZUXLmN+BRNrO5n41h/Cw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id D330B1F00898; Wed, 10 Jun 2026 15:09:59 +0000 (UTC) From: Geert Uytterhoeven To: Arnd Bergmann , Krzysztof Kozlowski , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Thierry Reding , Jonathan Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 1/2] arm64: dts: exynos: gs101: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 10 Jun 2026 17:09:53 +0200 Message-ID: <9967bb6d5a9f371a7e02a16e5bc8057bcdb657a9.1781103355.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- v2: - Rebase on top of commit d0298724f901d45c ("arm64: dts: exynos: Add EL2 virtual timer interrupt") in soc/for-next. --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 86933f22647b701a..d4250f51b13092a2 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1853,11 +1853,11 @@ apm_sram: sram@2039000 { timer { compatible =3D "arm,armv8-timer"; interrupts =3D - , - , - , - , - ; + , + , + , + , + ; }; }; =20 --=20 2.43.0 From nobody Sun Jun 28 02:48:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E570841C2EF; Wed, 10 Jun 2026 15:10:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781104206; cv=none; b=ZuNIa/As9SZDrmyxtfDEN98TlKPAOvv0OjlvoxRoO0Cii2Wcz6fAkMaJfpuXBEVaTkoV69ecnLLD/Q/gH1pC/94u2cFkFVpwi20uFP6G4+dmeeQqtK2rEy+h+FahZgOJLT8tLVQGWqW/DBa8L0Cmn5geb2Oi025wKguwnaUDL6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781104206; c=relaxed/simple; bh=UnORoybj1kwAjQwxs/GmgO7PN5XvskdkbObR4fnn0lc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tGj1itLclSJ1oYeG1KaEt4LRa8tDqBePKbgISV7FGtc2bKNo71Jgxb17cx521/EgnajCFZTaTkbJBxwamopoxk8+1tGyp6OnC6Q9e5foJ9pIfczwIBhKU59UcnsSFkV0qcqpYlU3NPsWDAjtvGUcC1OIjCz6MTZ6KXVbbN5KrOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0611C1F00893; Wed, 10 Jun 2026 15:10:02 +0000 (UTC) From: Geert Uytterhoeven To: Arnd Bergmann , Krzysztof Kozlowski , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Thierry Reding , Jonathan Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 2/2] arm64: tegra: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 10 Jun 2026 17:09:54 +0200 Message-ID: <0be8708c53609bb64bfa31d84dffc5c2d56b5679.1781103355.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- v2: - No changes. --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 04a95b6658caaa92..390609fee09c9da0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4083,7 +4083,7 @@ gic: interrupt-controller@f400000 { reg =3D <0x0 0x0f400000 0x0 0x010000>, /* GICD */ <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent =3D <&gic>; - interrupts =3D ; + interrupts =3D ; =20 #redistributor-regions =3D <1>; #interrupt-cells =3D <3>; @@ -5869,10 +5869,10 @@ tj-thermal { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; interrupt-parent =3D <&gic>; always-on; }; --=20 2.43.0