From nobody Mon Jun 8 08:53:11 2026 Received: from mail-244123.protonmail.ch (mail-244123.protonmail.ch [109.224.244.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BB5A3E1CF0 for ; Wed, 3 Jun 2026 17:10:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780506659; cv=none; b=Tq5mxiX8+Oo3VhkzAgmma5UPiSHBFfpzCbOq67f9Dd29XgrSDIinth5uT5NOBBzeJkATBIluqGDgv+4GduDLZEB6wL7vPdqZyCMMvQ/remcT08u4xpuazsb2DeQz0giD4tpQm51+N+WwYpVvymYcVjAoUl5wiO8V1WRuNnGCQcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780506659; c=relaxed/simple; bh=LUOBYd4ORFeevaOtH4lY37Yfvcul1Ro63bhTSHnvaeA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nLf7PpWuJVRYEApVI6h6Vx8Q7FdeSAOljygw2UAGeRBZAzzp6nPx5xVpfHup97EgZoZX3MQBtqtPXzBN7jKFhD2stqtFOcR6t/xjnhqkTDk333+fNgOCzde+ypo9ptxzH2YnFD425YK8+EAk47dGJLEICW0dQJTCHowkrro6g8U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=BLNK/apa; arc=none smtp.client-ip=109.224.244.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="BLNK/apa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1780506654; x=1780765854; bh=4ungl5PVoOZETiiyungpsiTQW+V5hgoQ3LbM7ojo0Ww=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=BLNK/apaeAPHgrzQHwxv2pglq1HT8jQT9oq4JWgJ93iUhXYajnLaGMIw+ZrmHlMWa GfdR4EinF4yBiPhDW83oH/69sNgeyo4yJnfgwA8L7QtVkMYi9G/yt+K7aIlB2fYYOj bLeKw6UpsUz7huqCrdGr9QHsDrOZEtMD9dt+U9jZjP6ly2gmfOpS5Kb9xEpj2oAttU cLiSoeFXGUMLBosInkMf1d05uEPJtOhXtUgu6sjX/v21p5xoM6dT6uQ8a3hpgsIKcC 1oubNHvT0ZIexv2puFIu1nbW5Osqw3OyxMOcxOdrizbQl3K/hwC37LEc0JGN5jdD9P ZLqJU6dRRQ7Jg== Date: Wed, 03 Jun 2026 17:10:49 +0000 To: mingo@redhat.com, dave.hansen@linux.intel.com, bp@alien8.de From: Maciej Wieczor-Retman Cc: hpa@zytor.com, darwi@linutronix.de, tglx@kernel.org, sohil.mehta@intel.com, andrew.cooper3@citrix.com, linux-kernel@vger.kernel.org, x86@kernel.org, m.wieczorretman@pm.me, john.ogness@linutronix.de, ludloff@gmail.com, maciej.wieczor-retman@intel.com, x86-cpuid@lists.linux.dev Subject: [PATCH v2 1/2] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.1 Message-ID: In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: df0ea5f732669fd70db4f1f1f687deb11bcefcc1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman Update kcpuid's CSV file to version 3.1, as generated by x86-cpuid-db. Summary of the v3.1 changes: * Fix a few typos that were found during the kernel CPUID data model review. Also include fixes found using an LLM agent review. * Rename thrd_director_nclasses to hw_feedback_nclasses as it's the name used in Intel SDM. Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.r= st Signed-off-by: Maciej Wieczor-Retman --- tools/arch/x86/kcpuid/cpuid.csv | 52 ++++++++++++++++----------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index 9f5155c825ca..45a876d3519f 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v3.0 +# Generator: x86-cpuid-db v3.1 =20 # # Auto-generated file. @@ -177,7 +177,7 @@ 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR - 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 0x6, 0, ecx, 15:8, hw_feedback_nclasses , Number o= f Intel Thread Director classes 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting 0x6, 0, edx, 11:8, feedback_sz , Feedback= interface structure size, in 4K pages @@ -247,10 +247,10 @@ 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision - 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOVSB 0x7, 0, edx, 5, uintr , User int= errupts 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR + 0x7, 0, edx, 9, srbds_ctrl , SRBDS mi= tigation MSR 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit @@ -296,8 +296,8 @@ 0x7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable 0x7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} 0x7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U - 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed 0x7, 2, edx, 6, uclock_disable , UC-lock = disable =20 @@ -368,7 +368,7 @@ 0xd, 1, ecx, 8, xss_pt , PT state 0xd, 1, ecx, 10, xss_pasid , PASID st= ate 0xd, 1, ecx, 11, xss_cet_u , CET user= state - 0xd, 1, ecx, 12, xss_cet_p , CET supe= rvisor state + 0xd, 1, ecx, 12, xss_cet_s , CET supe= rvisor state 0xd, 1, ecx, 13, xss_hdc , HDC state 0xd, 1, ecx, 14, xss_uintr , UINTR st= ate 0xd, 1, ecx, 15, xss_lbr , LBR state @@ -433,7 +433,7 @@ 0x12, 1, eax, 7, secs_attr_kss , Key Sepa= ration and Sharing 0x12, 1, eax, 10, secs_attr_aexnotify , Enclave = threads: AEX notifications 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 - 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE + 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SSE 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (MPX BND0-BND3 registers) 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers) @@ -466,9 +466,9 @@ 0x14, 0, ecx, 0, topa_output , ToPA out= put scheme 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tab= les can hold multiple entries 0x14, 0, ecx, 2, single_range_output , Single-r= ange output - 0x14, 0, ecx, 3, trance_transport_output, Trace Tr= ansport subsystem output + 0x14, 0, ecx, 3, trace_transport_output , Trace Tr= ansport subsystem output 0x14, 0, ecx, 31, ip_payloads_lip , IP paylo= ads have LIP values (CS base included) - 0x14, 1, eax, 2:0, num_address_ranges , Number o= f configurable Address Ranges + 0x14, 1, eax, 2:0, num_address_ranges , Number o= f configurable address ranges 0x14, 1, eax, 31:16, mtc_periods_bmp , MTC peri= od encodings bitmap 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Th= reshold encodings bitmap 0x14, 1, ebx, 31:16, psb_periods_bmp , Configur= able PSB frequency encodings bitmap @@ -494,7 +494,7 @@ 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumeration scheme (not Intel) 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor - 0x17, 0, edx, 31:0, soc_stepping_id , Soc proj= ect stepping ID, assigned by vendor + 0x17, 0, edx, 31:0, soc_stepping_id , SoC proj= ect stepping ID, assigned by vendor 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor B= rand ID string, bytes subleaf_nr * (0 -> 3) 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor B= rand ID string, bytes subleaf_nr * (4 -> 7) 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor B= rand ID string, bytes subleaf_nr * (8 -> 11) @@ -514,12 +514,12 @@ 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs - 1 + 0x18, 31:0, edx, 25:14, tlb_max_addressable_ids, Max numb= er of addressable IDs - 1 =20 # Leaf 19H # Intel key locker =20 - 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key Locker restriction + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key locker restriction 0x19, 0, eax, 1, kl_no_encrypt , No-encry= pt key locker restriction 0x19, 0, eax, 2, kl_no_decrypt , No-decry= pt key locker restriction 0x19, 0, ebx, 0, aes_keylocker , AES key = locker instructions @@ -546,7 +546,7 @@ # Intel LBR (Last Branch Record) =20 0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR = stack depth bitmask - 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may= be cleared on MWAIT C-state > C1 + 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may= be cleared on MWAIT C-state > C1 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP c= ontain Last IP (otherwise effective IP) 0x1c, 0, ebx, 0, lbr_cpl , CPL filt= ering 0x1c, 0, ebx, 1, lbr_branch_filter , Branch f= iltering @@ -591,8 +591,8 @@ # Intel TD (Trust Domain) =20 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vend= or ID string bytes 0 - 3 - 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vend= or ID string bytes 8 - 11 - 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + 0x21, 0, ecx, 31:0, tdx_vendorid_2 , TDX vend= or ID string bytes 8 - 11 + 0x21, 0, edx, 31:0, tdx_vendorid_1 , TDX vend= or ID string bytes 4 - 7 =20 # Leaf 23H # Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) @@ -857,7 +857,7 @@ 0x8000000a, 0, edx, 1, lbrv , LBR virt= ualization 0x8000000a, 0, edx, 2, svm_lock , SVM lock 0x8000000a, 0, edx, 3, nrip_save , NRIP sav= e support on #VMEXIT -0x8000000a, 0, edx, 4, tsc_scale , MSR base= d TSC rate control +0x8000000a, 0, edx, 4, tsc_scale , MSR-base= d TSC rate control 0x8000000a, 0, edx, 5, vmcb_clean , VMCB cle= an bits support 0x8000000a, 0, edx, 6, flushbyasid , Flush by= ASID + Extended VMCB TLB_Control 0x8000000a, 0, edx, 7, decodeassists , Decode A= ssists support @@ -895,7 +895,7 @@ =20 0x8000001a, 0, eax, 0, fp_128 , Internal= FP/SIMD exec data path is 128-bits wide 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOV= U* better than MOVL*/MOVH* -0x8000001a, 0, eax, 2, fp_256 , internal= FP/SSE exec data path is 256-bits wide +0x8000001a, 0, eax, 2, fp_256 , Internal= FP/SSE exec data path is 256-bits wide =20 # Leaf 8000001BH # AMD IBS (Instruction-Based Sampling) @@ -917,7 +917,7 @@ # AMD LWP (Lightweight Profiling) =20 0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP = is available to application programs -0x8000001c, 0, eax, 1, os_lpwval , OS: LWPV= AL instruction +0x8000001c, 0, eax, 1, os_lwpval , OS: LWPV= AL instruction 0x8000001c, 0, eax, 2, os_lwp_ire , OS: Inst= ructions Retired Event 0x8000001c, 0, eax, 3, os_lwp_bre , OS: Bran= ch Retired Event 0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcac= he Miss Event @@ -934,13 +934,13 @@ 0x8000001c, 0, ecx, 5, lwp_data_addr , Cache mi= ss events report data cache address 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache la= tency rounding amount 0x8000001c, 0, ecx, 15:9, lwp_version , LWP vers= ion -0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, 32 event records units +0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, 32 event record units 0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches= Retired events can be filtered 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events: filter by cache level 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events: filter by latency 0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP = available -0x8000001c, 0, edx, 1, hw_lpwval , HW: LWPV= AL available +0x8000001c, 0, edx, 1, hw_lwpval , HW: LWPV= AL available 0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Inst= ructions Retired Event 0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Bran= ch Retired Event 0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcac= he Miss Event @@ -1040,8 +1040,8 @@ 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore 0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR not available -0x80000021, 0, eax, 10, fsrs , Fast Sho= rt Rep STOSB -0x80000021, 0, eax, 11, fsrc , Fast Sho= rt Rep CMPSB +0x80000021, 0, eax, 10, fsrs , Fast Sho= rt REP STOSB +0x80000021, 0, eax, 11, fsrc , Fast Sho= rt REP CMPSB 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR 0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 @@ -1093,9 +1093,9 @@ # Maximum Transmeta leaf + CPU vendor string =20 0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = Transmeta leaf -0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 -0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 -0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 +0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a vendor ID string bytes 0 - 3 +0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a vendor ID string bytes 8 - 11 +0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a vendor ID string bytes 4 - 7 =20 # Leaf 80860001H # Transmeta extended CPU features --=20 2.54.0 From nobody Mon Jun 8 08:53:11 2026 Received: from mail-106121.protonmail.ch (mail-106121.protonmail.ch [79.135.106.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B26B13E559A for ; Wed, 3 Jun 2026 17:11:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.121 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780506669; cv=none; b=IEtQiwN8LicwcJ1EKpwJbn2Y3ELsF/36w4taH1XmIqEjrUA+qpNlLyj8NoBeqtB4FmecbKeXuJHzdSBODBuZKM47ho+G80NgywA5ueOslTPVRH/UKY0li/Ofw6FWt90ZYRBorJz+MTEnmxLVP7ls7OOiYwm5oFhN0mrnf8ObHS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780506669; c=relaxed/simple; bh=VymDrokPGsDuZzo6kL+Hge7SAusWnvFYyT00mvnN7Nw=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YCN89d4TgSt/Mp0OycYZerp2uqsXrfLCYjEYW0d1eaytmY8DUOpS1X0chLMW44c++yJMui8PZKrV6JL8Gh1tqI+eSPeqmwSjod452FPfwkhnmpf8MMSqRz3MDZMx6/Utr2YHwLruzNgqw9uBlkpiPBEwFNAdT8hxSZPvBux/Hkw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=X/fXbc8r; arc=none smtp.client-ip=79.135.106.121 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="X/fXbc8r" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1780506663; x=1780765863; bh=dSVdZb/n6EEsjkOMirUNeqjA4XPdTSpYPJQeM9Wk9MU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=X/fXbc8ro8TT2EUYm/CMKTLeKxyeXRI2/j0mf9/4m4IF2rzqupxynzZG9THnoSwTr Hu4GoOUd32FLdKHN0TVBRo81kbjs2cFns2a12tiWYsMwwDdxAxFkhpOj6FtluX20L6 cAkATBtrjCTsrgvxUd9oq9h7Hz2cMoAeSoGARawVZJMaQQRkNl226qHspMAB8qJdDv sQ/khYdzl1eVkuWSF8OGtCaS/5t0tLHqrTXGVY8WlK9Zeoq5cbaq6cHHYzwQ5BI5z0 /SUuuTy6bOBkfLcKxme0q3Fo9Xge3ZN5Ljq9VfPcEzghYf+HSRQAhPIrG2t9IhjClu lN1gs5R3Sjw3Q== Date: Wed, 03 Jun 2026 17:10:57 +0000 To: mingo@redhat.com, dave.hansen@linux.intel.com, bp@alien8.de From: Maciej Wieczor-Retman Cc: hpa@zytor.com, darwi@linutronix.de, tglx@kernel.org, sohil.mehta@intel.com, andrew.cooper3@citrix.com, linux-kernel@vger.kernel.org, x86@kernel.org, m.wieczorretman@pm.me, john.ogness@linutronix.de, ludloff@gmail.com, maciej.wieczor-retman@intel.com, x86-cpuid@lists.linux.dev Subject: [PATCH v2 2/2] x86/cpuid: Update bitfields to x86-cpuid-db v3.1 Message-ID: <9653d8690ec7093c8190b12d1fa8c689c4da50fe.1780506200.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: aa9c5e31d1dc9ff1b0137b1b48981d1ea44da92a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman Update leaf_types.h to version 3.1, as generated by x86-cpuid-db. Summary of the v3.1 changes: * Fix a few typos that were found during the kernel CPUID data model review. Also include fixes found using an LLM agent review. * Rename thrd_director_nclasses to hw_feedback_nclasses as it's the name used in Intel SDM. Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.r= st Signed-off-by: Maciej Wieczor-Retman --- arch/x86/include/asm/cpuid/leaf_types.h | 62 ++++++++++++------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm= /cpuid/leaf_types.h index 5b0008e455e2..222d2d2682c8 100644 --- a/arch/x86/include/asm/cpuid/leaf_types.h +++ b/arch/x86/include/asm/cpuid/leaf_types.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: MIT */ -/* Generator: x86-cpuid-db v3.0 */ +/* Generator: x86-cpuid-db v3.1 */ =20 /* * Auto-generated file. @@ -246,7 +246,7 @@ struct leaf_0x6_0 { : 2, // Reserved energy_perf_bias : 1, // IA32_ENERGY_PERF_BIAS MSR : 4, // Reserved - thrd_director_nclasses : 8, // Number of classes, Intel thread director + hw_feedback_nclasses : 8, // Number of Intel Thread Director classes : 16; // Reserved // edx u32 perfcap_reporting : 1, // Performance capability reporting @@ -332,11 +332,11 @@ struct leaf_0x7_0 { sgx_keys : 1, // Intel SGX attestation services avx512_4vnniw : 1, // AVX-512 neural network instructions avx512_4fmaps : 1, // AVX-512 multiply accumulation single precision - fsrm : 1, // Fast short REP MOV + fsrm : 1, // Fast short REP MOVSB uintr : 1, // User interrupts : 2, // Reserved avx512_vp2intersect : 1, // VP2INTERSECT{D,Q} instructions - srdbs_ctrl : 1, // SRBDS mitigation MSR + srbds_ctrl : 1, // SRBDS mitigation MSR md_clear : 1, // VERW MD_CLEAR microcode rtm_always_abort : 1, // XBEGIN (RTM transaction) always aborts : 1, // Reserved @@ -379,7 +379,7 @@ struct leaf_0x7_1 { wrmsrns : 1, // WRMSRNS instruction (WRMSR-non-serializing) nmi_src : 1, // NMI-source reporting with FRED event data amx_fp16 : 1, // AMX-FP16: FP16 tile operations - hreset : 1, // HRESET (Thread director history reset) + hreset : 1, // HRESET (Thread director history reset) avx_ifma : 1, // Integer fused multiply add : 2, // Reserved lam : 1, // Linear address masking @@ -414,8 +414,8 @@ struct leaf_0x7_2 { u32 intel_psfd : 1, // Intel predictive store forward disable ipred_ctrl : 1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S} rrsba_ctrl : 1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U - bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S + ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U + bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S mcdt_no : 1, // MCDT mitigation not needed uclock_disable : 1, // UC-lock disable : 25; // Reserved @@ -547,7 +547,7 @@ struct leaf_0xd_1 { : 1, // Reserved xss_pasid : 1, // PASID state xss_cet_u : 1, // CET user state - xss_cet_p : 1, // CET supervisor state + xss_cet_s : 1, // CET supervisor state xss_hdc : 1, // HDC state xss_uintr : 1, // UINTR state xss_lbr : 1, // LBR state @@ -711,7 +711,7 @@ struct leaf_0x12_1 { u32 : 32; // Reserved // ecx u32 xfrm_x87 : 1, // Enclave XFRM.X87 - xfrm_sse : 1, // Enclave XFRM.SEE + xfrm_sse : 1, // Enclave XFRM.SSE xfrm_avx : 1, // Enclave XFRM.AVX xfrm_mpx_bndregs : 1, // Enclave XFRM.BNDREGS (MPX BND0-BND3 registers) xfrm_mpx_bndcsr : 1, // Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS re= gisters) @@ -771,7 +771,7 @@ struct leaf_0x14_0 { u32 topa_output : 1, // ToPA output scheme topa_multiple_entries : 1, // ToPA tables can hold multiple entries single_range_output : 1, // Single-range output - trance_transport_output : 1, // Trace Transport subsystem output + trace_transport_output : 1, // Trace Transport subsystem output : 27, // Reserved ip_payloads_lip : 1; // IP payloads have LIP values (CS base included) // edx @@ -780,7 +780,7 @@ struct leaf_0x14_0 { =20 struct leaf_0x14_1 { // eax - u32 num_address_ranges : 3, // Number of configurable Address Ranges + u32 num_address_ranges : 3, // Number of configurable address ranges : 13, // Reserved mtc_periods_bmp : 16; // MTC period encodings bitmap // ebx @@ -842,7 +842,7 @@ struct leaf_0x17_0 { // ecx u32 soc_proj_id : 32; // SoC project ID, assigned by vendor // edx - u32 soc_stepping_id : 32; // Soc project stepping ID, assigned by vendor + u32 soc_stepping_id : 32; // SoC project stepping ID, assigned by vendor }; =20 struct leaf_0x17_n { @@ -883,7 +883,7 @@ struct leaf_0x18_n { tlb_cache_level : 3, // Translation cache level (1-based) is_fully_associative : 1, // Fully-associative : 5, // Reserved - tlb_max_addressible_ids : 12, // Max number of addressable IDs - 1 + tlb_max_addressable_ids : 12, // Max number of addressable IDs - 1 : 6; // Reserved }; =20 @@ -897,7 +897,7 @@ struct leaf_0x18_n { =20 struct leaf_0x19_0 { // eax - u32 kl_cpl0_only : 1, // CPL0-only key Locker restriction + u32 kl_cpl0_only : 1, // CPL0-only key locker restriction kl_no_encrypt : 1, // No-encrypt key locker restriction kl_no_decrypt : 1, // No-decrypt key locker restriction : 29; // Reserved @@ -962,7 +962,7 @@ struct leaf_0x1c_0 { // eax u32 lbr_depth_mask : 8, // Max LBR stack depth bitmask : 22, // Reserved - lbr_deep_c_reset : 1, // LBRs maybe cleared on MWAIT C-state > C1 + lbr_deep_c_reset : 1, // LBRs may be cleared on MWAIT C-state > C1 lbr_ip_is_lip : 1; // LBR IP contain Last IP (otherwise effective IP) // ebx u32 lbr_cpl : 1, // CPL filtering @@ -1079,9 +1079,9 @@ struct leaf_0x21_0 { // ebx u32 tdx_vendorid_0 : 32; // TDX vendor ID string bytes 0 - 3 // ecx - u32 tdx_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + u32 tdx_vendorid_2 : 32; // TDX vendor ID string bytes 8 - 11 // edx - u32 tdx_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 + u32 tdx_vendorid_1 : 32; // TDX vendor ID string bytes 4 - 7 }; =20 /* @@ -1281,12 +1281,12 @@ struct leaf_0x4c780001_0 { flexpriority : 1, // Intel FlexPriority ept : 1, // Intel Extended Page Table vpid : 1, // Intel Virtual Processor ID - coherency_sfw_no : 1, // SNP cache coherency software work around not = needed + coherency_sfw_no : 1, // SNP cache coherency software workaround not n= eeded : 10, // Reserved vmmcall : 1, // Prefer VMMCALL to VMCALL xenpv : 1, // Xen paravirtual guest ept_ad : 1, // Intel Extended Page Table access-dirty bit - VMCALL : 1, // Hypervisor supports the VMCALL instruction + vmcall : 1, // Hypervisor supports the VMCALL instruction vmw_vmmcall : 1, // VMware prefers the VMMCALL instruction pvunlock : 1, // PV unlock function vcpupreempt : 1, // PV vcpu_is_preempted function @@ -1380,11 +1380,11 @@ struct leaf_0x4c780002_0 { amd_e400 : 1, // CPU is among the affected by Erratum 400 cpu_meltdown : 1, // CPU affected by meltdown; needs kernel page tabl= e isolation spectre_v1 : 1, // CPU affected by Spectre variant 1 with conditional= branches - specture_v2 : 1, // CPU affected by Spectre variant 2 with indirect b= ranches + spectre_v2 : 1, // CPU affected by Spectre variant 2 with indirect br= anches spec_store_bypass : 1, // CPU affected by speculative store bypass att= ack l1tf : 1, // CPU affected by L1 Terminal Fault mds : 1, // CPU affected by Microarchitectural data sampling - msbds_only : 1, // Microarchitectural data sampling: CPU only affecte= d by the MSDBS variant + msbds_only : 1, // Microarchitectural data sampling: CPU only affecte= d by the MSBDS variant swapgs : 1, // CPU affected by speculation through SWAPGS taa : 1, // CPU is affected by TSX Async Abort (TAA) itlb_multihit : 1, // CPU may incur MCE during certain page attribute= changes @@ -1732,7 +1732,7 @@ struct leaf_0x8000000a_0 { lbr_virt : 1, // LBR virtualization svm_lock : 1, // SVM lock nrip_save : 1, // NRIP save support on #VMEXIT - tsc_rate_msr : 1, // MSR based TSC rate control + tsc_rate_msr : 1, // MSR-based TSC rate control vmcb_clean : 1, // VMCB clean bits support flush_by_asid : 1, // Flush by ASID + Extended VMCB TLB_Control decode_assists : 1, // Decode Assists support @@ -1790,7 +1790,7 @@ struct leaf_0x8000001a_0 { // eax u32 fp_128 : 1, // Internal FP/SIMD exec data path is 128-bits wide movu_preferred : 1, // SSE: MOVU* better than MOVL*/MOVH* - fp_256 : 1, // internal FP/SSE exec data path is 256-bits wide + fp_256 : 1, // Internal FP/SSE exec data path is 256-bits wide : 29; // Reserved // ebx u32 : 32; // Reserved @@ -1836,7 +1836,7 @@ struct leaf_0x8000001b_0 { struct leaf_0x8000001c_0 { // eax u32 os_lwp_avail : 1, // OS: LWP is available to application programs - os_lpwval : 1, // OS: LWPVAL instruction + os_lwpval : 1, // OS: LWPVAL instruction os_lwp_ire : 1, // OS: Instructions Retired Event os_lwp_bre : 1, // OS: Branch Retired Event os_lwp_dme : 1, // OS: Dcache Miss Event @@ -1856,7 +1856,7 @@ struct leaf_0x8000001c_0 { lwp_data_addr : 1, // Cache miss events report data cache address lwp_latency_rnd : 3, // Cache latency rounding amount lwp_version : 7, // LWP version - lwp_buf_min_sz : 8, // LWP event ring buffer min size, 32 event recor= ds units + lwp_buf_min_sz : 8, // LWP event ring buffer min size, 32 event recor= d units : 4, // Reserved lwp_branch_predict : 1, // Branches Retired events can be filtered lwp_ip_filtering : 1, // IP filtering (IPI, IPF, BaseIP, and LimitIP @= LWPCP) @@ -1864,7 +1864,7 @@ struct leaf_0x8000001c_0 { lwp_cache_latency : 1; // Cache-related events: filter by latency // edx u32 hw_lwp_avail : 1, // HW: LWP available - hw_lpwval : 1, // HW: LWPVAL available + hw_lwpval : 1, // HW: LWPVAL available hw_lwp_ire : 1, // HW: Instructions Retired Event hw_lwp_bre : 1, // HW: Branch Retired Event hw_lwp_dme : 1, // HW: Dcache Miss Event @@ -2051,8 +2051,8 @@ struct leaf_0x80000021_0 { upper_addr_ignore : 1, // EFER MSR Upper Address Ignore auto_ibrs : 1, // EFER MSR Automatic IBRS no_smm_ctl_msr : 1, // SMM_CTL MSR not available - fsrs : 1, // Fast Short Rep STOSB - fsrc : 1, // Fast Short Rep CMPSB + fsrs : 1, // Fast Short REP STOSB + fsrc : 1, // Fast Short REP CMPSB : 1, // Reserved prefetch_ctl_msr : 1, // Prefetch control MSR : 2, // Reserved @@ -2157,11 +2157,11 @@ struct leaf_0x80860000_0 { // eax u32 max_tra_leaf : 32; // Maximum Transmeta leaf // ebx - u32 cpu_vendorid_0 : 32; // Transmeta Vendor ID string bytes 0 - 3 + u32 cpu_vendorid_0 : 32; // Transmeta vendor ID string bytes 0 - 3 // ecx - u32 cpu_vendorid_2 : 32; // Transmeta Vendor ID string bytes 8 - 11 + u32 cpu_vendorid_2 : 32; // Transmeta vendor ID string bytes 8 - 11 // edx - u32 cpu_vendorid_1 : 32; // Transmeta Vendor ID string bytes 4 - 7 + u32 cpu_vendorid_1 : 32; // Transmeta vendor ID string bytes 4 - 7 }; =20 /* --=20 2.54.0