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charset="utf-8" Document clock-controller under zynqmp-firmware in the binding example so ZynqMP DTs validate against xlnx,zynqmp-clk.yaml (Versal example already di= d). Signed-off-by: Michal Simek Acked-by: Conor Dooley --- Changes in v3: - new patch in series .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-= firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynq= mp-firmware.yaml index d50438b0fca8..680082c29f01 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwar= e.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwar= e.yaml @@ -132,6 +132,14 @@ examples: zynqmp_firmware: zynqmp-firmware { compatible =3D "xlnx,zynqmp-firmware"; #power-domain-cells =3D <1>; + clock-controller { + compatible =3D "xlnx,zynqmp-clk"; + clocks =3D <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names =3D "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells =3D <1>; + }; soc-nvmem { compatible =3D "xlnx,zynqmp-nvmem-fw"; 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charset="utf-8" The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins), but a regex character class cannot express a multi-digit decimal range. Replace the bogus character class with an explicit alternation that enumerates the two-digit decimal values 00..77. Fixes: 03d4a1004053 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-c= lk.txt to yaml") Signed-off-by: Michal Simek Acked-by: Conor Dooley --- Changes in v3: - New patch in series Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b= /Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index bef109d163a8..d843d95801b5 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -116,7 +116,7 @@ allOf: - const: pss_alt_ref_clk - const: aux_ref_clk - const: gt_crx_ref_clk - - pattern: "^mio_clk[00-77]+.*$" + - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$" - pattern: "gem[0-3]+_emio_clk.*$" - pattern: "swdt[0-1]+_ext_clk.*$" =20 --=20 2.43.0 From nobody Mon Jun 8 08:28:00 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011039.outbound.protection.outlook.com [40.93.194.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8B0B25CC74; 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charset="utf-8" The ZynqMP clock controller binding shares only #clock-cells with the Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema. Also remove "(Optional clock)" from clock description because it is visible from schema itself. Suggested-by: Rob Herring Signed-off-by: Michal Simek Acked-by: Conor Dooley --- Changes in v3: - Cover change in zynqmp-firmware.yaml - Move clock-cells to be the last in the example - Remove comment around (Optional clock) which is obvious from schema itself Changes in v2: - New patch in series - Split zynqmp-clk from versal-clk .../bindings/clock/xlnx,versal-clk.yaml | 50 +------------- .../bindings/clock/xlnx,zynqmp-clk.yaml | 68 +++++++++++++++++++ .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +- 3 files changed, 76 insertions(+), 49 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk= .yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b= /Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index d843d95801b5..12d060c39bfc 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -17,9 +17,7 @@ description: | properties: compatible: oneOf: - - enum: - - xlnx,versal-clk - - xlnx,zynqmp-clk + - const: xlnx,versal-clk - items: - enum: - xlnx,versal-net-clk @@ -32,11 +30,11 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 8 + maxItems: 3 =20 clock-names: minItems: 2 - maxItems: 8 + maxItems: 3 =20 required: - compatible @@ -87,39 +85,6 @@ allOf: - const: pl_alt_ref - const: alt_ref =20 - - if: - properties: - compatible: - contains: - enum: - - xlnx,zynqmp-clk - - then: - properties: - clocks: - minItems: 5 - items: - - description: PS reference clock - - description: reference clock for video system - - description: alternative PS reference clock - - description: auxiliary reference clock - - description: transceiver reference clock - - description: (E)MIO clock source (Optional clock) - - description: GEM emio clock (Optional clock) - - description: Watchdog external clock (Optional clock) - - clock-names: - minItems: 5 - items: - - const: pss_ref_clk - - const: video_clk - - const: pss_alt_ref_clk - - const: aux_ref_clk - - const: gt_crx_ref_clk - - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$" - - pattern: "gem[0-3]+_emio_clk.*$" - - pattern: "swdt[0-1]+_ext_clk.*$" - examples: - | firmware { @@ -134,13 +99,4 @@ examples: }; }; }; - - clock-controller { - #clock-cells =3D <1>; - compatible =3D "xlnx,zynqmp-clk"; - clocks =3D <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, - <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names =3D "pss_ref_clk", "video_clk", "pss_alt_ref_clk", - "aux_ref_clk", "gt_crx_ref_clk"; - }; ... diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b= /Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml new file mode 100644 index 000000000000..ccea3184b041 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP clock controller + +maintainers: + - Michal Simek + +description: + The clock controller is a hardware block of Xilinx ZynqMP clock tree. It + reads required input clock frequencies from the devicetree and acts as c= lock + provider for all clock consumers of PS clocks. + +properties: + compatible: + const: xlnx,zynqmp-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + minItems: 5 + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + - description: (E)MIO clock source + - description: GEM emio clock + - description: Watchdog external clock + + clock-names: + minItems: 5 + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$" + - pattern: "gem[0-3]+_emio_clk.*$" + - pattern: "swdt[0-1]+_ext_clk.*$" + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller { + compatible =3D "xlnx,zynqmp-clk"; + clocks =3D <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names =3D "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells =3D <1>; + }; +... diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-= firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynq= mp-firmware.yaml index 680082c29f01..72af37cdb103 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwar= e.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwar= e.yaml @@ -48,8 +48,7 @@ properties: const: 1 =20 clock-controller: - $ref: /schemas/clock/xlnx,versal-clk.yaml# - description: The clock controller is a hardware block of Xilinx versal + description: The clock controller is a hardware block of Xilinx SoC clock tree. It reads required input clock frequencies from the devic= etree and acts as clock provider for all clock consumers of PS clocks.list= of clock specifiers which are external input clocks to the given clock @@ -113,10 +112,14 @@ allOf: const: xlnx,zynqmp-firmware then: properties: + clock-controller: + $ref: /schemas/clock/xlnx,zynqmp-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# else: properties: + clock-controller: + $ref: /schemas/clock/xlnx,versal-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,versal-pinctrl.yaml# =20 --=20 2.43.0 From nobody Mon Jun 8 08:28:00 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012021.outbound.protection.outlook.com [52.101.53.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7979939A063; Wed, 3 Jun 2026 15:12:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.21 ARC-Seal: i=2; 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Wed, 3 Jun 2026 10:12:35 -0500 From: Michal Simek To: , , , CC: Conor Dooley , Conor Dooley , Krzysztof Kozlowski , "Michael Turquette" , Rob Herring , Shubhrajyoti Datta , Stephen Boyd , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:COMMON CLK FRAMEWORK" Subject: [PATCH v3 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation Date: Wed, 3 Jun 2026 17:12:09 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3607; i=michal.simek@amd.com; h=from:subject:message-id; bh=JY0bKLpJ6n00tX1y4bMpuomiycTyaF+CgmXmTFblIlA=; b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWQpuHge72X/sdL+V0NKrtrDRwFH2rPfGO44LHd+scVDh k5TTwadjlIWBjEOBlkxRZbpTDoOa75dWyq2PDIfZg4rE8gQBi5OAZiIXgrDP+0vfG4Ksx1qjr7Q ZZgW+ZZHa63L+tdsG0X0qqf9snm/OZORYeUMceaJj1iX5h//8yr97FXOdUd+ex35V9FoNzlvi3G HDjMA X-Developer-Key: i=michal.simek@amd.com; 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charset="utf-8" The Versal NET clock controller compatible is specified as: compatible =3D "xlnx,versal-net-clk", "xlnx,versal-clk"; with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET. Define clock-names at the top-level and use if/then only to constrain the clock count (2 for Versal, 3 for Versal NET). Add a dedicated example for the Versal NET 3-clock configuration. Fixes: 39118392d19a ("dt-bindings: Remove alt_ref from versal") Signed-off-by: Michal Simek Acked-by: Conor Dooley --- Changes in v3: - Move clock-cells to be the last property in the example - use 2 spaces for indentation in example to follow the same style which is already used - Add fixed tag Changes in v2: - Update logic without ZynqMP part in this file and have if/else only around min/maxItems .../bindings/clock/xlnx,versal-clk.yaml | 51 ++++++++----------- 1 file changed, 22 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b= /Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 12d060c39bfc..b533ffd082fd 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -30,11 +30,17 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 3 + items: + - description: reference clock + - description: alternate reference clock for programmable logic + - description: alternate reference clock =20 clock-names: minItems: 2 - maxItems: 3 + items: + - const: ref + - const: pl_alt_ref + - const: alt_ref =20 required: - compatible @@ -50,40 +56,19 @@ allOf: compatible: contains: enum: - - xlnx,versal-clk - + - xlnx,versal-net-clk then: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - + minItems: 3 clock-names: - items: - - const: ref - - const: pl_alt_ref - - - if: - properties: - compatible: - contains: - enum: - - xlnx,versal-net-clk - - then: + minItems: 3 + else: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - description: alternate reference clock - + maxItems: 2 clock-names: - items: - - const: ref - - const: pl_alt_ref - - const: alt_ref + maxItems: 2 =20 examples: - | @@ -99,4 +84,12 @@ examples: }; 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charset="utf-8" Switch Versal NET from using fixed clocks to the firmware-based clock interface (versal-net-clk.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions. Add DT macro headers for Versal NET and base Versal clocks, power domains and mandatory resets required by the clock dtsi. Signed-off-by: Michal Simek --- Changes in v3: - Remove interrupt from zynqmp-power - Versal NET is using event framework instead. No interrupt is required. - Remove unused GEM{0,1}_REF_{R,T}X macros - Update commit message - s/zynqmp/versal-net/ in subject - Update copyrights - Make all macro values lower case - Fix guarding macro names Changes in v2: - use clock- node name for fixed clocks - Reuse existing versal-net-clk.dtsi file .../arm64/boot/dts/xilinx/versal-net-clk.dtsi | 345 +++++++++++++----- arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h | 123 +++++++ .../boot/dts/xilinx/xlnx-versal-net-clk.h | 74 ++++ .../boot/dts/xilinx/xlnx-versal-net-power.h | 38 ++ .../boot/dts/xilinx/xlnx-versal-net-resets.h | 53 +++ .../arm64/boot/dts/xilinx/xlnx-versal-power.h | 55 +++ .../boot/dts/xilinx/xlnx-versal-resets.h | 106 ++++++ 7 files changed, 695 insertions(+), 99 deletions(-) create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h diff --git a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi b/arch/arm64/bo= ot/dts/xilinx/versal-net-clk.dtsi index b7a8a1a512cb..d3a27da90090 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi @@ -1,231 +1,378 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx Versal NET fixed clock + * dts file for Xilinx Versal NET with PM * - * (C) Copyright 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ =20 +#include +#include +#include "xlnx-versal-net-clk.h" +#include "xlnx-versal-net-power.h" +#include "xlnx-versal-net-resets.h" + / { - clk60: clk60 { + ref_clk: clock-33333333 { compatible =3D "fixed-clock"; + bootph-all; + clock-frequency =3D <33333333>; + clock-output-names =3D "ref_clk"; #clock-cells =3D <0>; - clock-frequency =3D <60000000>; }; =20 - clk100: clk100 { + rtc_clk: clock-32768 { compatible =3D "fixed-clock"; + bootph-all; + clock-frequency =3D <32768>; + clock-output-names =3D "rtc_clk"; #clock-cells =3D <0>; - clock-frequency =3D <100000000>; }; =20 - clk125: clk125 { - compatible =3D "fixed-clock"; + can0_clk: can0-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&versal_net_clk CAN0_REF_2X>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "can0_clk"; #clock-cells =3D <0>; - clock-frequency =3D <125000000>; }; =20 - clk150: clk150 { - compatible =3D "fixed-clock"; + can1_clk: can1-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&versal_net_clk CAN1_REF_2X>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "can1_clk"; #clock-cells =3D <0>; - clock-frequency =3D <150000000>; }; =20 - clk160: clk160 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <160000000>; + firmware { + versal_net_firmware: versal-net-firmware { + compatible =3D "xlnx,versal-net-firmware", "xlnx,versal-firmware"; + bootph-all; + method =3D "smc"; + #power-domain-cells =3D <1>; + + versal_net_reset: reset-controller { + compatible =3D "xlnx,versal-net-reset"; + #reset-cells =3D <1>; + }; + + versal_net_clk: clock-controller { + compatible =3D "xlnx,versal-net-clk", "xlnx,versal-clk"; + bootph-all; + clocks =3D <&ref_clk>, <&ref_clk>, <&ref_clk>; + clock-names =3D "ref", "pl_alt_ref", "alt_ref"; + #clock-cells =3D <1>; + }; + + versal_net_power: power-management { + compatible =3D "xlnx,zynqmp-power"; + mboxes =3D <&ipi_mailbox_pmu1 0>, + <&ipi_mailbox_pmu1 1>; + mbox-names =3D "tx", "rx"; + }; + }; }; =20 - clk200: clk200 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <200000000>; + zynqmp-ipi { + compatible =3D "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + xlnx,ipi-id =3D <2>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@eb3f0440 { + compatible =3D "xlnx,zynqmp-ipi-dest-mailbox"; + reg =3D <0 0xeb3f0440 0 0x20>, + <0 0xeb3f0460 0 0x20>, + <0 0xeb3f0280 0 0x20>, + <0 0xeb3f02a0 0 0x20>; + reg-names =3D "local_request_region", "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells =3D <1>; + xlnx,ipi-id =3D <1>; + }; }; +}; =20 - clk250: clk250 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <250000000>; - }; +&cpu0 { + clocks =3D <&versal_net_clk ACPU_0>; +}; =20 - clk300: clk300 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <300000000>; - }; +&cpu100 { + clocks =3D <&versal_net_clk ACPU_0>; +}; =20 - clk450: clk450 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <450000000>; - }; +&cpu200 { + clocks =3D <&versal_net_clk ACPU_0>; +}; =20 - clk1200: clk1200 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1200000000>; - }; +&cpu300 { + clocks =3D <&versal_net_clk ACPU_0>; +}; =20 - firmware { - versal_net_firmware: versal-net-firmware { - compatible =3D "xlnx,versal-net-firmware", "xlnx,versal-firmware"; - bootph-all; - method =3D "smc"; - }; - }; +&cpu10000 { + clocks =3D <&versal_net_clk ACPU_1>; }; =20 -&adma0 { - clocks =3D <&clk450>, <&clk450>; +&cpu10100 { + clocks =3D <&versal_net_clk ACPU_1>; }; =20 -&adma1 { - clocks =3D <&clk450>, <&clk450>; +&cpu10200 { + clocks =3D <&versal_net_clk ACPU_1>; }; =20 -&adma2 { - clocks =3D <&clk450>, <&clk450>; +&cpu10300 { + clocks =3D <&versal_net_clk ACPU_1>; }; =20 -&adma3 { - clocks =3D <&clk450>, <&clk450>; +&cpu20000 { + clocks =3D <&versal_net_clk ACPU_2>; }; =20 -&adma4 { - clocks =3D <&clk450>, <&clk450>; +&cpu20100 { + clocks =3D <&versal_net_clk ACPU_2>; }; =20 -&adma5 { - clocks =3D <&clk450>, <&clk450>; +&cpu20200 { + clocks =3D <&versal_net_clk ACPU_2>; }; =20 -&adma6 { - clocks =3D <&clk450>, <&clk450>; +&cpu20300 { + clocks =3D <&versal_net_clk ACPU_2>; }; =20 -&adma7 { - clocks =3D <&clk450>, <&clk450>; +&cpu30000 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&cpu30100 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&cpu30200 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&cpu30300 { + clocks =3D <&versal_net_clk ACPU_3>; }; =20 &can0 { - clocks =3D <&clk160>, <&clk160>; + clocks =3D <&can0_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_CAN_FD_0>; }; =20 &can1 { - clocks =3D <&clk160>, <&clk160>; + clocks =3D <&can1_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_CAN_FD_1>; }; =20 &gem0 { - clocks =3D <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; + clocks =3D <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, + <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; + power-domains =3D <&versal_net_firmware PM_DEV_GEM_0>; }; =20 &gem1 { - clocks =3D <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; + clocks =3D <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, + <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; + power-domains =3D <&versal_net_firmware PM_DEV_GEM_1>; }; =20 &gpio0 { - clocks =3D <&clk100>; + clocks =3D <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_GPIO>; }; =20 &gpio1 { - clocks =3D <&clk100>; + clocks =3D <&versal_net_clk PMC_LSBUS_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_GPIO_PMC>; }; =20 &i2c0 { - clocks =3D <&clk100>; + clocks =3D <&versal_net_clk I3C0_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_0>; }; =20 &i2c1 { - clocks =3D <&clk100>; + clocks =3D <&versal_net_clk I3C1_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_1>; }; =20 &i3c0 { - clocks =3D <&clk100>; + clocks =3D <&versal_net_clk I3C0_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_0>; }; =20 &i3c1 { - clocks =3D <&clk100>; + clocks =3D <&versal_net_clk I3C1_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_1>; }; =20 -&ospi { - clocks =3D <&clk200>; +&adma0 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_0>; }; =20 -&qspi { - clocks =3D <&clk300>, <&clk300>; +&adma1 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_1>; }; =20 -&rtc { - /* Nothing */ +&adma2 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_2>; }; =20 -&sdhci0 { - clocks =3D <&clk200>, <&clk200>, <&clk1200>; +&adma3 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_3>; }; =20 -&sdhci1 { - clocks =3D <&clk200>, <&clk200>, <&clk1200>; +&adma4 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_4>; +}; + +&adma5 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_5>; +}; + +&adma6 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_6>; +}; + +&adma7 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_7>; +}; + +&qspi { + clocks =3D <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_QSPI>; +}; + +&ospi { + clocks =3D <&versal_net_clk OSPI_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_OSPI>; +}; + +&rtc { + clocks =3D <&rtc_clk>; + clock-names =3D "rtc"; + power-domains =3D <&versal_net_firmware PM_DEV_RTC>; }; =20 &serial0 { - clocks =3D <&clk100>, <&clk100>; + clocks =3D <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_UART_0>; }; =20 &serial1 { - clocks =3D <&clk100>, <&clk100>; + clocks =3D <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_UART_1>; +}; + +&sdhci0 { + clocks =3D <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_SDIO_0>; +}; + +&sdhci1 { + clocks =3D <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_SDIO_1>; }; =20 &spi0 { - clocks =3D <&clk200>, <&clk200>; + clocks =3D <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_SPI_0>; }; =20 &spi1 { - clocks =3D <&clk200>, <&clk200>; + clocks =3D <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_SPI_1>; }; =20 &ttc0 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk TTC0>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_0>; +}; + +&ttc1 { + clocks =3D <&versal_net_clk TTC1>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_1>; +}; + +&ttc2 { + clocks =3D <&versal_net_clk TTC2>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_2>; +}; + +&ttc3 { + clocks =3D <&versal_net_clk TTC3>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_3>; }; =20 &usb0 { - clocks =3D <&clk60>, <&clk60>; + clocks =3D <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_USB_0>; + resets =3D <&versal_net_reset VERSAL_RST_USB_0>; }; =20 &dwc3_0 { - clocks =3D <&clk60>; + clocks =3D <&versal_net_clk USB0_BUS_REF>; }; =20 &usb1 { - clocks =3D <&clk60>, <&clk60>; + clocks =3D <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_USB_1>; + resets =3D <&versal_net_reset VERSAL_RST_USB_1>; }; =20 &dwc3_1 { - clocks =3D <&clk60>; + clocks =3D <&versal_net_clk USB1_BUS_REF>; }; =20 &wwdt0 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk FPD_WWDT0>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; =20 &wwdt1 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk FPD_WWDT1>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; =20 &wwdt2 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk FPD_WWDT2>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; =20 &wwdt3 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk FPD_WWDT3>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; =20 &lpd_wwdt0 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk LPD_WWDT0>; + power-domains =3D <&versal_net_firmware PM_DEV_LPD_SWDT_0>; }; =20 &lpd_wwdt1 { - clocks =3D <&clk150>; + clocks =3D <&versal_net_clk LPD_WWDT1>; + power-domains =3D <&versal_net_firmware PM_DEV_LPD_SWDT_1>; }; diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h b/arch/arm64/boot= /dts/xilinx/xlnx-versal-clk.h new file mode 100644 index 000000000000..d0c4abf78f30 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_CLK_H +#define _XLNX_VERSAL_CLK_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h b/arch/arm64/= boot/dts/xilinx/xlnx-versal-net-clk.h new file mode 100644 index 000000000000..4a6add03c173 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_CLK_H +#define _XLNX_VERSAL_NET_CLK_H + +#include "xlnx-versal-clk.h" + +#define CAN0_REF_2X 0x9e +#define CAN1_REF_2X 0xac +#define FPD_WWDT0 0xb5 +#define FPD_WWDT1 0xb6 +#define FPD_WWDT2 0xb7 +#define FPD_WWDT3 0xb8 +#define LPD_WWDT0 0xb9 +#define LPD_WWDT1 0xba +#define ACPU_0 0x98 +#define ACPU_1 0x9b +#define ACPU_2 0x9a +#define ACPU_3 0x99 +#define I3C0_REF 0x9d +#define I3C1_REF 0x9f +#define USB1_BUS_REF 0xae +#define LPD_WWDT 0xad + +/* Remove Versal specific node IDs */ +#undef APU_PLL +#undef RPU_PLL +#undef CPM_PLL +#undef APU_PRESRC +#undef APU_POSTCLK +#undef APU_PLL_OUT +#undef APLL +#undef RPU_PRESRC +#undef RPU_POSTCLK +#undef RPU_PLL_OUT +#undef RPLL +#undef CPM_PRESRC +#undef CPM_POSTCLK +#undef CPM_PLL_OUT +#undef CPLL +#undef APLL_TO_XPD +#undef RPLL_TO_XPD +#undef RCLK_PMC +#undef RCLK_LPD +#undef WDT +#undef MUXED_IRO_DIV2 +#undef MUXED_IRO_DIV4 +#undef PSM_REF +#undef CPM_CORE_REF +#undef CPM_LSBUS_REF +#undef CPM_DBG_REF +#undef CPM_AUX0_REF +#undef CPM_AUX1_REF +#undef CPU_R5 +#undef CPU_R5_CORE +#undef CPU_R5_OCM +#undef CPU_R5_OCM2 +#undef CAN0_REF +#undef CAN1_REF +#undef I2C0_REF +#undef I2C1_REF +#undef CPM_TOPSW_REF +#undef USB3_DUAL_REF +#undef MUXED_IRO +#undef PL_EXT +#undef PL_LB +#undef MIO_50_OR_51 +#undef MIO_24_OR_25 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h b/arch/arm6= 4/boot/dts/xilinx/xlnx-versal-net-power.h new file mode 100644 index 000000000000..4f73593c966b --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_POWER_H +#define _XLNX_VERSAL_NET_POWER_H + +#include "xlnx-versal-power.h" + +#define PM_DEV_USB_1 (0x182240d7U) +#define PM_DEV_FPD_SWDT_0 (0x182240dbU) +#define PM_DEV_FPD_SWDT_1 (0x182240dcU) +#define PM_DEV_FPD_SWDT_2 (0x182240ddU) +#define PM_DEV_FPD_SWDT_3 (0x182240deU) +#define PM_DEV_TCM_A_0A (0x183180cbU) +#define PM_DEV_TCM_A_0B (0x183180ccU) +#define PM_DEV_TCM_A_0C (0x183180cdU) +#define PM_DEV_RPU_A_0 (0x181100bfU) +#define PM_DEV_LPD_SWDT_0 (0x182240d9U) +#define PM_DEV_LPD_SWDT_1 (0x182240daU) + +/* Remove Versal specific node IDs */ +#undef PM_DEV_RPU0_0 +#undef PM_DEV_RPU0_1 +#undef PM_DEV_OCM_0 +#undef PM_DEV_OCM_1 +#undef PM_DEV_OCM_2 +#undef PM_DEV_OCM_3 +#undef PM_DEV_TCM_0_A +#undef PM_DEV_TCM_1_A +#undef PM_DEV_TCM_0_B +#undef PM_DEV_TCM_1_B +#undef PM_DEV_SWDT_FPD +#undef PM_DEV_AI + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h b/arch/arm= 64/boot/dts/xilinx/xlnx-versal-net-resets.h new file mode 100644 index 000000000000..edc5841df214 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_RESETS_H +#define _XLNX_VERSAL_NET_RESETS_H + +#include "xlnx-versal-resets.h" + +#define VERSAL_RST_USB_1 (0xc1040c6U) + +/* Remove Versal specific reset IDs */ +#undef VERSAL_RST_ACPU_0_POR +#undef VERSAL_RST_ACPU_1_POR +#undef VERSAL_RST_OCM2_POR +#undef VERSAL_RST_APU +#undef VERSAL_RST_ACPU_0 +#undef VERSAL_RST_ACPU_1 +#undef VERSAL_RST_ACPU_L2 +#undef VERSAL_RST_RPU_ISLAND +#undef VERSAL_RST_RPU_AMBA +#undef VERSAL_RST_R5_0 +#undef VERSAL_RST_R5_1 +#undef VERSAL_RST_OCM2_RST +#undef VERSAL_RST_I2C_PMC +#undef VERSAL_RST_I2C_0 +#undef VERSAL_RST_I2C_1 +#undef VERSAL_RST_SWDT_FPD +#undef VERSAL_RST_SWDT_LPD +#undef VERSAL_RST_USB +#undef VERSAL_RST_DPC +#undef VERSAL_RST_DBG_TRACE +#undef VERSAL_RST_DBG_TSTMP +#undef VERSAL_RST_RPU0_DBG +#undef VERSAL_RST_RPU1_DBG +#undef VERSAL_RST_HSDP +#undef VERSAL_RST_CPMDBG +#undef VERSAL_RST_PCIE_CFG +#undef VERSAL_RST_PCIE_CORE0 +#undef VERSAL_RST_PCIE_CORE1 +#undef VERSAL_RST_PCIE_DMA +#undef VERSAL_RST_L2_0 +#undef VERSAL_RST_L2_1 +#undef VERSAL_RST_ADDR_REMAP +#undef VERSAL_RST_CPI0 +#undef VERSAL_RST_CPI1 +#undef VERSAL_RST_XRAM +#undef VERSAL_RST_AIE_ARRAY +#undef VERSAL_RST_AIE_SHIM + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h b/arch/arm64/bo= ot/dts/xilinx/xlnx-versal-power.h new file mode 100644 index 000000000000..c3450675658a --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_POWER_H +#define _XLNX_VERSAL_POWER_H + +#define PM_DEV_RPU0_0 (0x18110005U) +#define PM_DEV_RPU0_1 (0x18110006U) +#define PM_DEV_OCM_0 (0x18314007U) +#define PM_DEV_OCM_1 (0x18314008U) +#define PM_DEV_OCM_2 (0x18314009U) +#define PM_DEV_OCM_3 (0x1831400aU) +#define PM_DEV_TCM_0_A (0x1831800bU) +#define PM_DEV_TCM_0_B (0x1831800cU) +#define PM_DEV_TCM_1_A (0x1831800dU) +#define PM_DEV_TCM_1_B (0x1831800eU) +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_LPD (0x18224028U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_I2C_PMC (0x1822402dU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h b/arch/arm64/b= oot/dts/xilinx/xlnx-versal-resets.h new file mode 100644 index 000000000000..fe00f4a0ba65 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_RESETS_H +#define _XLNX_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif --=20 2.43.0