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Wed, 03 Jun 2026 08:24:40 -0700 (PDT) From: Andrea della Porta To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Andrea della Porta , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Naushir Patuck , Stanimir Varbanov , mbrugger@suse.com Cc: Krzysztof Kozlowski Subject: [PATCH v4 1/3] dt-bindings: pwm: Add Raspberry Pi RP1 PWM controller Date: Wed, 3 Jun 2026 17:27:44 +0200 Message-ID: <350c2fb454951fd2c9d959f1d94802fea8fa8152.1780498640.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Naushir Patuck Add the devicetree binding documentation for the PWM controller found in the Raspberry Pi RP1 chipset. Signed-off-by: Naushir Patuck Co-developed-by: Stanimir Varbanov Signed-off-by: Stanimir Varbanov Signed-off-by: Andrea della Porta Reviewed-by: Krzysztof Kozlowski --- Referring to the first comment from: https://sashiko.dev/#/patchset/cover.1776932336.git.andrea.porta%40suse.com regarding the DT-bindings, #pwm-cells is not required here because that requirement is inherited from the referenced pwm.yaml --- .../bindings/pwm/raspberrypi,rp1-pwm.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/raspberrypi,rp1-p= wm.yaml diff --git a/Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml= b/Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml new file mode 100644 index 0000000000000..6f8461d0454f7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/raspberrypi,rp1-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raspberry Pi RP1 PWM controller + +maintainers: + - Naushir Patuck + +allOf: + - $ref: pwm.yaml# + +description: | + The PWM peripheral is a flexible waveform generator with a + variety of operational modes. It has the following features: + - four independent output channels + - 32-bit counter widths + - Seven output generation modes + - Optional per-channel output inversion + - Optional duty-cycle data FIFO with DMA support + - Optional sigma-delta noise shaping engine + Serves as a fan speed provider to other nodes for a PWM-connected + fan using shared registers (syscon). + +properties: + compatible: + const: raspberrypi,rp1-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + pwm@98000 { + compatible =3D "raspberrypi,rp1-pwm"; + reg =3D <0x98000 0x100>; + clocks =3D <&rp1_clocks 17>; + #pwm-cells =3D <3>; + }; --=20 2.35.3 From nobody Mon Jun 8 08:35:27 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32A3D3DE42D for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Naushir Patuck The Raspberry Pi RP1 southbridge features an embedded PWM controller with 4 output channels, alongside an RPM interface to read the fan speed on the Raspberry Pi 5. Add the supporting driver. Signed-off-by: Naushir Patuck Co-developed-by: Stanimir Varbanov Signed-off-by: Stanimir Varbanov Signed-off-by: Andrea della Porta --- Referring to the comments from: https://sashiko.dev/#/patchset/cover.1776932336.git.andrea.porta%40suse.com regarding the register synchronization, there is no race condition because the pwm driver is not using the PHASE register at all, while the (future) consumer driver will just read from that register. --- drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rp1.c | 422 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 432 insertions(+) create mode 100644 drivers/pwm/pwm-rp1.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6f3147518376a..c3ddc0eb4774f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -625,6 +625,15 @@ config PWM_ROCKCHIP Generic PWM framework driver for the PWM controller found on Rockchip SoCs. =20 +config PWM_RASPBERRYPI_RP1 + tristate "RP1 PWM support" + depends on MISC_RP1 || COMPILE_TEST + depends on HAS_IOMEM + select REGMAP_MMIO + select MFD_SYSCON + help + PWM framework driver for Raspberry Pi RP1 controller. + config PWM_SAMSUNG tristate "Samsung PWM support" depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025d..59f29f60f9123 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_PWM_RENESAS_RZG2L_GPT) +=3D pwm-rzg2l-gpt.o obj-$(CONFIG_PWM_RENESAS_RZ_MTU3) +=3D pwm-rz-mtu3.o obj-$(CONFIG_PWM_RENESAS_TPU) +=3D pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) +=3D pwm-rockchip.o +obj-$(CONFIG_PWM_RASPBERRYPI_RP1) +=3D pwm-rp1.o obj-$(CONFIG_PWM_SAMSUNG) +=3D pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) +=3D pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) +=3D pwm-sl28cpld.o diff --git a/drivers/pwm/pwm-rp1.c b/drivers/pwm/pwm-rp1.c new file mode 100644 index 0000000000000..052c3ae770569 --- /dev/null +++ b/drivers/pwm/pwm-rp1.c @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pwm-rp1.c + * + * Raspberry Pi RP1 PWM. + * + * Copyright =C2=A9 2026 Raspberry Pi Ltd. + * + * Author: Naushir Patuck (naush@raspberrypi.com) + * + * Based on the pwm-bcm2835 driver by: + * Bart Tanghe + * + * Datasheet: https://pip-assets.raspberrypi.com/categories/892-raspberry-= pi-5/documents/RP-008370-DS-1-rp1-peripherals.pdf?disposition=3Dinline + * + * Limitations: + * - Channels can be enabled/disabled through a global update flag, while = the + * period and duty per-channel registers are independently updatable, and + * they are latched on the end of (specific channel) period strobe. + * This means that period and duty changes might result in glitches if t= he + * period/duty is changed exactly during an end of period strobe. + * - Since the duty/period registers are freely updatable (do not depend on + * the global update flag), setting one of them close to the period end = and + * the other right afterwards results in a mixed output for that cycle b= ecause + * the write ops are not atomic. + * - The global update flag prevents mis-sampling of multi-bit bus signals= in + * the PWM clock domain. This ensures that all PWM channel settings upda= te + * on the same PWM clock cycle. Channels start in sync only if they shar= e the + * same period. + * - If both duty and period are set to 0, the output is a constant low si= gnal + * if polarity is normal or a constant high signal if polarity is invers= ed. + * - When disabled the output is driven to 0 if polarity is normal, or to 1 + * if polarity is inversed. + * - Disabling the PWM stops the output immediately, without waiting for c= urrent + * period to complete first. + * - Channels are phase-capable, but on RPi5, the firmware can use a chann= el + * phase register to report the RPM of the fan connected to that PWM + * channel. As a result, phase control will be ignored for now. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RP1_PWM_GLB_CTRL 0x000 +#define RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(chan) BIT(chan) +#define RP1_PWM_GLB_CTRL_SET_UPDATE BIT(31) + +#define RP1_PWM_CHAN_CTRL(chan) (0x014 + ((chan) * 0x10)) +#define RP1_PWM_CHAN_CTRL_POLARITY BIT(3) +#define RP1_PWM_CHAN_CTRL_FIFO_POP_MASK BIT(8) +#define RP1_PWM_CHAN_CTRL_MODE GENMASK(2, 0) +enum rp1_pwm_ctrl_mode { + RP1_PWM_CHAN_CTRL_MODE_ZERO, + RP1_PWM_CHAN_CTRL_MODE_TE_MS, + RP1_PWM_CHAN_CTRL_MODE_PC_MS, + RP1_PWM_CHAN_CTRL_MODE_PD_ENC, + RP1_PWM_CHAN_CTRL_MODE_MSB_SER, + RP1_PWM_CHAN_CTRL_MODE_PPM, + RP1_PWM_CHAN_CTRL_MODE_LE_MS, + RP1_PWM_CHAN_CTRL_MODE_LSB_SER, +}; + +#define RP1_PWM_CHAN_CTRL_DEFAULT (RP1_PWM_CHAN_CTRL_FIFO_POP_MASK + \ + FIELD_PREP(RP1_PWM_CHAN_CTRL_MODE, \ + RP1_PWM_CHAN_CTRL_MODE_TE_MS)) + +#define RP1_PWM_RANGE(chan) (0x018 + ((chan) * 0x10)) +#define RP1_PWM_PHASE(chan) (0x01C + ((chan) * 0x10)) +#define RP1_PWM_DUTY(chan) (0x020 + ((chan) * 0x10)) + +#define RP1_PWM_NUM_PWMS 4 + +struct rp1_pwm { + struct regmap *regmap; + struct clk *clk; + unsigned long clk_rate; + bool clk_enabled; +}; + +struct rp1_pwm_waveform { + u32 period_ticks; + u32 duty_ticks; + bool enabled; + bool inverted_polarity; +}; + +static const struct regmap_config rp1_pwm_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x60, +}; + +static void rp1_pwm_apply_config(struct pwm_chip *chip, struct pwm_device = *pwm) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + u32 value; + + /* update the changed registers on the next strobe to avoid glitches */ + regmap_read(rp1->regmap, RP1_PWM_GLB_CTRL, &value); + value |=3D RP1_PWM_GLB_CTRL_SET_UPDATE; + regmap_write(rp1->regmap, RP1_PWM_GLB_CTRL, value); +} + +static int rp1_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + + /* init channel to reset defaults, preserving the polarity bit */ + regmap_update_bits(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), + ~(u32)RP1_PWM_CHAN_CTRL_POLARITY, RP1_PWM_CHAN_CTRL_DEFAULT); + return 0; +} + +static int rp1_pwm_round_waveform_tohw(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_waveform *wf, + void *_wfhw) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + u64 period_ticks, duty_ticks, offset_ticks; + struct rp1_pwm_waveform *wfhw =3D _wfhw; + u64 clk_rate =3D rp1->clk_rate; + int ret =3D 0; + + if (!wf->period_length_ns) { + wfhw->enabled =3D false; + return 0; + } + + period_ticks =3D mul_u64_u64_div_u64(wf->period_length_ns, clk_rate, NSEC= _PER_SEC); + + /* + * The period is limited to U32_MAX - 1 + * to allow 100% duty cycle. + */ + if (period_ticks > U32_MAX) { + period_ticks =3D U32_MAX - 1; + } else if (!period_ticks) { + period_ticks =3D 2; + ret =3D 1; + } + + duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, clk_rate, NSEC_PER= _SEC); + duty_ticks =3D min(duty_ticks, period_ticks); + offset_ticks =3D mul_u64_u64_div_u64(wf->duty_offset_ns, clk_rate, NSEC_P= ER_SEC); + if (offset_ticks >=3D period_ticks) + offset_ticks %=3D period_ticks; + if (duty_ticks && offset_ticks && + duty_ticks + offset_ticks >=3D period_ticks) { + wfhw->duty_ticks =3D period_ticks - duty_ticks; + wfhw->inverted_polarity =3D true; + } else { + wfhw->duty_ticks =3D duty_ticks; + wfhw->inverted_polarity =3D false; + } + /* Account for the extra tick at the end of the period */ + wfhw->period_ticks =3D period_ticks - 1; + + wfhw->enabled =3D true; + + return ret; +} + +static int rp1_pwm_round_waveform_fromhw(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw, + struct pwm_waveform *wf) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + const struct rp1_pwm_waveform *wfhw =3D _wfhw; + u64 clk_rate =3D rp1->clk_rate; + u32 ticks; + + *wf =3D (struct pwm_waveform){ }; + + if (!wfhw->enabled) + return 0; + + wf->period_length_ns =3D DIV_ROUND_UP_ULL((u64)(wfhw->period_ticks + 1) *= NSEC_PER_SEC, + clk_rate); + + if (!wfhw->inverted_polarity) { + wf->duty_length_ns =3D DIV_ROUND_UP_ULL((u64)wfhw->duty_ticks * NSEC_PER= _SEC, + clk_rate); + } else { + ticks =3D wfhw->period_ticks + 1 - wfhw->duty_ticks; + wf->duty_length_ns =3D DIV_ROUND_UP_ULL((u64)ticks * NSEC_PER_SEC, clk_r= ate); + wf->duty_offset_ns =3D wf->period_length_ns - wf->duty_length_ns; + } + + return 0; +} + +static int rp1_pwm_write_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + const struct rp1_pwm_waveform *wfhw =3D _wfhw; + u32 value, ctrl; + + /* early exit if disabled */ + regmap_read(rp1->regmap, RP1_PWM_GLB_CTRL, &ctrl); + if (!wfhw->enabled) { + ctrl &=3D ~RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(pwm->hwpwm); + goto exit_disable; + } + + /* set period and duty cycle */ + regmap_write(rp1->regmap, + RP1_PWM_RANGE(pwm->hwpwm), wfhw->period_ticks); + regmap_write(rp1->regmap, + RP1_PWM_DUTY(pwm->hwpwm), wfhw->duty_ticks); + + /* set polarity */ + regmap_read(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), &value); + if (!wfhw->inverted_polarity) + value &=3D ~RP1_PWM_CHAN_CTRL_POLARITY; + else + value |=3D RP1_PWM_CHAN_CTRL_POLARITY; + regmap_write(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), value); + + /* enable the channel */ + ctrl |=3D RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(pwm->hwpwm); +exit_disable: + regmap_write(rp1->regmap, RP1_PWM_GLB_CTRL, ctrl); + + rp1_pwm_apply_config(chip, pwm); + + return 0; +} + +static int rp1_pwm_read_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + void *_wfhw) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + struct rp1_pwm_waveform *wfhw =3D _wfhw; + u32 value; + + regmap_read(rp1->regmap, RP1_PWM_GLB_CTRL, &value); + wfhw->enabled =3D !!(value & RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(pwm->hwpwm)); + + regmap_read(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), &value); + wfhw->inverted_polarity =3D !!(value & RP1_PWM_CHAN_CTRL_POLARITY); + + if (wfhw->enabled) { + regmap_read(rp1->regmap, RP1_PWM_RANGE(pwm->hwpwm), &wfhw->period_ticks); + regmap_read(rp1->regmap, RP1_PWM_DUTY(pwm->hwpwm), &wfhw->duty_ticks); + } else { + wfhw->period_ticks =3D 0; + wfhw->duty_ticks =3D 0; + } + + return 0; +} + +static const struct pwm_ops rp1_pwm_ops =3D { + .sizeof_wfhw =3D sizeof(struct rp1_pwm_waveform), + .request =3D rp1_pwm_request, + .round_waveform_tohw =3D rp1_pwm_round_waveform_tohw, + .round_waveform_fromhw =3D rp1_pwm_round_waveform_fromhw, + .read_waveform =3D rp1_pwm_read_waveform, + .write_waveform =3D rp1_pwm_write_waveform, +}; + +static int rp1_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + unsigned long clk_rate; + struct pwm_chip *chip; + void __iomem *base; + struct rp1_pwm *rp1; + int ret; + + chip =3D devm_pwmchip_alloc(dev, RP1_PWM_NUM_PWMS, sizeof(*rp1)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + rp1 =3D pwmchip_get_drvdata(chip); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + rp1->regmap =3D devm_regmap_init_mmio(dev, base, &rp1_pwm_regmap_config); + if (IS_ERR(rp1->regmap)) + return dev_err_probe(dev, PTR_ERR(rp1->regmap), "Cannot initialize regma= p\n"); + + rp1->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(rp1->clk)) + return dev_err_probe(dev, PTR_ERR(rp1->clk), "Clock not found\n"); + + ret =3D clk_prepare_enable(rp1->clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable clock\n"); + rp1->clk_enabled =3D true; + + ret =3D devm_clk_rate_exclusive_get(dev, rp1->clk); + if (ret) { + dev_err_probe(dev, ret, "Failed to get exclusive rate\n"); + goto err_disable_clk; + } + + clk_rate =3D clk_get_rate(rp1->clk); + if (!clk_rate) { + ret =3D dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n"); + goto err_disable_clk; + } + /* + * To prevent u64 overflow in period calculations: + * mul_u64_u64_div_u64(period_ns, clk_rate, NSEC_PER_SEC) + * If clk_rate > 1 GHz, the result can overflow. + */ + if (clk_rate > HZ_PER_GHZ) { + ret =3D dev_err_probe(dev, -EINVAL, "Clock rate > 1 GHz is not supported= \n"); + goto err_disable_clk; + } + rp1->clk_rate =3D clk_rate; + + chip->ops =3D &rp1_pwm_ops; + + platform_set_drvdata(pdev, chip); + + ret =3D pwmchip_add(chip); + if (ret) { + dev_err_probe(dev, ret, "Failed to register PWM chip\n"); + goto err_disable_clk; + } + + ret =3D of_syscon_register_regmap(np, rp1->regmap); + if (ret) { + dev_err_probe(dev, ret, "Failed to register syscon\n"); + goto err_disable_clk; + } + + return 0; + +err_disable_clk: + clk_disable_unprepare(rp1->clk); + + return ret; +} + +static void rp1_pwm_remove(struct platform_device *pdev) +{ + struct pwm_chip *chip =3D platform_get_drvdata(pdev); + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + + pwmchip_remove(chip); + + if (rp1->clk_enabled) { + clk_disable_unprepare(rp1->clk); + rp1->clk_enabled =3D false; + } +} + +static int rp1_pwm_suspend(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + + if (rp1->clk_enabled) { + clk_disable_unprepare(rp1->clk); + rp1->clk_enabled =3D false; + } + + return 0; +} + +static int rp1_pwm_resume(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + int ret; + + ret =3D clk_prepare_enable(rp1->clk); + if (ret) { + dev_err(dev, "Failed to enable clock on resume: %pe\n", ERR_PTR(ret)); + return ret; + } + + rp1->clk_enabled =3D true; + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rp1_pwm_pm_ops, rp1_pwm_suspend, rp1_pwm_r= esume); + +static const struct of_device_id rp1_pwm_of_match[] =3D { + { .compatible =3D "raspberrypi,rp1-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rp1_pwm_of_match); + +static struct platform_driver rp1_pwm_driver =3D { + .probe =3D rp1_pwm_probe, + .remove =3D rp1_pwm_remove, + .driver =3D { + .name =3D "rp1-pwm", + .of_match_table =3D rp1_pwm_of_match, + .pm =3D pm_ptr(&rp1_pwm_pm_ops), + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(rp1_pwm_driver); + +MODULE_DESCRIPTION("RP1 PWM driver"); +MODULE_AUTHOR("Naushir Patuck "); +MODULE_AUTHOR("Andrea della Porta "); +MODULE_LICENSE("GPL"); --=20 2.35.3 From nobody Mon Jun 8 08:35:27 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FB463DD509 for ; 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Wed, 03 Jun 2026 08:24:43 -0700 (PDT) Received: from localhost ([82.192.120.99]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b725fb1bsm63329125e9.8.2026.06.03.08.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 08:24:43 -0700 (PDT) From: Andrea della Porta To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Andrea della Porta , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Naushir Patuck , Stanimir Varbanov , mbrugger@suse.com Subject: [PATCH v4 3/3] arm64: dts: broadcom: rpi-5: Add RP1 PWM node Date: Wed, 3 Jun 2026 17:27:46 +0200 Message-ID: <3328baef11e5cf57391c2679d810922807f26a7a.1780498640.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stanimir Varbanov The RP1 chipset used on the Raspberry Pi 5 features an integrated PWM controller to drive the cooling fan. Add the corresponding DT node for this PWM controller. Signed-off-by: Stanimir Varbanov Co-developed-by: Andrea della Porta Signed-off-by: Andrea della Porta --- arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 12 ++++++++++++ arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/= boot/dts/broadcom/bcm2712-rpi-5-b.dts index 0fc57e72632ed..748be8f1ee9e2 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -64,6 +64,12 @@ phy1: ethernet-phy@1 { }; =20 &rp1_gpio { + fan_pwm_default_state: fan-pwm-default-state { + function =3D "pwm1"; + pins =3D "gpio45"; + bias-pull-down; + }; + usb_vbus_default_state: usb-vbus-default-state { function =3D "vbus1"; groups =3D "vbus1"; @@ -94,6 +100,12 @@ &rp1_i2c6 { pinctrl-names =3D "default"; }; =20 +&rp1_pwm1 { + pinctrl-0 =3D <&fan_pwm_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &rp1_usb0 { pinctrl-0 =3D <&usb_vbus_default_state>; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot= /dts/broadcom/rp1-common.dtsi index 16f5359395835..df4c2d09c8d34 100644 --- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi @@ -99,7 +99,16 @@ rp1_i2c6: i2c@40088000 { clocks =3D <&rp1_clocks RP1_CLK_SYS>; i2c-scl-rising-time-ns =3D <65>; i2c-scl-falling-time-ns =3D <100>; + status =3D "disabled"; + }; =20 + rp1_pwm1: pwm@4009c000 { + compatible =3D "raspberrypi,rp1-pwm"; + reg =3D <0x00 0x4009c000 0x0 0x100>; + clocks =3D <&rp1_clocks RP1_CLK_PWM1>; + assigned-clocks =3D <&rp1_clocks RP1_CLK_PWM1>; + assigned-clock-rates =3D <50000000>; + #pwm-cells =3D <3>; status =3D "disabled"; }; =20 --=20 2.35.3