From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF22C3033EA; Sun, 31 May 2026 19:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256786; cv=none; b=IIVW4KUrGFOaeWWDqpDrgn/B5ICsPONE1pVWQ+Xefdi//+17VypJ9m2pbDuGCp0l19k+lUkHQ1QHAHGQeWRLfluU4NPluwjfhbqawFeRH6ELVMw/IlnCNYprZ7qNizk8yPFmjlKc8gBIUT0v4q589zQKiGGE+zmBaVbx4X5hj/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256786; c=relaxed/simple; bh=wI0ISySzioJ8reBoXw3GppaJ0yTveO08/zV/9m3B9vs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Rp2iG0QWunRfzl/5SOH31MhDc0lH0kPBCEjoRveP4Y4ipVDt3Voq+irRIaZHlQa77AwFfUH88rN0+r/a+kkdUOH5jkwS4RIf6OPvvzVH2u9LukmkFDUlSth83wVey9TTysxngP0fFO8/Ed8H9FiNn+g5eAaXMVgD1DikTupfRYo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IS1o+LlO; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IS1o+LlO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256785; x=1811792785; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wI0ISySzioJ8reBoXw3GppaJ0yTveO08/zV/9m3B9vs=; b=IS1o+LlOdS9z7VWxWiYSKi5Q54MYpNhSXoX83YVXxZBkSqB1OYHB+Iqx QS4glD2cHcK1wEPzOlpYkymACsJwT0qlKhhEOdnfhL0AI9GmxUl25WQ1/ oMZwPfF9BikUOsrAHw8sxXDTJ+g8XPaJ8OiFGsV3mai4dkGiizlBl61h8 UJG8g1WPKHkEJx+xdi+5Df8TJTxs0VThzqQ9yhMaHC0p7HjANQqXmOxr1 B7HtkQLkBuIZ7Tr/Ji6n4S6EZg2oBUfBFuunUIcZ6pSj0IHW/pssaBAvN L+dBDOONzUV1X8mV6yWLzGgfhWYqGmlFPJWbr+iXdpKM07BUZUQSXAsMI A==; X-CSE-ConnectionGUID: Ddi6wL6xSBqxnsiguQPJ+w== X-CSE-MsgGUID: TmDntpawRn+MsOZ8fTaCuw== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751272" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751272" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: kQz9vE5QRq+DOwuAqMU6cw== X-CSE-MsgGUID: k1Ykt+1CSZO1KxRTK7utYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363891" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 01/15] platform/x86/intel/pmt: Add pre/post decode hooks around header parsing Date: Sun, 31 May 2026 12:46:03 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add optional pre- and post-decode callbacks to the PMT class so namespaces can perform setup and cleanup steps around header parsing. - Add pmt_pre_decode() and pmt_post_decode() to struct intel_pmt_namespace. - Update intel_pmt_dev_create() to invoke, in order: pre =E2=86=92 header_decode() =E2=86=92 post. - Keep the existing pmt_header_decode() callback unchanged. No functional changes. This adds flexibility for upcoming decoders while preserving current behavior. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/class.c | 12 ++++++++++++ drivers/platform/x86/intel/pmt/class.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index b4c9964df807..9b315334a69b 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -381,10 +381,22 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entr= y, struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); =20 + if (ns->pmt_pre_decode) { + ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); + if (ret) + return ret; + } + ret =3D ns->pmt_header_decode(entry, dev); if (ret) return ret; =20 + if (ns->pmt_post_decode) { + ret =3D ns->pmt_post_decode(intel_vsec_dev, entry); + if (ret) + return ret; + } + ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); if (ret) return ret; diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 1ae56a5baad2..ff39014b208c 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -62,6 +62,10 @@ struct intel_pmt_namespace { struct xarray *xa; int (*pmt_header_decode)(struct intel_pmt_entry *entry, struct device *dev); + int (*pmt_pre_decode)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); + int (*pmt_post_decode)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); int (*pmt_add_endpoint)(struct intel_vsec_device *ivdev, struct intel_pmt_entry *entry); }; --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC68A3264D5; Sun, 31 May 2026 19:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256788; cv=none; b=HrUoDfrNHcdHTZ4vBkAEHN7D3xrO8nTsjsvGjy8kwd+1Lp2lyw7ykRnB/cE4gNaNm1b5gGF/XpCnv6lopjZX/hVmZzYz0SHalP4Stx/+00LmazXGWeDxwNCClcyD4QeWF8ep9KxzTH4jHj377+KkM9B+1WUzV9HnMYZDWSMoooI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256788; c=relaxed/simple; bh=1P1TwYoDfNLbH+8aR7ieaMCAt4ZRzqB4ux5f50uHvnc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W06/5iYuqabwpjms5fOHgtedNSi48F7fvKQGtucT6CQRzEVjpdGbApOJaACP9Z6nEyvRl33qZv9BpxAhrB3u1e5lUw1N2OPJakM3sMS8YdguDGrJN7tErzPqTqFb/R5Pvc0P6XsAVXMaATVmuDR4SWtH1GEGqRpYGoNI8tWvV+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A7lQL2Kq; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A7lQL2Kq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256787; x=1811792787; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1P1TwYoDfNLbH+8aR7ieaMCAt4ZRzqB4ux5f50uHvnc=; b=A7lQL2Kqi6pt0ryOxc0JepCcRs1hvNhXh3RR8IyBfsIAd+0Vv3goSFpQ ED1S6CI1iuf9CKpq2SoFttg3KeDd4S8HbqzaL9EAGx5uwxtZ/G/sXBNtA AL9FH5m6syMCChtT+K5v1Xu4XDy70VZPrNebIA5bvXo9M/d8QlpyaEHSL L3moYR8Wa3GzeYqEXFf1OwDbG9C85peN+fCBbamjMzpSrK2WtvmoKulfk jckFJA9+tqMB+S1aVhJ44f/0HvaGRi16kcIUJv6i76z2oZDfuK7tj5095 u0QzFBGnqevl1hdWuW1n9TggwCepcGXyjZuitDGsa/khEFb5LS4XEA7Qj g==; X-CSE-ConnectionGUID: SseYIbiSR4W98Y17xATfBA== X-CSE-MsgGUID: oM/BRqaZQmiMDXni4kN8/Q== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751275" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751275" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: sT1SAI/MShmDF5CBuPBnug== X-CSE-MsgGUID: r227P7DqTgWXmHXT+XGbjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363892" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 02/15] platform/x86/intel/pmt/crashlog: Split init into pre-decode Date: Sun, 31 May 2026 12:46:04 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor crashlog initialization to use the PMT namespace pre-decode hook: - Add pmt_crashlog_pre_decode() to parse type/version, select the crashlog_info, initialize the control mutex, and set entry->attr_grp. - Simplify pmt_crashlog_header_decode() to only read header fields from the discovery table. - Wire the namespace with .pmt_pre_decode =3D pmt_crashlog_pre_decode. This separates structural initialization from header parsing, aligning crashlog with the PMT class pre/post decode flow. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/crashlog.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x= 86/intel/pmt/crashlog.c index b0393c9c5b4b..f936daf99e4d 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -496,11 +496,9 @@ static const struct crashlog_info *select_crashlog_inf= o(u32 type, u32 version) return &crashlog_type1_ver2; } =20 -static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, - struct device *dev) +static int pmt_crashlog_pre_decode(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) { - void __iomem *disc_table =3D entry->disc_table; - struct intel_pmt_header *header =3D &entry->header; struct crashlog_entry *crashlog; u32 version; u32 type; @@ -513,6 +511,16 @@ static int pmt_crashlog_header_decode(struct intel_pmt= _entry *entry, mutex_init(&crashlog->control_mutex); =20 crashlog->info =3D select_crashlog_info(type, version); + entry->attr_grp =3D crashlog->info->attr_grp; + + return 0; +} + +static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, + struct device *dev) +{ + void __iomem *disc_table =3D entry->disc_table; + struct intel_pmt_header *header =3D &entry->header; =20 header->access_type =3D GET_ACCESS(readl(disc_table)); header->guid =3D readl(disc_table + GUID_OFFSET); @@ -521,8 +529,6 @@ static int pmt_crashlog_header_decode(struct intel_pmt_= entry *entry, /* Size is measured in DWORDS, but accessor returns bytes */ header->size =3D GET_SIZE(readl(disc_table + SIZE_OFFSET)); =20 - entry->attr_grp =3D crashlog->info->attr_grp; - return 0; } =20 @@ -530,6 +536,7 @@ static DEFINE_XARRAY_ALLOC(crashlog_array); static struct intel_pmt_namespace pmt_crashlog_ns =3D { .name =3D "crashlog", .xa =3D &crashlog_array, + .pmt_pre_decode =3D pmt_crashlog_pre_decode, .pmt_header_decode =3D pmt_crashlog_header_decode, }; =20 --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C355933D6DD; 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X-CSE-ConnectionGUID: SXV6PGAmT+6GGlyPCmBcRw== X-CSE-MsgGUID: RSiatKzqQ9mv6O+N5U3XKA== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751278" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751278" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: ZvYzRHgFRVy1NoMh1V+YQA== X-CSE-MsgGUID: 3w9ARsOxS2mbUmS3Ve1zXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363893" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 03/15] platform/x86/intel/pmt/telemetry: Move overlap check to post-decode hook Date: Sun, 31 May 2026 12:46:05 -0700 Message-ID: <17af548cc53800f03d50dd85e9213c2a1aa9413f.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the telemetry namespace to use the new PMT class pre/post decode interface. The overlap check, which previously occurred during header decode, is now performed in the post-decode hook once header fields are populated. This preserves existing behavior while reusing the same header decode logic across PMT drivers. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 24 ++++++++++++++-------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index ff39014b208c..8a0db0ef58c1 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -37,6 +37,7 @@ struct intel_pmt_header { u32 size; u32 guid; u8 access_type; + u8 telem_type; }; =20 struct intel_pmt_entry { diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/= x86/intel/pmt/telemetry.c index bdc7c24a3678..d22f633638be 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -58,14 +58,9 @@ struct pmt_telem_priv { struct intel_pmt_entry entry[]; }; =20 -static bool pmt_telem_region_overlaps(struct intel_pmt_entry *entry, - struct device *dev) +static bool pmt_telem_region_overlaps(struct device *dev, u32 guid, u32 ty= pe) { - u32 guid =3D readl(entry->disc_table + TELEM_GUID_OFFSET); - if (intel_pmt_is_early_client_hw(dev)) { - u32 type =3D TELEM_TYPE(readl(entry->disc_table)); - if ((type =3D=3D TELEM_TYPE_PUNIT_FIXED) || (guid =3D=3D TELEM_CLIENT_FIXED_BLOCK_GUID)) return true; @@ -80,15 +75,25 @@ static int pmt_telem_header_decode(struct intel_pmt_ent= ry *entry, void __iomem *disc_table =3D entry->disc_table; struct intel_pmt_header *header =3D &entry->header; =20 - if (pmt_telem_region_overlaps(entry, dev)) - return 1; - header->access_type =3D TELEM_ACCESS(readl(disc_table)); header->guid =3D readl(disc_table + TELEM_GUID_OFFSET); header->base_offset =3D readl(disc_table + TELEM_BASE_OFFSET); =20 /* Size is measured in DWORDS, but accessor returns bytes */ header->size =3D TELEM_SIZE(readl(disc_table)); + header->telem_type =3D TELEM_TYPE(readl(entry->disc_table)); + + return 0; +} + +static int pmt_telem_post_decode(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) +{ + struct intel_pmt_header *header =3D &entry->header; + struct device *dev =3D &ivdev->auxdev.dev; + + if (pmt_telem_region_overlaps(dev, header->guid, header->telem_type)) + return 1; =20 /* * Some devices may expose non-functioning entries that are @@ -131,6 +136,7 @@ static struct intel_pmt_namespace pmt_telem_ns =3D { .name =3D "telem", .xa =3D &telem_array, .pmt_header_decode =3D pmt_telem_header_decode, + .pmt_post_decode =3D pmt_telem_post_decode, .pmt_add_endpoint =3D pmt_telem_add_endpoint, }; =20 --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D71633D4E9; Sun, 31 May 2026 19:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256789; cv=none; b=OGYkaIm21ApbOJtcTTQA+/vtZCtq+3WoqoHs58E5zKqyJYm/iZUu9xZ064c0qxcGNVedsSkjYDTkJSbpdvx9brfi7wV+CZOhkaHL459AUD1Vxgmcs3EWhC5iqckU9713WGdFGia1wqOzTLARrnXBzUCCG+K9LLWVaxiroOzyXR8= ARC-Message-Signature: i=1; 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d="scan'208";a="247363894" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 04/15] platform/x86/intel/pmt: Pass discovery index instead of resource Date: Sun, 31 May 2026 12:46:06 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change PMT class code to pass a discovery index rather than a direct struct resource when creating entries. This allows the class to identify the discovery source generically without assuming PCI BAR resources. For PCI devices, the index still resolves to a resource in the intel_vsec_device. Other discovery sources, such as ACPI, can use the same index without needing a struct resource. Signed-off-by: David E. Box --- V6 - No changes V5 - No changes V4 - No changes V3 changes: - Rebased after dropping the previous "Move header decode into common helper" patch - Adjusted the intel_pmt_populate_entry() call path to match the restored intel_pmt_dev_create() flow - Did not apply Ilpo V2 signoff due to these changes. V2 - No changes drivers/platform/x86/intel/pmt/class.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 9b315334a69b..7da8279b54f8 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -206,11 +206,12 @@ EXPORT_SYMBOL_GPL(intel_pmt_class); =20 static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, struct intel_vsec_device *ivdev, - struct resource *disc_res) + int idx) { struct pci_dev *pci_dev =3D to_pci_dev(ivdev->dev); struct device *dev =3D &ivdev->auxdev.dev; struct intel_pmt_header *header =3D &entry->header; + struct resource *disc_res; u8 bir; =20 /* @@ -235,6 +236,7 @@ static int intel_pmt_populate_entry(struct intel_pmt_en= try *entry, * For access_type LOCAL, the base address is as follows: * base address =3D end of discovery region + base offset */ + disc_res =3D &ivdev->resource[idx]; entry->base_addr =3D disc_res->end + 1 + header->base_offset; =20 /* @@ -397,7 +399,7 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry,= struct intel_pmt_namespa return ret; } =20 - ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); + ret =3D intel_pmt_populate_entry(entry, intel_vsec_dev, idx); if (ret) return ret; =20 --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735D133D4F3; Sun, 31 May 2026 19:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256794; cv=none; b=mpYBFVcbVcpIpDsr7YRvm8HKL3/kqoRHJHcexVLhQY6tZN0dVYxK4yaCULzVU9E0Ct06RwAGBIAD6HgRKXlmH5FVk+C8Rz0vzW9RiUv3pO51Noa6WoVTodm8ObSZogyEnbrQ+gutaa3V3tL0ItDRXezAarhs0+LX7UZEIgYb1iM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256794; c=relaxed/simple; bh=Z/uLTLsYf0mcbMRkea2lsYoW8eUnxTETtzjmjRqTBNE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gAw9qhgvnVlubLR1zWWxVKQbSGMKfAFDSabQCsL34yV07h8CKLoTQAFtnlABqFsKG2rNscZGxqu/I3zpuxktmyjA5rciLNjJ7Xr2WhQa+So2/nMDa9NFqWFKOSrLPGUmA1sfEAscc2Nu5nGUgPC1xqfz/SpjMr/gehlSbCEI3t8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZlwcbQ84; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZlwcbQ84" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256789; x=1811792789; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z/uLTLsYf0mcbMRkea2lsYoW8eUnxTETtzjmjRqTBNE=; b=ZlwcbQ84uvoj/TqLAa9tvO6KF2dqQJRkqQso4Q86kc+dKIgLok52PadB OnZTJd1RhWjgsCvxxDP1Qfj1FrBVKQMw9Vk4xSFqT4B86dyC0xZDtcCJs HFsJ/npBtYtXvVDI8ItpZ+g5qxSAm20sMnUWRVIXAMMXLJpvkpka1CFrq KmP5O3J9lGWsi7+fZ/GX7UdFSstGzlGqIC4QDYrXuynZBglZQD2EVZcWU IR4U04nyJx/JGEUmYae8XLTXNwUHe2LAS/x79tpAdvhS/Tti/zSFUNp0A mpgn5LwjN2zPu3UiCJS+JQnvQ2IJ7QM1SbCEJ5hb2UM9NOr6cug7mwLp6 A==; X-CSE-ConnectionGUID: MtWW/MUzTMq6biHxniSpGg== X-CSE-MsgGUID: 5Aou90kBQeWND8S4gpJGRw== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751284" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751284" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: NrjBj20oS+e7ZwJv9mt30Q== X-CSE-MsgGUID: 5Ap9tRaDRMGdeU445rki4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363895" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 05/15] platform/x86/intel/pmt: Cache the telemetry discovery header Date: Sun, 31 May 2026 12:46:07 -0700 Message-ID: <6337062b826c4169eb48389ed581a4fe6085c409.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pmt_telem_header_decode() only needs the discovery header dwords, but it currently decodes them by reading directly from entry->disc_table. Cache the discovery header in intel_pmt_entry when the device is created and have telemetry decode use the cached values instead of performing MMIO reads at decode time. The DVSEC discovery resource for a namespace is sized by its per-entry entry_size (in dwords), which can be less than the 4-dword cache (e.g. telemetry uses entry_size =3D 3, i.e. 12 bytes). Cap the memcpy_fromio() to resource_size(disc_res) so the new cache does not read past the mapped region. Any unread dwords stay zero from the zero-initialized allocation of the containing struct. This keeps the telemetry header decode path independent of how the discovery data is backed and avoids baking a direct MMIO assumption into the feature-specific decode logic. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V6 changes: - Added #include for min_t() macro used in memcpy_fromio() size calculation (Ilpo). V5 changes: - Cap memcpy_fromio() of the cached discovery header to resource_size(disc_res) so the newly introduced cache does not over-read namespaces whose DVSEC entry_size is smaller than the cache (e.g. telemetry has entry_size =3D 3, 12 bytes). V4 - No changes V3 changes: - New patch split out from PMT header-fetch rework to cache discovery header data before downstream decode/population. - Added to carry the post-v3 bug fix while preserving the original series ordering intent. drivers/platform/x86/intel/pmt/class.c | 12 ++++++++++++ drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 12 ++++++------ 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 7da8279b54f8..44a0a52014fc 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -383,6 +384,17 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry= , struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); =20 + /* + * The mapped discovery resource may be smaller than disc_header (its + * size is the namespace's DVSEC entry_size in dwords, which can be + * less than 4). Cap the copy to the actual resource size to avoid + * reading past the mapped region; any unread dwords stay zero from + * the zero-initialized allocation of the containing struct. + */ + memcpy_fromio(entry->disc_header, entry->disc_table, + min_t(size_t, sizeof(entry->disc_header), + resource_size(disc_res))); + if (ns->pmt_pre_decode) { ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); if (ret) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 8a0db0ef58c1..84202fc7920c 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -44,6 +44,7 @@ struct intel_pmt_entry { struct telem_endpoint *ep; struct pci_dev *pcidev; struct intel_pmt_header header; + u32 disc_header[4]; struct bin_attribute pmt_bin_attr; const struct attribute_group *attr_grp; struct kobject *kobj; diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/= x86/intel/pmt/telemetry.c index d22f633638be..953f35b6daec 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -72,16 +72,16 @@ static bool pmt_telem_region_overlaps(struct device *de= v, u32 guid, u32 type) static int pmt_telem_header_decode(struct intel_pmt_entry *entry, struct device *dev) { - void __iomem *disc_table =3D entry->disc_table; struct intel_pmt_header *header =3D &entry->header; + u32 *disc_header =3D entry->disc_header; =20 - header->access_type =3D TELEM_ACCESS(readl(disc_table)); - header->guid =3D readl(disc_table + TELEM_GUID_OFFSET); - header->base_offset =3D readl(disc_table + TELEM_BASE_OFFSET); + header->access_type =3D TELEM_ACCESS(disc_header[0]); + header->guid =3D disc_header[1]; + header->base_offset =3D disc_header[2]; =20 /* Size is measured in DWORDS, but accessor returns bytes */ - header->size =3D TELEM_SIZE(readl(disc_table)); - header->telem_type =3D TELEM_TYPE(readl(entry->disc_table)); + header->size =3D TELEM_SIZE(disc_header[0]); + header->telem_type =3D TELEM_TYPE(disc_header[0]); =20 return 0; } --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AEEA33DED5; Sun, 31 May 2026 19:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="80751287" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751287" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: BLAMz90RRIuhkIMkHOvaww== X-CSE-MsgGUID: ZEZOxrYTTIit6giUEWzL6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363896" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 06/15] platform/x86/intel/pmt: Unify header fetch and add ACPI source Date: Sun, 31 May 2026 12:46:08 -0700 Message-ID: <64a001eb6f3ef227163caf43dfb81c2d45a51fd1.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the PMT class to read discovery headers from either PCI MMIO or ACPI-provided entries, depending on the discovery source. The new source-aware fetch helper caches the canonical discovery header for both paths, capping PCI MMIO reads to the mapped resource size, while keeping the mapped PCI discovery table available for users such as crashlog. Split intel_pmt_populate_entry() into source-specific resolvers: - pmt_resolve_access_pci(): handles both ACCESS_LOCAL and ACCESS_BARID for PCI-backed devices and sets entry->pcidev. Same existing functionality. - pmt_resolve_access_acpi(): handles only ACCESS_BARID for ACPI-backed devices, rejecting ACCESS_LOCAL which has no valid semantics without a physical discovery resource. This maintains existing PCI behavior and makes no functional changes for PCI devices. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V6 changes: - Removed unneeded headers parameter from pmt_get_headers() (Ilpo). - Added memset() to zero-initialize disc_header before copying to avoid uninitialized data in entry reuse scenarios (Ilpo/Sashiko). V5 changes: - Bounded memcpy_fromio() to resource_size() of the mapped DVSEC entry to avoid over-reading namespaces with smaller entry_size. - Documented that entry->disc_table =3D NULL in the ACPI branch is intentional and that consumers must only be wired to INTEL_VSEC_DISC_PCI namespaces if they dereference disc_table. V4 - Replaced local raw ACPI discovery pointer type u32 (*)[4] with acpi_disc_t for consistency with exported PMC helper types. V3 - No changes V2 changes: - Replaced intermediate header-decode helper with inline ACPI path - Removed separate disc_acpi resource - Moved ACPI fetch directly into intel_pmt_dev_create drivers/platform/x86/intel/pmt/class.c | 152 +++++++++++++++++++++---- drivers/platform/x86/intel/pmt/class.h | 2 +- include/linux/intel_vsec.h | 5 +- 3 files changed, 136 insertions(+), 23 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 44a0a52014fc..75c411ad92a6 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -205,9 +205,9 @@ struct class intel_pmt_class =3D { }; EXPORT_SYMBOL_GPL(intel_pmt_class); =20 -static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, - struct intel_vsec_device *ivdev, - int idx) +static int pmt_resolve_access_pci(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev, + int idx) { struct pci_dev *pci_dev =3D to_pci_dev(ivdev->dev); struct device *dev =3D &ivdev->auxdev.dev; @@ -287,6 +287,81 @@ static int intel_pmt_populate_entry(struct intel_pmt_e= ntry *entry, } =20 entry->pcidev =3D pci_dev; + + return 0; +} + +static int pmt_resolve_access_acpi(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev) +{ + struct pci_dev *pci_dev =3D NULL; + struct device *dev =3D &ivdev->auxdev.dev; + struct intel_pmt_header *header =3D &entry->header; + u8 bir; + + if (dev_is_pci(ivdev->dev)) + pci_dev =3D to_pci_dev(ivdev->dev); + + /* + * The base offset should always be 8 byte aligned. + * + * For non-local access types the lower 3 bits of base offset + * contains the index of the base address register where the + * telemetry can be found. + */ + bir =3D GET_BIR(header->base_offset); + + switch (header->access_type) { + case ACCESS_BARID: + /* ACPI platform drivers use base_addr */ + if (ivdev->base_addr) { + entry->base_addr =3D ivdev->base_addr + + GET_ADDRESS(header->base_offset); + break; + } + + /* If base_addr is not provided, then this is an ACPI companion device */ + if (!pci_dev) { + dev_err(dev, "ACCESS_BARID requires PCI BAR resources or base_addr\n"); + return -EINVAL; + } + + entry->base_addr =3D pci_resource_start(pci_dev, bir) + + GET_ADDRESS(header->base_offset); + break; + default: + dev_err(dev, "Unsupported access type %d for ACPI based PMT\n", + header->access_type); + return -EINVAL; + } + + return 0; +} + +static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, + struct intel_vsec_device *ivdev, + int idx) +{ + struct intel_pmt_header *header =3D &entry->header; + struct device *dev =3D &ivdev->auxdev.dev; + int ret; + + switch (ivdev->src) { + case INTEL_VSEC_DISC_PCI: + ret =3D pmt_resolve_access_pci(entry, ivdev, idx); + if (ret) + return ret; + break; + case INTEL_VSEC_DISC_ACPI: + ret =3D pmt_resolve_access_acpi(entry, ivdev); + if (ret) + return ret; + break; + default: + dev_err(dev, "Unknown discovery source: %d\n", ivdev->src); + return -EINVAL; + } + entry->guid =3D header->guid; entry->size =3D header->size; entry->cb =3D ivdev->priv_data; @@ -371,29 +446,66 @@ static int intel_pmt_dev_register(struct intel_pmt_en= try *entry, return ret; } =20 +static int pmt_get_headers(struct intel_vsec_device *ivdev, int idx, + struct intel_pmt_entry *entry) +{ + struct device *dev =3D &ivdev->auxdev.dev; + size_t header_bytes =3D sizeof(entry->disc_header); + + switch (ivdev->src) { + case INTEL_VSEC_DISC_PCI: { + struct resource *disc_res =3D &ivdev->resource[idx]; + void __iomem *disc_table; + + disc_table =3D devm_ioremap_resource(dev, disc_res); + if (IS_ERR(disc_table)) + return PTR_ERR(disc_table); + + /* + * The mapped resource is sized by the namespace's DVSEC + * entry_size (in dwords), which can be less than the default + * size (e.g. telemetry uses entry_size =3D 3, 12 bytes). Cap the + * copy to resource_size() to avoid reading past the mapped + * region. + */ + memset(entry->disc_header, 0, header_bytes); + memcpy_fromio(entry->disc_header, disc_table, + min_t(size_t, header_bytes, resource_size(disc_res))); + + /* Used by crashlog driver */ + entry->disc_table =3D disc_table; + + return 0; + } + case INTEL_VSEC_DISC_ACPI: { + memcpy(entry->disc_header, &ivdev->acpi_disc[idx][0], header_bytes); + /* + * No MMIO mapping exists on the ACPI source path; the cached + * headers are the only view of the discovery record. Consumers + * that dereference disc_table (e.g. crashlog) must therefore + * only be wired to namespaces backed by INTEL_VSEC_DISC_PCI. + */ + entry->disc_table =3D NULL; + + return 0; + } + default: + dev_err(dev, "Unknown discovery source type: %d\n", ivdev->src); + break; + } + + return -EINVAL; +} + int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_n= amespace *ns, struct intel_vsec_device *intel_vsec_dev, int idx) { struct device *dev =3D &intel_vsec_dev->auxdev.dev; - struct resource *disc_res; int ret; =20 - disc_res =3D &intel_vsec_dev->resource[idx]; - - entry->disc_table =3D devm_ioremap_resource(dev, disc_res); - if (IS_ERR(entry->disc_table)) - return PTR_ERR(entry->disc_table); - - /* - * The mapped discovery resource may be smaller than disc_header (its - * size is the namespace's DVSEC entry_size in dwords, which can be - * less than 4). Cap the copy to the actual resource size to avoid - * reading past the mapped region; any unread dwords stay zero from - * the zero-initialized allocation of the containing struct. - */ - memcpy_fromio(entry->disc_header, entry->disc_table, - min_t(size_t, sizeof(entry->disc_header), - resource_size(disc_res))); + ret =3D pmt_get_headers(intel_vsec_dev, idx, entry); + if (ret) + return ret; =20 if (ns->pmt_pre_decode) { ret =3D ns->pmt_pre_decode(intel_vsec_dev, entry); diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/= intel/pmt/class.h index 84202fc7920c..a0ece4fc3837 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -44,7 +44,7 @@ struct intel_pmt_entry { struct telem_endpoint *ep; struct pci_dev *pcidev; struct intel_pmt_header header; - u32 disc_header[4]; + u32 disc_header[PMT_DISC_DWORDS]; struct bin_attribute pmt_bin_attr; const struct attribute_group *attr_grp; struct kobject *kobj; diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 07ea563f524e..843cda8f8644 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -28,6 +28,7 @@ #define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) #define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) #define TABLE_OFFSET_SHIFT 3 +#define PMT_DISC_DWORDS 4 =20 struct device; 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d="scan'208";a="80751290" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: AhGNfwkuQBW7GGy6dtNnhg== X-CSE-MsgGUID: iCpUf43DT4e1EWnMbvsUUg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363897" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 07/15] platform/x86/intel/pmc: Add PMC SSRAM Kconfig description Date: Sun, 31 May 2026 12:46:09 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a proper description for the intel_pmc_ssram driver. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/= intel/pmc/Kconfig index c6ef0bcf76af..e9012b703918 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -28,3 +28,14 @@ config INTEL_PMC_CORE =20 config INTEL_PMC_SSRAM_TELEMETRY tristate + help + This driver discovers PMC SSRAM telemetry regions through the PMC's + MMIO interface (PCI) or ACPI _DSD properties and registers them with + the Intel VSEC framework as Intel PMT telemetry devices. + + It probes the PMC SSRAM device, extracts DVSEC information from MMIO, + reads device IDs and base addresses for multiple PMCs (main, IOE, PCH), + and exposes the discovered telemetry through Intel PMT interfaces + (including sysfs). + + This option is selected by INTEL_PMC_CORE. --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6750832B136; Sun, 31 May 2026 19:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256807; cv=none; b=ND/rk2laACxOiY2YIgW0+vlLu2t530Rq1Vl3KXOHxsRTtPiyHW9nsQCER6nGxJtUJeHs6MnMxn4yz/Ss4V22B5mrMoQ762Gi0oomSo5B+hLE9TSA1ZdSdy+Qmxe2kC443QvGWhreSmvZRs874PoSi8yAnferndqpC13f1rZxRxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256807; c=relaxed/simple; bh=OR4WrqOTElYd9mBdkRUEctZHYvo38ATpLo6sCT6uG3Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gcHRttTmM3IRDS1Yc0HjToEx0+ritCDcwdLApEkDHZmSJsaBhzpVdP6qoljKBpNmPvSUGznm4WhYGafIQw1hUCw0yPSfo7jjlHDCNnc/37y3V+NDpT8hBbhA5Y4zMBGns18ZQa0lxKQvjiOp2Zhm54E7EcBOZ4q6e/sEJS8bxl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WQbSQ9/6; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WQbSQ9/6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256795; x=1811792795; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OR4WrqOTElYd9mBdkRUEctZHYvo38ATpLo6sCT6uG3Q=; b=WQbSQ9/6YIzAVsTpbLmwqFJUyDbcfdwjkA7Kzpw2f3dkXpf2pj2r0kuV KVGABHh2Mt7xuUaJJCT660tZ+eQfl+2FlLTSjhVv1nxmSjSwya1a8ISn1 GgsRt2igvZEicCMxueGUiflVHJqwSHG+SetwPTKykjtbD3h9ckqy0z1AA zZreAewjMWF7Hivqxnj70n5uq0LASZtG+uwL+TzrERxYK9YeEiMeMU/BK 1xAn+bT3qpUNrdgaOxMgywCFboJ1zWiEJP90K3tOvUd2zd4dINHWGVMsp zhMCGcPQEdDnBu/MDOgt6Y+oHHDhD5wdHyptDt+bWpy69Z/XyOQjhgPge g==; X-CSE-ConnectionGUID: Hx8yWVJHQrGSTGEtweG0WQ== X-CSE-MsgGUID: 16+iCFjOSI6g0kTH1T2xKQ== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751294" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751294" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: LHtBJAdcTh6oJu8LJvNADQ== X-CSE-MsgGUID: q2sepDRgT+26soL++wpOlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363898" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 08/15] platform/x86/intel/pmc: Add ACPI PWRM telemetry driver for Nova Lake S Date: Sun, 31 May 2026 12:46:10 -0700 Message-ID: <465ceee2988ee37b0f13de10e84aedb310e6ae56.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an ACPI-based PMC PWRM telemetry driver for Nova Lake S. The driver locates PMT discovery data in _DSD under the Intel VSEC UUID, parses it, and registers telemetry regions with the PMT/VSEC framework so PMC telemetry is exposed via existing PMT interfaces. Export pmc_parse_telem_dsd() and pmc_find_telem_guid() to support ACPI discovery in other PMC drivers (e.g., ssram_telemetry) without duplicating ACPI parsing logic. Also export acpi_disc_t typedef from core.h for callers to properly declare discovery table arrays. Selected by INTEL_PMC_CORE. Existing PCI functionality is preserved. Assisted-by: GitHub-Copilot:claude-opus-4.7 Signed-off-by: David E. Box --- V6 - No changes V5 changes: - Added #include for U16_MAX (Ilpo). - Split acpi_handle declaration from ACPI_HANDLE() assignment and placed the assignment immediately before the !handle check (Ilpo). - Reordered local variables in pmc_pwrm_acpi_probe() in reverse-xmas-tree order (Ilpo). V4 changes: - These changes were supposed to be in V3 - Updated pmc_parse_telem_dsd() in pwrm_telemetry.c to use acpi_disc_t in the function return type for consistency with the exported typedef - In pmc_parse_telem_dsd(), change acpi_disc declaration to happen at the allocation site as specified by cleanup.h - Style, readability and cleanup-path refinement based on review feedback V2 changes: - Added explicit include for guid_t type availability in core.h - Added explicit include in pwrm_telemetry.c for GENMASK() - Added and converted goto based cleanup to __free() attributes per Ilpo's feedback - Combined u64 hdr0 and u64 hdr1 into single declaration - Converted pmc_parse_telem_dsd() to return acpi_disc directly with ERR_PTR() for failures - Added braces around _DSD evaluation failure path drivers/platform/x86/intel/pmc/Kconfig | 14 ++ drivers/platform/x86/intel/pmc/Makefile | 2 + drivers/platform/x86/intel/pmc/core.h | 16 ++ .../platform/x86/intel/pmc/pwrm_telemetry.c | 216 ++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 drivers/platform/x86/intel/pmc/pwrm_telemetry.c diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/= intel/pmc/Kconfig index e9012b703918..561d46634ab2 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -9,6 +9,7 @@ config INTEL_PMC_CORE depends on ACPI depends on INTEL_PMT_TELEMETRY select INTEL_PMC_SSRAM_TELEMETRY + select INTEL_PMC_PWRM_TELEMETRY help The Intel Platform Controller Hub for Intel Core SoCs provides access to Power Management Controller registers via various interfaces. This @@ -39,3 +40,16 @@ config INTEL_PMC_SSRAM_TELEMETRY (including sysfs). =20 This option is selected by INTEL_PMC_CORE. + +config INTEL_PMC_PWRM_TELEMETRY + tristate + help + This driver discovers PMC PWRM telemetry regions described in ACPI + _DSD and registers them with the Intel VSEC framework as Intel PMT + telemetry devices. + + It validates the ACPI discovery data and publishes the discovered + regions so they can be accessed through the Intel PMT telemetry + interfaces (including sysfs). + + This option is selected by INTEL_PMC_CORE. diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86= /intel/pmc/Makefile index 23853e867c91..5b595176f812 100644 --- a/drivers/platform/x86/intel/pmc/Makefile +++ b/drivers/platform/x86/intel/pmc/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_INTEL_PMC_CORE) +=3D intel_pmc_core_pltdrv.o # Intel PMC SSRAM driver intel_pmc_ssram_telemetry-y +=3D ssram_telemetry.o obj-$(CONFIG_INTEL_PMC_SSRAM_TELEMETRY) +=3D intel_pmc_ssram_telemetry.o +intel_pmc_pwrm_telemetry-y +=3D pwrm_telemetry.o +obj-$(CONFIG_INTEL_PMC_PWRM_TELEMETRY) +=3D intel_pmc_pwrm_telemetry.o diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 55cf567febe4..b4c7399f8369 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -14,10 +14,15 @@ =20 #include #include +#include +#include #include +#include =20 struct telem_endpoint; =20 +DEFINE_FREE(pmc_acpi_free, void *, if (_T) ACPI_FREE(_T)) + #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) =20 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 @@ -622,6 +627,8 @@ int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcdev= , struct pmc *pmc, extern const struct file_operations pmc_core_substate_req_regs_fops; extern const struct file_operations pmc_core_substate_blk_req_fops; =20 +extern const guid_t intel_vsec_guid; + #define pmc_for_each_mode(mode, pmc) \ for (unsigned int __i =3D 0, __cond; \ __cond =3D __i < (pmc)->num_lpm_modes, \ @@ -643,4 +650,13 @@ static const struct file_operations __name ## _fops = =3D { \ .release =3D single_release, \ } =20 +struct intel_vsec_header; +union acpi_object; + +/* Avoid checkpatch warning */ +typedef u32 (*acpi_disc_t)[PMT_DISC_DWORDS]; + +acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj, + struct intel_vsec_header *header); +union acpi_object *pmc_find_telem_guid(union acpi_object *dsd); #endif /* PMC_CORE_H */ diff --git a/drivers/platform/x86/intel/pmc/pwrm_telemetry.c b/drivers/plat= form/x86/intel/pmc/pwrm_telemetry.c new file mode 100644 index 000000000000..70fdc79b48a2 --- /dev/null +++ b/drivers/platform/x86/intel/pmc/pwrm_telemetry.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PMC PWRM ACPI driver + * + * Copyright (C) 2025, Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" + +#define ENTRY_LEN 5 + +/* DWORD2 */ +#define DVSEC_ID_MASK GENMASK(15, 0) +#define NUM_ENTRIES_MASK GENMASK(23, 16) +#define ENTRY_SIZE_MASK GENMASK(31, 24) + +/* DWORD3 */ +#define TBIR_MASK GENMASK(2, 0) +#define DISC_TBL_OFF_MASK GENMASK(31, 3) + +const guid_t intel_vsec_guid =3D + GUID_INIT(0x294903fb, 0x634d, 0x4fc7, 0xaf, 0x1f, 0x0f, 0xb9, + 0x56, 0xb0, 0x4f, 0xc1); + +static bool is_valid_entry(union acpi_object *pkg) +{ + int i; + + if (!pkg || pkg->type !=3D ACPI_TYPE_PACKAGE || pkg->package.count !=3D E= NTRY_LEN) + return false; + + if (pkg->package.elements[0].type !=3D ACPI_TYPE_STRING) + return false; + + for (i =3D 1; i < ENTRY_LEN; i++) + if (pkg->package.elements[i].type !=3D ACPI_TYPE_INTEGER) + return false; + + return true; +} + +acpi_disc_t pmc_parse_telem_dsd(union acpi_object *obj, + struct intel_vsec_header *header) +{ + union acpi_object *vsec_pkg; + union acpi_object *disc_pkg; + u64 hdr0, hdr1; + int num_regions; + int i; + + if (!header) + return ERR_PTR(-EINVAL); + + if (!obj || obj->type !=3D ACPI_TYPE_PACKAGE || obj->package.count !=3D 2) + return ERR_PTR(-EINVAL); + + /* First Package is DVSEC info */ + vsec_pkg =3D &obj->package.elements[0]; + if (!is_valid_entry(vsec_pkg)) + return ERR_PTR(-EINVAL); + + hdr0 =3D vsec_pkg->package.elements[3].integer.value; + hdr1 =3D vsec_pkg->package.elements[4].integer.value; + + header->id =3D FIELD_GET(DVSEC_ID_MASK, hdr0); + header->num_entries =3D FIELD_GET(NUM_ENTRIES_MASK, hdr0); + header->entry_size =3D FIELD_GET(ENTRY_SIZE_MASK, hdr0); + header->tbir =3D FIELD_GET(TBIR_MASK, hdr1); + header->offset =3D FIELD_GET(DISC_TBL_OFF_MASK, hdr1); + + /* Second Package contains the discovery tables */ + disc_pkg =3D &obj->package.elements[1]; + if (disc_pkg->type !=3D ACPI_TYPE_PACKAGE || disc_pkg->package.count < 1) + return ERR_PTR(-EINVAL); + + num_regions =3D disc_pkg->package.count; + if (header->num_entries !=3D num_regions) + return ERR_PTR(-EINVAL); + + acpi_disc_t disc __free(kfree) =3D kmalloc_array(num_regions, sizeof(*dis= c), + GFP_KERNEL); + if (!disc) + return ERR_PTR(-ENOMEM); + + for (i =3D 0; i < num_regions; i++) { + union acpi_object *pkg; + u64 value; + int j; + + pkg =3D &disc_pkg->package.elements[i]; + if (!is_valid_entry(pkg)) + return ERR_PTR(-EINVAL); + + /* Element 0 is a descriptive string; DWORD values start at index 1. */ + for (j =3D 1; j < ENTRY_LEN; j++) { + value =3D pkg->package.elements[j].integer.value; + if (value > U32_MAX) + return ERR_PTR(-ERANGE); + + disc[i][j - 1] =3D value; + } + } + + return no_free_ptr(disc); +} +EXPORT_SYMBOL_NS_GPL(pmc_parse_telem_dsd, "INTEL_PMC_CORE"); + +union acpi_object *pmc_find_telem_guid(union acpi_object *dsd) +{ + int i; + + if (!dsd || dsd->type !=3D ACPI_TYPE_PACKAGE) + return NULL; + + for (i =3D 0; i + 1 < dsd->package.count; i +=3D 2) { + union acpi_object *uuid_obj, *data_obj; + guid_t uuid; + + uuid_obj =3D &dsd->package.elements[i]; + data_obj =3D &dsd->package.elements[i + 1]; + + if (uuid_obj->type !=3D ACPI_TYPE_BUFFER || + uuid_obj->buffer.length !=3D 16) + continue; + + memcpy(&uuid, uuid_obj->buffer.pointer, 16); + if (guid_equal(&uuid, &intel_vsec_guid)) + return data_obj; + } + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(pmc_find_telem_guid, "INTEL_PMC_CORE"); + +static int pmc_pwrm_acpi_probe(struct platform_device *pdev) +{ + struct intel_vsec_header header; + struct intel_vsec_header *headers[2] =3D { &header, NULL }; + struct acpi_buffer buf =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct intel_vsec_platform_info info =3D { }; + struct device *dev =3D &pdev->dev; + union acpi_object *dsd; + struct resource *res; + acpi_handle handle; + acpi_status status; + + handle =3D ACPI_HANDLE(&pdev->dev); + if (!handle) + return -ENODEV; + + status =3D acpi_evaluate_object(handle, "_DSD", NULL, &buf); + if (ACPI_FAILURE(status)) { + return dev_err_probe(dev, -ENODEV, "Could not evaluate _DSD: %s\n", + acpi_format_exception(status)); + } + + void *dsd_buf __free(pmc_acpi_free) =3D buf.pointer; + + dsd =3D pmc_find_telem_guid(dsd_buf); + if (!dsd) + return -ENODEV; + + acpi_disc_t acpi_disc __free(kfree) =3D pmc_parse_telem_dsd(dsd, &header); + if (IS_ERR(acpi_disc)) + return PTR_ERR(acpi_disc); + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, header.tbir); + if (!res) + return -EINVAL; + + info.headers =3D headers; + info.caps =3D VSEC_CAP_TELEMETRY; + info.acpi_disc =3D acpi_disc; + info.src =3D INTEL_VSEC_DISC_ACPI; + info.base_addr =3D res->start; + + return intel_vsec_register(&pdev->dev, &info); +} + +static const struct acpi_device_id pmc_pwrm_acpi_ids[] =3D { + { "INTC1122", 0 }, /* Nova Lake */ + { "INTC1129", 0 }, /* Nova Lake */ + { } +}; +MODULE_DEVICE_TABLE(acpi, pmc_pwrm_acpi_ids); + +static struct platform_driver pmc_pwrm_acpi_driver =3D { + .probe =3D pmc_pwrm_acpi_probe, + .driver =3D { + .name =3D "intel_pmc_pwrm_acpi", + .acpi_match_table =3D ACPI_PTR(pmc_pwrm_acpi_ids), + }, +}; +module_platform_driver(pmc_pwrm_acpi_driver); + +MODULE_AUTHOR("David E. Box "); +MODULE_DESCRIPTION("Intel PMC PWRM ACPI driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("INTEL_VSEC"); --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C9DD33D4E9; Sun, 31 May 2026 19:46:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256808; cv=none; b=tFrGRpncT9nzGA/zDxxjLtVz20tXwrkNOL3odLUAdvLhE6OZ07HKohZaWOhQpsDmWo9++HYYIACiK7tJ0ufKHc1BqOpmriUsoGoyASi+j3l6b74eNj+2BtradDv13cvwRDziPj33jazZrIB2NFJNqiRKTWMtag6Rmwp3HXV4i6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256808; c=relaxed/simple; bh=IE1sSmfcIxO9481gahp4PuqraUK7jxPb3qtDfuWSWOk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fAAwf3BWgMVB5DrxLZ7m/G9PoucslqMTZhKPv8ql/i/3Pr2DHdGSxukbbAvLUY4aU+0dd3ElAyZGouqcnwpVAYwhc4Xm5Bn16PmSyR3YiV1Mb1uo1NJoIk2/VuO/XdV3lOMtzaYY0XiJfV/gVeQQEPfmCkXLww+hKVaPeQuBcvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eqbsg7QN; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eqbsg7QN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256796; x=1811792796; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IE1sSmfcIxO9481gahp4PuqraUK7jxPb3qtDfuWSWOk=; b=eqbsg7QNXfPoNNLGF3QYXFXPkHpix+g5AcazxbbPuBTXbZ4SwTlaDSdq PpFk3xH43vVMQGiekVvWnmp9pl/pxKATz5YowE4HGsmVQffQm+pNHGEua 3+bjgeKJoj/zYremK4VLFonUqEFW4PPvND5QSsfzSH5PXDFPN7kgFm0gq qYYGh1ymsyZM1RtzjHsxkiavmtzAuRgeBz0a/r4c5a8/eDQqvqo3sS8E7 ix1BIEbKdouY80d24FUPcqiR72byGumjIOc0zs+UsRQyPYyNlxY98aBXX xCSsicXPRQLVAqt/z0Eqsa1dlkoW/D6hqz9jHhE8dWqt6yIKFZfo9U4yZ w==; X-CSE-ConnectionGUID: cDcxl2IsQHCCH9w3Xc6a8w== X-CSE-MsgGUID: lUJCGRxORTmyQXmpGrPAzQ== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751297" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751297" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: V6aNpT0JTVaEd/SWzQY4Yg== X-CSE-MsgGUID: KnsUSj4nQp+kIPs6e5DLLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363899" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 09/15] platform/x86/intel/pmc/ssram: Rename probe and PCI ID table for consistency Date: Sun, 31 May 2026 12:46:11 -0700 Message-ID: <75a186c976dce5800ed1905414af6ad6c793de33.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename intel_pmc_ssram_telemetry_probe() to pmc_ssram_telemetry_probe() and intel_pmc_ssram_telemetry_pci_ids[] to pmc_ssram_telemetry_pci_ids[], updating the MODULE_DEVICE_TABLE() and pci_driver wiring accordingly. This aligns the symbol names with the driver filename and module name, reduces redundant intel_ prefixes, and improves readability. No functional behavior changes are intended. Reviewed-by: Ilpo J=C3=A4rvinen Signed-off-by: David E. Box --- V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/ssram_telemetry.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 6f6e83e70fc5..1deb4d71da3f 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -149,7 +149,7 @@ int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_i= dx, } EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 -static int intel_pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const s= truct pci_device_id *id) +static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { int ret; =20 @@ -183,7 +183,7 @@ static int intel_pmc_ssram_telemetry_probe(struct pci_d= ev *pcidev, const struct return ret; } =20 -static const struct pci_device_id intel_pmc_ssram_telemetry_pci_ids[] =3D { +static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, @@ -193,14 +193,14 @@ static const struct pci_device_id intel_pmc_ssram_tel= emetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN) }, { } }; -MODULE_DEVICE_TABLE(pci, intel_pmc_ssram_telemetry_pci_ids); +MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids); =20 -static struct pci_driver intel_pmc_ssram_telemetry_driver =3D { +static struct pci_driver pmc_ssram_telemetry_driver =3D { .name =3D "intel_pmc_ssram_telemetry", - .id_table =3D intel_pmc_ssram_telemetry_pci_ids, - .probe =3D intel_pmc_ssram_telemetry_probe, + .id_table =3D pmc_ssram_telemetry_pci_ids, + .probe =3D pmc_ssram_telemetry_probe, }; -module_pci_driver(intel_pmc_ssram_telemetry_driver); +module_pci_driver(pmc_ssram_telemetry_driver); =20 MODULE_IMPORT_NS("INTEL_VSEC"); MODULE_AUTHOR("Xi Pardee "); --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE16A32B12B; Sun, 31 May 2026 19:46:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="80751300" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751300" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: aQu2Hu40RBKpOI4GeVIShA== X-CSE-MsgGUID: Z+QH4sLYR5OjbtZZxt940A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363900" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 10/15] platform/x86/intel/pmc/ssram: Add PCI platform data Date: Sun, 31 May 2026 12:46:12 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add per-device platform data for SSRAM telemetry PCI IDs and route probe through a method selector driven by id->driver_data. This is a preparatory refactor for follow-on discovery methods while preserving current behavior: all supported IDs continue to use the PCI initialization path. Signed-off-by: David E. Box --- V6 changes: - Reordered from v5 patch 12 to maintain logical flow before probe state refactoring. V5 - No changes V4 - No changes V3 - No changes V2 changes: - Added missing include for dev_dbg() usage in probe .../platform/x86/intel/pmc/ssram_telemetry.c | 71 +++++++++++++++---- 1 file changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 1deb4d71da3f..3d1f5a17903b 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -24,6 +25,18 @@ =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 +enum resource_method { + RES_METHOD_PCI, +}; + +struct ssram_type { + enum resource_method method; +}; + +static const struct ssram_type pci_main =3D { + .method =3D RES_METHOD_PCI, +}; + static struct pmc_ssram_telemetry *pmc_ssram_telems; static bool device_probed; =20 @@ -69,7 +82,7 @@ static inline u64 get_base(void __iomem *addr, u32 offset) } =20 static int -pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, unsigned int pmc_idx, = u32 offset) +pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; @@ -109,6 +122,20 @@ pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, un= signed int pmc_idx, u32 of return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); } =20 +static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev) +{ + int ret; + + ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_MAIN, 0); + if (ret) + return ret; + + pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); + pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + + return ret; +} + /** * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr info= rmation * @pmc_idx: Index of the PMC @@ -151,6 +178,8 @@ EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { + const struct ssram_type *ssram_type; + enum resource_method method; int ret; =20 pmc_ssram_telems =3D devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems)= * MAX_NUM_PMC, @@ -160,18 +189,25 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de goto probe_finish; } =20 + ssram_type =3D (const struct ssram_type *)id->driver_data; + if (!ssram_type) { + dev_dbg(&pcidev->dev, "missing driver data\n"); + ret =3D -EINVAL; + goto probe_finish; + } + + method =3D ssram_type->method; + ret =3D pcim_enable_device(pcidev); if (ret) { dev_dbg(&pcidev->dev, "failed to enable PMC SSRAM device\n"); goto probe_finish; } =20 - ret =3D pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_MAIN, 0); - if (ret) - goto probe_finish; - - pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); - pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + if (method =3D=3D RES_METHOD_PCI) + ret =3D pmc_ssram_telemetry_pci_init(pcidev); + else + ret =3D -EINVAL; =20 probe_finish: /* @@ -184,13 +220,20 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de } =20 static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP), + .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN), + .driver_data =3D (kernel_ulong_t)&pci_main }, { } }; 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X-CSE-ConnectionGUID: 9vzfioO7TdCibSMubFnpjQ== X-CSE-MsgGUID: 88gnJBiAQDuorE8B9uSLNA== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751305" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751305" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: N13RyABPSDC/IREK9fB0lw== X-CSE-MsgGUID: BhfX9XYESnWWr17gEM7VMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363901" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 11/15] platform/x86/intel/pmc/ssram: Refactor DEVID/PWRMBASE extraction into helper Date: Sun, 31 May 2026 12:46:13 -0700 Message-ID: <7eba1a0595ebce6266bfa70e477597790313a29f.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move DEVID/PWRMBASE extraction into pmc_ssram_get_devid_pwrmbase(). This is a preparatory refactor to place functionality in a common helper for reuse by a subsequent patch. Additionally add missing bits.h include and define SSRAM_BASE_ADDR_MASK for the address extraction mask. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V6 - No changes V5 - No changes V4 - No changes V3 - No changes V2 changes: - Added missing include for GENMASK_ULL() used in get_base= () - Defined SSRAM_BASE_ADDR_MASK macro to replace magic mask constant GENMASK_ULL(63, 3) .../platform/x86/intel/pmc/ssram_telemetry.c | 33 ++++++++++++------- 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 3d1f5a17903b..e7ddd1788132 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -22,6 +23,7 @@ #define SSRAM_PCH_OFFSET 0x60 #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 +#define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3) =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 @@ -40,6 +42,23 @@ static const struct ssram_type pci_main =3D { static struct pmc_ssram_telemetry *pmc_ssram_telems; static bool device_probed; =20 +static inline u64 get_base(void __iomem *addr, u32 offset) +{ + return lo_hi_readq(addr + offset) & SSRAM_BASE_ADDR_MASK; +} + +static void pmc_ssram_get_devid_pwrmbase(void __iomem *ssram, unsigned int= pmc_idx) +{ + u64 pwrm_base; + u16 devid; + + pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); + devid =3D readw(ssram + SSRAM_DEVID_OFFSET); + + pmc_ssram_telems[pmc_idx].devid =3D devid; + pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; +} + static int pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 ssram_base, void _= _iomem *ssram) { @@ -76,18 +95,12 @@ pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64= ssram_base, void __iomem return intel_vsec_register(&pcidev->dev, &info); } =20 -static inline u64 get_base(void __iomem *addr, u32 offset) -{ - return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); -} - static int pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; 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X-CSE-ConnectionGUID: gSZokyagSqORzXVhGfsseQ== X-CSE-MsgGUID: t0drFPq6SpOpxH0R+s6oVA== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751308" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751308" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: M/jCZlfASo+xtQcDWilv3w== X-CSE-MsgGUID: pXYgZuNUSWar8u7PcJJX3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363902" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: Xi Pardee , david.e.box@linux.intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH v6 12/15] platform/x86/intel/pmc/ssram: Switch to static array with per-index probe state Date: Sun, 31 May 2026 12:46:14 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xi Pardee Replace devm-allocated pmc_ssram_telems pointer with a fixed-size static array and introduce per-index probe state tracking. This prepares the driver for later per-device probe handling where tying the PMC tracking storage to one probed PCI device is no longer suitable. The previous single global device_probed flag cannot describe the state of individual PMC indices when multiple devices can be probed independently. Replace it with per-index state (UNPROBED, PROBING, PRESENT, ABSENT) and a staging cache that publishes discovered values only after probe completes. This avoids races between probe/unbind and concurrent readers. Use READ_ONCE/WRITE_ONCE for pmc_ssram_state[] accesses to prevent compiler optimizations from refetching or tearing the state value across concurrent probe/unbind cycles. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Assisted-by: Claude:claude-sonnet-4-5 --- V6 changes: - Squashed patch combining v5 patches 10 ("Use fixed-size static pmc array") and 13 ("Refactor memory barrier for reentrant probe"). Both patches addressed per-index probe state tracking and reentrant probe protection, so they were combined for better logical cohesion. - Added per-index probe state enum (UNPROBED, PROBING, PRESENT, ABSENT) to replace devid overload where devid was used as both payload and probe state indicator. This fixes stale data issues on reprobe, distinguishes between -EAGAIN (probe in progress) and -ENODEV (probe failed) error semantics, and prevents stale values from being visible after failed reprobe (Ilpo/Sashiko/Claude). - Added staging cache that publishes devid and base_addr only after probe completes successfully to avoid races between probe/unbind and concurrent readers. - Added .remove callback to handle proper state cleanup on driver unbind. - Used READ_ONCE/WRITE_ONCE for pmc_ssram_state[] accesses to prevent compiler optimizations from causing issues across concurrent probe/ unbind cycles. V5 - No changes (for both original patches) V4 - No changes (for both original patches) V3 - No changes (for both original patches) V2 changes (from original patch 10 "Use fixed-size static pmc array"): - Replaced hardcoded array size [3] with MAX_NUM_PMC constant V2 changes (from original patch 13 "Refactor memory barrier"): - Expanded commit message to explain synchronization rationale - Remove unused probe_finish label associated with the old global flag .../platform/x86/intel/pmc/ssram_telemetry.c | 198 ++++++++++++++---- 1 file changed, 159 insertions(+), 39 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index e7ddd1788132..ad961ee469b2 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -24,6 +25,7 @@ #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 #define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3) +#define SSRAM_PCI_PMC_MASK (BIT(PMC_IDX_MAIN) | BIT(PMC_IDX_IOE) | BIT(PMC= _IDX_PCH)) =20 DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_= T)) =20 @@ -39,15 +41,33 @@ static const struct ssram_type pci_main =3D { .method =3D RES_METHOD_PCI, }; =20 -static struct pmc_ssram_telemetry *pmc_ssram_telems; -static bool device_probed; +enum pmc_ssram_state { + PMC_SSRAM_UNPROBED, + PMC_SSRAM_PROBING, + PMC_SSRAM_PRESENT, + PMC_SSRAM_ABSENT, +}; + +static enum pmc_ssram_state pmc_ssram_state[MAX_NUM_PMC]; +static struct pmc_ssram_telemetry pmc_ssram_telems[MAX_NUM_PMC]; + +struct pmc_ssram_probe_cache { + struct pmc_ssram_telemetry telems[MAX_NUM_PMC]; + unsigned long owned_mask; + unsigned long valid_mask; +}; + +struct pmc_ssram_drvdata { + unsigned long owned_mask; +}; =20 static inline u64 get_base(void __iomem *addr, u32 offset) { return lo_hi_readq(addr + offset) & SSRAM_BASE_ADDR_MASK; } =20 -static void pmc_ssram_get_devid_pwrmbase(void __iomem *ssram, unsigned int= pmc_idx) +static void pmc_ssram_get_devid_pwrmbase(struct pmc_ssram_probe_cache *pro= be_cache, + void __iomem *ssram, unsigned int pmc_idx) { u64 pwrm_base; u16 devid; @@ -55,8 +75,46 @@ static void pmc_ssram_get_devid_pwrmbase(void __iomem *s= sram, unsigned int pmc_i pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); devid =3D readw(ssram + SSRAM_DEVID_OFFSET); =20 - pmc_ssram_telems[pmc_idx].devid =3D devid; - pmc_ssram_telems[pmc_idx].base_addr =3D pwrm_base; + probe_cache->telems[pmc_idx].base_addr =3D pwrm_base; + probe_cache->telems[pmc_idx].devid =3D devid; +} + +static void pmc_ssram_publish_absent(unsigned int pmc_idx) +{ + /* + * Publish only the state without modifying telemetry data. This avoids + * a TOCTOU race where a reader that sampled state=3D=3DPRESENT before un= bind + * could read modified data after its smp_rmb(). Readers check state first + * and return -ENODEV for ABSENT without accessing data. + */ + WRITE_ONCE(pmc_ssram_state[pmc_idx], PMC_SSRAM_ABSENT); +} + +static void pmc_ssram_publish_present(struct pmc_ssram_probe_cache *probe_= cache, + unsigned int pmc_idx) +{ + /* + * The devid and base_addr fields are read from immutable hardware MMIO + * registers and do not change across unbind/rebind cycles. A reader + * observing PRESENT from an earlier probe can safely read fields being + * updated by a concurrent rebind because both probes read identical + * values from the same hardware. + */ + pmc_ssram_telems[pmc_idx] =3D probe_cache->telems[pmc_idx]; + /* + * Barrier ensures telemetry data write completes before PRESENT state + * becomes visible. Pairs with smp_rmb() in reader. + */ + smp_wmb(); + WRITE_ONCE(pmc_ssram_state[pmc_idx], PMC_SSRAM_PRESENT); +} + +static void pmc_ssram_mark_probing(unsigned long mask) +{ + unsigned long bit; + + for_each_set_bit(bit, &mask, MAX_NUM_PMC) + WRITE_ONCE(pmc_ssram_state[bit], PMC_SSRAM_PROBING); } =20 static int @@ -96,11 +154,14 @@ pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u6= 4 ssram_base, void __iomem } =20 static int -pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, unsigned int pmc_i= dx, u32 offset) +pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache, + unsigned int pmc_idx, u32 offset) { void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram =3D NULL; void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D NULL; u64 ssram_base; + int ret; =20 ssram_base =3D pci_resource_start(pcidev, 0); tmp_ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); @@ -125,22 +186,38 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcide= v, unsigned int pmc_idx, u3 ssram =3D no_free_ptr(tmp_ssram); } =20 - pmc_ssram_get_devid_pwrmbase(ssram, pmc_idx); + pmc_ssram_get_devid_pwrmbase(probe_cache, ssram, pmc_idx); =20 /* Find and register and PMC telemetry entries */ - return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); + ret =3D pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); + if (ret) + return ret; + + probe_cache->valid_mask |=3D BIT(pmc_idx); + + return 0; } =20 -static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev) +static int pmc_ssram_telemetry_pci_init(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache) { int ret; =20 - ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_MAIN, 0); + ret =3D pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_MAIN= , 0); if (ret) return ret; =20 - pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); - pmc_ssram_telemetry_get_pmc_pci(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + /* + * If MAIN PMC enumeration is successful but either IOE or PCH fail, + * don't fail probe as the MAIN PMC is still useful as it provides the + * global reset and slp_s0 counter access. Failed or missing secondary + * PMCs are left out of valid_mask and published as absent. + */ + pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_IOE, + SSRAM_IOE_OFFSET); + + pmc_ssram_telemetry_get_pmc_pci(pcidev, probe_cache, PMC_IDX_PCH, + SSRAM_PCH_OFFSET); =20 return ret; } @@ -159,53 +236,86 @@ static int pmc_ssram_telemetry_pci_init(struct pci_de= v *pcidev) int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx, struct pmc_ssram_telemetry *pmc_ssram_telemetry) { + enum pmc_ssram_state state; + + if (pmc_idx >=3D MAX_NUM_PMC) + return -EINVAL; + /* * PMCs are discovered in probe function. If this function is called befo= re - * probe function complete, the result would be invalid. Use device_probed - * variable to avoid this case. Return -EAGAIN to inform the consumer to = call - * again later. + * probe function complete, the result would be invalid. Use per-PMC state + * to inform the consumer to call again later. */ - if (!device_probed) + state =3D READ_ONCE(pmc_ssram_state[pmc_idx]); + if (state =3D=3D PMC_SSRAM_UNPROBED || state =3D=3D PMC_SSRAM_PROBING) return -EAGAIN; =20 + if (state =3D=3D PMC_SSRAM_ABSENT) + return -ENODEV; + /* * Memory barrier is used to ensure the correct read order between - * device_probed variable and PMC info. + * pmc_ssram_state and PMC info. */ smp_rmb(); - if (pmc_idx >=3D MAX_NUM_PMC) - return -EINVAL; - - if (!pmc_ssram_telems || !pmc_ssram_telems[pmc_idx].devid) - return -ENODEV; - pmc_ssram_telemetry->devid =3D pmc_ssram_telems[pmc_idx].devid; pmc_ssram_telemetry->base_addr =3D pmc_ssram_telems[pmc_idx].base_addr; return 0; } EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); =20 +static void pmc_ssram_publish_absent_mask(unsigned long mask) +{ + unsigned long bit; + + for_each_set_bit(bit, &mask, MAX_NUM_PMC) + pmc_ssram_publish_absent(bit); +} + +static void pmc_ssram_publish_telems(struct pmc_ssram_probe_cache *probe_c= ache, int ret) +{ + unsigned long bit; + + if (ret) { + pmc_ssram_publish_absent_mask(probe_cache->owned_mask); + return; + } + + for_each_set_bit(bit, &probe_cache->owned_mask, MAX_NUM_PMC) { + if (probe_cache->valid_mask & BIT(bit)) + pmc_ssram_publish_present(probe_cache, bit); + else + pmc_ssram_publish_absent(bit); + } +} + static int pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct = pci_device_id *id) { + struct pmc_ssram_probe_cache probe_cache =3D {}; + struct pmc_ssram_drvdata *drvdata; const struct ssram_type *ssram_type; enum resource_method method; int ret; =20 - pmc_ssram_telems =3D devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems)= * MAX_NUM_PMC, - GFP_KERNEL); - if (!pmc_ssram_telems) { - ret =3D -ENOMEM; - goto probe_finish; - } - ssram_type =3D (const struct ssram_type *)id->driver_data; if (!ssram_type) { dev_dbg(&pcidev->dev, "missing driver data\n"); - ret =3D -EINVAL; - goto probe_finish; + return -EINVAL; } =20 method =3D ssram_type->method; + if (method =3D=3D RES_METHOD_PCI) + probe_cache.owned_mask =3D SSRAM_PCI_PMC_MASK; + else + return -EINVAL; + + pmc_ssram_mark_probing(probe_cache.owned_mask); + + drvdata =3D devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) { + ret =3D -ENOMEM; + goto probe_finish; + } =20 ret =3D pcim_enable_device(pcidev); if (ret) { @@ -214,20 +324,29 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *= pcidev, const struct pci_de } =20 if (method =3D=3D RES_METHOD_PCI) - ret =3D pmc_ssram_telemetry_pci_init(pcidev); + ret =3D pmc_ssram_telemetry_pci_init(pcidev, &probe_cache); else ret =3D -EINVAL; =20 + if (!ret) { + drvdata->owned_mask =3D probe_cache.owned_mask; + pci_set_drvdata(pcidev, drvdata); + } + probe_finish: - /* - * Memory barrier is used to ensure the correct write order between PMC i= nfo - * and device_probed variable. - */ - smp_wmb(); - device_probed =3D true; + pmc_ssram_publish_telems(&probe_cache, ret); + return ret; } =20 +static void pmc_ssram_telemetry_remove(struct pci_dev *pcidev) +{ + struct pmc_ssram_drvdata *drvdata =3D pci_get_drvdata(pcidev); + + if (drvdata) + pmc_ssram_publish_absent_mask(drvdata->owned_mask); +} + static const struct pci_device_id pmc_ssram_telemetry_pci_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM), .driver_data =3D (kernel_ulong_t)&pci_main }, @@ -251,6 +370,7 @@ static struct pci_driver pmc_ssram_telemetry_driver =3D= { .name =3D "intel_pmc_ssram_telemetry", .id_table =3D pmc_ssram_telemetry_pci_ids, .probe =3D pmc_ssram_telemetry_probe, + .remove =3D pmc_ssram_telemetry_remove, }; module_pci_driver(pmc_ssram_telemetry_driver); =20 --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 206C533EB17; Sun, 31 May 2026 19:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="80751311" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 X-CSE-ConnectionGUID: EzF4okOCQSOS6dzaciyNsg== X-CSE-MsgGUID: QqqFvil0RKuS/jq1HfW71g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363903" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 13/15] platform/x86/intel/pmc/ssram: Add ACPI discovery scaffolding Date: Sun, 31 May 2026 12:46:15 -0700 Message-ID: <0437ded98dc4ae5b7fc6a07c8b2a5277290e7c49.1780248804.git.david.e.box@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the SSRAM telemetry driver for ACPI-based discovery by adding support for reading telemetry regions from ACPI _DSD properties. Add pmc_ssram_telemetry_acpi_init() to parse _DSD for telemetry discovery tables and register them with the Intel VSEC framework. Extend ssram_type with a p_index field to specify which PMC index each ACPI device owns (unlike PCI which discovers all three PMCs from one device). At this stage, no platform IDs are wired to use ACPI discovery - existing devices continue using the PCI path. Follow-on patches will add platform support. Assisted-by: Claude:claude-sonnet-4-5 Signed-off-by: Xi Pardee Signed-off-by: David E. Box --- V6 - No changes V5 changes: - Fix dsd_buf leak by moving the __free(pmc_acpi_free) declaration after acpi_evaluate_object() populates buf.pointer, and switched pmc_find_telem_guid(buf.pointer) to operate on dsd_buf so cleanup releases the actual allocation. - Split acpi_handle declaration from ACPI_HANDLE() assignment and placed the assignment immediately before the !handle check (Ilpo). - Reordered local variables in pmc_ssram_telemetry_acpi_init() in reverse-xmas-tree order (Ilpo). V4 - Replaced local raw ACPI discovery pointer type u32 (*)[4] with acpi_disc_t in SSRAM ACPI initialization path. V3 - No changes V2 changes: - Fixed cleanup patterns using __free() attributes - Addressed Ilpo's recommendations for safer cleanup.h patterns .../platform/x86/intel/pmc/ssram_telemetry.c | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index ad961ee469b2..7ebfbb177499 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -5,6 +5,7 @@ * Copyright (c) 2023, Intel Corporation. */ =20 +#include #include #include #include @@ -31,14 +32,17 @@ DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *= , if (_T) iounmap(_T)) =20 enum resource_method { RES_METHOD_PCI, + RES_METHOD_ACPI, }; =20 struct ssram_type { enum resource_method method; + enum pmc_index p_index; }; =20 static const struct ssram_type pci_main =3D { .method =3D RES_METHOD_PCI, + .p_index =3D PMC_IDX_MAIN, }; =20 enum pmc_ssram_state { @@ -222,6 +226,73 @@ static int pmc_ssram_telemetry_pci_init(struct pci_dev= *pcidev, return ret; } =20 +static int pmc_ssram_telemetry_get_pmc_acpi(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache, + unsigned int pmc_idx) +{ + u64 ssram_base; + + ssram_base =3D pci_resource_start(pcidev, 0); + if (!ssram_base) + return -ENODEV; + + void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram =3D + ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + return -ENOMEM; + + pmc_ssram_get_devid_pwrmbase(probe_cache, ssram, pmc_idx); + probe_cache->valid_mask |=3D BIT(pmc_idx); + + return 0; +} + +static int pmc_ssram_telemetry_acpi_init(struct pci_dev *pcidev, + struct pmc_ssram_probe_cache *probe_cache, + enum pmc_index index) +{ + struct intel_vsec_header header; + struct intel_vsec_header *headers[2] =3D { &header, NULL }; + struct acpi_buffer buf =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct intel_vsec_platform_info info =3D { }; + union acpi_object *dsd; + acpi_handle handle; + acpi_status status; + int ret; + + handle =3D ACPI_HANDLE(&pcidev->dev); + if (!handle) + return -ENODEV; + + status =3D acpi_evaluate_object(handle, "_DSD", NULL, &buf); + if (ACPI_FAILURE(status)) + return -ENODEV; + + void *dsd_buf __free(pmc_acpi_free) =3D buf.pointer; + + dsd =3D pmc_find_telem_guid(dsd_buf); + if (!dsd) + return -ENODEV; + + acpi_disc_t disc __free(kfree) =3D pmc_parse_telem_dsd(dsd, &header); + if (IS_ERR(disc)) + return PTR_ERR(disc); + + info.headers =3D headers; + info.caps =3D VSEC_CAP_TELEMETRY; + info.acpi_disc =3D disc; + info.src =3D INTEL_VSEC_DISC_ACPI; + + /* This is an ACPI companion device. PCI BAR will be used for base addr. = */ + info.base_addr =3D 0; + + ret =3D intel_vsec_register(&pcidev->dev, &info); + if (ret) + return ret; + + return pmc_ssram_telemetry_get_pmc_acpi(pcidev, probe_cache, index); +} + /** * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr info= rmation * @pmc_idx: Index of the PMC @@ -295,6 +366,7 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de struct pmc_ssram_drvdata *drvdata; const struct ssram_type *ssram_type; enum resource_method method; + enum pmc_index index; int ret; =20 ssram_type =3D (const struct ssram_type *)id->driver_data; @@ -303,9 +375,12 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *p= cidev, const struct pci_de return -EINVAL; } =20 + index =3D ssram_type->p_index; method =3D ssram_type->method; if (method =3D=3D RES_METHOD_PCI) probe_cache.owned_mask =3D SSRAM_PCI_PMC_MASK; + else if (method =3D=3D RES_METHOD_ACPI) + probe_cache.owned_mask =3D BIT(index); else return -EINVAL; =20 @@ -325,6 +400,8 @@ static int pmc_ssram_telemetry_probe(struct pci_dev *pc= idev, const struct pci_de =20 if (method =3D=3D RES_METHOD_PCI) ret =3D pmc_ssram_telemetry_pci_init(pcidev, &probe_cache); + else if (method =3D=3D RES_METHOD_ACPI) + ret =3D pmc_ssram_telemetry_acpi_init(pcidev, &probe_cache, index); else ret =3D -EINVAL; =20 @@ -375,6 +452,7 @@ static struct pci_driver pmc_ssram_telemetry_driver =3D= { module_pci_driver(pmc_ssram_telemetry_driver); =20 MODULE_IMPORT_NS("INTEL_VSEC"); +MODULE_IMPORT_NS("INTEL_PMC_CORE"); MODULE_AUTHOR("Xi Pardee "); MODULE_DESCRIPTION("Intel PMC SSRAM Telemetry driver"); MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 804A6342532; Sun, 31 May 2026 19:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256811; cv=none; b=ewA7QkF+jng7Ht7wRA7CGU/Js0C0VCQ+tbYss6l84tT0F3nx/hMx2sX6KVMNyxuZnkY3+KJn+dqJDeheHFa/ueAeXg6WsxLBpvqWOvKTRIWzXbLF8XKW67i8lVJMEQ4AoPK04SpKgZBKD/dEO6H7f83ngOHW5mUV+GCfaEg2q6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256811; c=relaxed/simple; bh=eummtBHJWZr+4kyo8IrQtTlGGaxS1Tt2BAi8273f5RU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r/B1tKvwfdUfGGhTXXvw5WjQ+T1B+zO7t0q0x6sonpxay52Tl/agN8jg2bi9/AqL+yhyPsK6fU8wZrj50paDkEiRre8iep2REo425T2rGZV27tHDuTs4fsFjGxqoikACQWuD1BeO35eajshTY/h2jNYePc37KX1JFmmWmas5+7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MX45sIgo; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MX45sIgo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256810; x=1811792810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eummtBHJWZr+4kyo8IrQtTlGGaxS1Tt2BAi8273f5RU=; b=MX45sIgoU2978T3h1hhW95g9RXuR0mYSKcHIUqb2l9kmOa9fIq7ypqpr 2tvTVlHuB/Rbs+MKKiRigrfFvNCk/8wWV7HwQjyi1OH+WdpN+itE7rR1m XPCLpq/9R4tXwP35S1kF8LQ/XB3ChV4L5ff0suB7oSQdAIjXzCXzihXmT ZRzHXcXpLwEI06jv48WJPK2m4f1ZnfnWVEocr5Z5EOnTMcZU9AuKDO/EH s9IMgUp5sGpXyK/wOpxj1Gu/Rf4qQwlD9MGFd5fOoqy4crqIo3L+ObxVx tCnqPYDgYRfH11cDxF8RKrKYgPTi+Iuh5tfgTO5/bsdwQXWE1D/4c+357 w==; X-CSE-ConnectionGUID: aszQD9ocQv2kwe1Hw/ROow== X-CSE-MsgGUID: rkXMIgUhTnGTE7UjoxlO+A== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751314" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751314" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:26 -0700 X-CSE-ConnectionGUID: YQfj+QMiRiGOy2rgmN3W8g== X-CSE-MsgGUID: /aK3vduRRNmz1axnGlYpdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363904" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 14/15] platform/x86/intel/pmc/ssram: Make PMT registration optional Date: Sun, 31 May 2026 12:46:16 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SSRAM telemetry driver extracts essential PMC device ID and power management base address information that intel_pmc_core depends on for core functionality. If PMT registration failure prevents this critical data from being available, intel_pmc_core operation would break entirely. Therefore, PMT registration failures must not block access to this data. Change the behavior to log a warning when PMT registration fails but continue with successful driver initialization, ensuring the primary telemetry data remains accessible to dependent drivers. Signed-off-by: David E. Box --- V6 - No changes V5 - No changes V4 - No changes V3 changes: - Dropped the standalone cleanup-pattern patch from this refreshed series retaining the simpler ssram pointer flow requested in review. - Folded PMT-registration-optional handling onto that simpler flow with no intended functional change. V2 changes: - Update commit message for clarity - Also apply the PCI telemetry path drivers/platform/x86/intel/pmc/ssram_telemetry.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index 7ebfbb177499..b7cc4b540221 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -195,7 +195,7 @@ pmc_ssram_telemetry_get_pmc_pci(struct pci_dev *pcidev, /* Find and register and PMC telemetry entries */ ret =3D pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); if (ret) - return ret; + dev_warn(&pcidev->dev, "could not register PMT\n"); =20 probe_cache->valid_mask |=3D BIT(pmc_idx); =20 @@ -288,7 +288,7 @@ static int pmc_ssram_telemetry_acpi_init(struct pci_dev= *pcidev, =20 ret =3D intel_vsec_register(&pcidev->dev, &info); if (ret) - return ret; + dev_warn(&pcidev->dev, "could not register PMT\n"); =20 return pmc_ssram_telemetry_get_pmc_acpi(pcidev, probe_cache, index); } --=20 2.43.0 From nobody Mon Jun 8 07:21:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A340344DA8; Sun, 31 May 2026 19:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256812; cv=none; b=mJQsh8CnH0sTGRRDbhucmYselH+m1xIbx11YtM0roeR5gpBvTKK9Y+v6qhiP8z6QXzoLHINI6b0iFqnt1PSsKcu7Heme+O8Vetj8mMBf8SBez++PvmWSkXjyuMGvzC3g4yC0x594wS0PO5+X/tBl6yP1YQLict32ML9TKg9FF5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780256812; c=relaxed/simple; bh=LqX6b1jX4VzxJoqs09JQuLu/U4vArpVNUDEjNrQgkMM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uRsUdZNELFXJn7op8m6Npz+/V5rz0qORvfqoo9QODxv6gTp7+ROhI02lIdq0weWB4WEHcxh5hIgLNbFycfIV0ilF1t9wEhwme4cQhnii5rW8/kqkS1tEpW6lJFXvTGZfjgXTBfpgptCkm4GVuI1umRzLNYFma7SFgAPaSwSK9qU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fwFM5clX; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fwFM5clX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780256811; x=1811792811; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LqX6b1jX4VzxJoqs09JQuLu/U4vArpVNUDEjNrQgkMM=; b=fwFM5clXdCl36ylX2ycWqLX6m0nPgZ9LQAaFQ+z3D55YcmOm5vV+oXXq PkMQWfKxvLMyH2gvpKkmDXG8F4cx033wM8Lp1kEXV+JSRIF8SHyf5PJif Qi9YBx0EiWw6WSKuXz2nePmLqFuq6ij5LGKwady9VYgH41LIaeAyn7MeT pFO5G7wTXAjbYa3dltc/ypPDOSCAJRYuBFYfcDWmsaGwCvERXnfuDYyta fp8r/4A/G7y/9s4vShL8mn5OpRRYOqSiWWlony1lwdzWNDZj0TfyZz1A+ cWy/HeAJic8K+d/a1ejcW22FvpnCiUq/EgUGzeItikr/DtwMdnkEbbW2F A==; X-CSE-ConnectionGUID: iINlpfDyTxKUy0YfiwlWtg== X-CSE-MsgGUID: 3/GcYY5uRhmgcZfYHHs+ww== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80751315" X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="80751315" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:26 -0700 X-CSE-ConnectionGUID: fA1qHD3TRA+5pc38HY74Zw== X-CSE-MsgGUID: ngdMOH9bQnG+srazn02Vrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,179,1774335600"; d="scan'208";a="247363905" Received: from debox1-desk4.jf.intel.com ([10.88.27.138]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 12:46:25 -0700 From: "David E. Box" To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com Cc: "David E. Box" , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com Subject: [PATCH v6 15/15] platform/x86/intel/pmc: Add NVL PCI IDs for SSRAM telemetry discovery Date: Sun, 31 May 2026 12:46:17 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Nova Lake S PMC device IDs to enable binding of the SSRAM telemetry driver on NVL platforms, and map them to the ACPI-based discovery policy. Signed-off-by: David E. Box --- V6 - Dropped NVL product defines in core.h as they we already included in a prior patch from Xi. V5 - No changes V4 - No changes V3 - No changes V2 - No changes drivers/platform/x86/intel/pmc/ssram_telemetry.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/pla= tform/x86/intel/pmc/ssram_telemetry.c index b7cc4b540221..cf34964b4e47 100644 --- a/drivers/platform/x86/intel/pmc/ssram_telemetry.c +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -45,6 +45,16 @@ static const struct ssram_type pci_main =3D { .p_index =3D PMC_IDX_MAIN, }; =20 +static const struct ssram_type acpi_main =3D { + .method =3D RES_METHOD_ACPI, + .p_index =3D PMC_IDX_MAIN, +}; + +static const struct ssram_type acpi_pch =3D { + .method =3D RES_METHOD_ACPI, + .p_index =3D PMC_IDX_PCH, +}; + enum pmc_ssram_state { PMC_SSRAM_UNPROBED, PMC_SSRAM_PROBING, @@ -439,6 +449,12 @@ static const struct pci_device_id pmc_ssram_telemetry_= pci_ids[] =3D { .driver_data =3D (kernel_ulong_t)&pci_main }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_WCL_PCDN), .driver_data =3D (kernel_ulong_t)&pci_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDH), + .driver_data =3D (kernel_ulong_t)&acpi_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCDS), + .driver_data =3D (kernel_ulong_t)&acpi_main }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_NVL_PCHS), + .driver_data =3D (kernel_ulong_t)&acpi_pch }, { } }; MODULE_DEVICE_TABLE(pci, pmc_ssram_telemetry_pci_ids); --=20 2.43.0