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Thu, 28 May 2026 00:59:57 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 01/11] iommu/arm-smmu-v3: Add arm_smmu_attach_release() Date: Thu, 28 May 2026 00:59:29 -0700 Message-ID: <7771eae55f8c21dc7a90a52b9298486fae1ef63a.1779944354.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|DM4PR12MB7527:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a246681-3084-43a5-002c-08debc8f2751 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700016|56012099006|11063799006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: wPDnVxmAbYnbUJhPSNHmUPSZfJxGPO2uwn2S3zp+Q81kLzvlq7BYFGHqqPNKx8eQsV0KL/ZqQHYROfo1PchJUamWnhbc47hR42hpD/OhoSlyGdWrT3jveCFdVPXVn9P2A6cno1GcNIsTMhBaoByuJ05H0Dt3EHmiw0CtrKP9cxCMCZ5dm+YvHu9l3XTm1Pe0qKwUenk04upEPSJRHwN3xssIPvajgoGMBNncfhKYh/wJ/YQKGbjQg8Q4wYc5lWkakHH1+4M7XaJGS5Izrj5GmXl/hZCGecHSTDyYTL4OKHgNlItRiJCyv520VfhyRtpAwShQxaAhRZQouKCmO48eChJTXDI2O4YuRG7eLPsYL827cqMOpCu09CTLL6yTo6NvtM5u9PcPdnnwguDwpDwDAU59R8MAE5INt+NWIbbfx2KVamgnkfDNXWDpgHIRrumV/nSQ3+ZChFGsnzZ6w5bpT4KD2BcUzhAFL/DIYoWIBYWYFoYG2SZhPuz1o2877eeS9y/atuhT1x1U24xXJQ1ksppTOEyfAkolMZP9hIWsT5+n+jDHYCjPi30RaVRPyCJ7o8GrVqtnIqEQRdSoXN7745+ApZ8mrNznMqfJjj2jQKPtdiHZbVbWfYBFQmHM1C2L1PGY4y2iffEkuonZuzEaOfblPzlmkCNRZdZNNxCydgVp8+1ZS0vqoRHPK5O2YfzLh/IRAePiypZzlbTxfKd7LPs5ucmmN2VKXm94hJxsh4Y= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700016)(56012099006)(11063799006)(18002099003)(22082099003);DIR:OUT;SFP:1101; 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charset="utf-8" The IOPF teardown is done in arm_smmu_remove_master_domain() when releasing the master_domain on detach, under the global arm_smmu_asid_lock mutex. But the teardown must drain any in-flight IOPF (for the old domain), before the master_domain is freed via iopf_queue_flush_dev() calling flush_workqueue() that can block on user-faulting page-fault handlers. Doing so when holding the arm_smmu_asid_lock would stall any unrelated attachment in the system. Split the teardown out of arm_smmu_remove_master_domain(), to a new helper arm_smmu_attach_release() that runs after arm_smmu_asid_lock is released. Since no other device would use the old master_domain that is being freed, it's safe to move out of arm_smmu_asid_lock (still under the protection of iommu_group->mutex). Note: this is a pure refactor; no functional change; it is a prerequisite to apply bug fix calling iopf_queue_flush_dev(). Fixes: cfea71aea921 ("iommu/arm-smmu-v3: Put iopf enablement in the domain = attach path") Cc: stable@vger.kernel.org # v6.16 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 33 +++++++++++++++---- 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 16353596e08ad..2bb810e4d5fce 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1197,12 +1197,14 @@ struct arm_smmu_attach_state { struct arm_smmu_vmaster *vmaster; struct arm_smmu_inv_state old_domain_invst; struct arm_smmu_inv_state new_domain_invst; + struct arm_smmu_master_domain *old_master_domain; bool ats_enabled; }; =20 int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, struct iommu_domain *new_domain); void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); +void arm_smmu_attach_release(struct arm_smmu_attach_state *state); void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, const struct arm_smmu_ste *target); =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 1e9f7d2de3441..e53c8e97ba190 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -191,6 +191,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_doma= in *domain, arm_smmu_install_ste_for_dev(master, &ste); arm_smmu_attach_commit(&state); mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_attach_release(&state); return 0; } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8ce3e801eda3b..620c67811df48 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3195,9 +3195,9 @@ arm_smmu_master_build_invs(struct arm_smmu_master *ma= ster, bool ats_enabled, return master->build_invs; } =20 -static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, - struct iommu_domain *domain, - ioasid_t ssid) +static struct arm_smmu_master_domain * +arm_smmu_remove_master_domain(struct arm_smmu_master *master, + struct iommu_domain *domain, ioasid_t ssid) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain_devices(domain); struct arm_smmu_master_domain *master_domain; @@ -3205,7 +3205,7 @@ static void arm_smmu_remove_master_domain(struct arm_= smmu_master *master, unsigned long flags; =20 if (!smmu_domain) - return; + return NULL; =20 if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) nested_ats_flush =3D to_smmu_nested_domain(domain)->enable_ats; @@ -3220,8 +3220,23 @@ static void arm_smmu_remove_master_domain(struct arm= _smmu_master *master, } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 + /* arm_smmu_attach_release() will free it */ + return master_domain; +} + +/* Release the old master_domain detached by arm_smmu_remove_master_domain= () */ +void arm_smmu_attach_release(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_master_domain *master_domain =3D state->old_master_domain; + struct arm_smmu_master *master =3D state->master; + + iommu_group_mutex_assert(master->dev); + + if (!master_domain) + return; arm_smmu_disable_iopf(master, master_domain); kfree(master_domain); + state->old_master_domain =3D NULL; } =20 /* @@ -3519,7 +3534,8 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_st= ate *state) arm_smmu_atc_inv_master(master, IOMMU_NO_PASID); } =20 - arm_smmu_remove_master_domain(master, state->old_domain, state->ssid); + state->old_master_domain =3D arm_smmu_remove_master_domain( + master, state->old_domain, state->ssid); arm_smmu_install_old_domain_invs(state); master->ats_enabled =3D state->ats_enabled; } @@ -3594,6 +3610,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, =20 arm_smmu_attach_commit(&state); mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_attach_release(&state); return 0; } =20 @@ -3694,6 +3711,7 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, =20 out_unlock: mutex_unlock(&arm_smmu_asid_lock); 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charset="utf-8" queue_empty() and queue_consumed() each compare a ring-position pair where one operand is fixed to a cached llq field (q->prod, q->cons). A subsequent change will need the same ring-position comparisons against a CONS value read live from MMIO into a local, which does not live in q->llq. Factor the ring-position checks in queue_empty() and queue_consumed() into __queue_empty() and __queue_consumed() primitives that accept both operands explicitly. queue_empty() and queue_consumed() become pass-through wrappers that pass the cached fields. No functional change intended; it's a prerequisite to apply bug fix calling iopf_queue_flush_dev(). Fixes: cfea71aea921 ("iommu/arm-smmu-v3: Put iopf enablement in the domain = attach path") Cc: stable@vger.kernel.org # v6.16 Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 +++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 620c67811df48..cf41b3cf5985f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -146,18 +146,28 @@ static bool queue_full(struct arm_smmu_ll_queue *q) Q_WRP(q, q->prod) !=3D Q_WRP(q, q->cons); } =20 +static bool __queue_empty(struct arm_smmu_ll_queue *q, u32 cons, u32 prod) +{ + return Q_IDX(q, prod) =3D=3D Q_IDX(q, cons) && + Q_WRP(q, prod) =3D=3D Q_WRP(q, cons); +} + static bool queue_empty(struct arm_smmu_ll_queue *q) { - return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) && - Q_WRP(q, q->prod) =3D=3D Q_WRP(q, q->cons); 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charset="utf-8" A poll-until-empty form does not converge on the shared EVTQ or PRIQ since other masters keep advancing PROD with unrelated traffic. A fixed snapshot bounds the wait even under sustained unrelated load, since the target does not move with subsequent enqueues. Add a helper that drains an SMMU EVTQ or PRIQ up to a PROD snapshot taken on entry, waiting until CONS reaches the snapshot. Every entry already in the queue is consumed by the threaded IRQ handler before this returns. A subsequent change uses it from the IOPF attach-release path. SMMUv3 guarantees that after a CMD_SYNC following STE/CD invalidation and any CMD_ATC_INV, no further entries tied to the pre-SYNC configuration will appear in either queue. A caller that has completed that sequence captures its entire in-flight cohort in the snapshot. Read CONS from MMIO each iteration so the comparison does not rely on the cached llq->cons, which the threaded handler owns. Disable WFE since SMMU does not signal SEV on EVTQ/PRIQ PROD advance. Call cond_resched() inside the loop so this caller does not starve the threaded IRQ handler it waits on when both share a CPU on a non-preemptible kernel. This is a prerequisite to apply bug fix calling iopf_queue_flush_dev(). Fixes: cfea71aea921 ("iommu/arm-smmu-v3: Put iopf enablement in the domain = attach path") Cc: stable@vger.kernel.org # v6.16 Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 +++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index cf41b3cf5985f..4794a15f351c4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -894,6 +894,33 @@ static int arm_smmu_cmdq_batch_submit(struct arm_smmu_= device *smmu, cmds->num, true); } =20 +/* Drain an SMMU EVTQ or PRIQ to a PROD snapshot taken on entry */ +static int arm_smmu_drain_queue_for_iopf(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q) +{ + struct arm_smmu_queue_poll qp; + u32 prod, cons; + int ret =3D 0; + + /* Snapshot PROD; entries [old_cons, prod) are the cohort to drain */ + prod =3D readl_relaxed(q->prod_reg); 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charset="utf-8" When a device is switching away from a domain, either through a detach or a replace operation, in-flight stall events for the old domain might still be on the SMMU's hardware event queue or on the IOMMU core's IOPF queue. Thus, if the IOMMU core swaps the device's attach_handle and frees the old domain before those handlers complete, the IOPF work might hit use-after-free. Two queues need to be drained: the SMMU hardware event queue and the IOMMU core IOPF software workqueue. Poll the evtq so that pending IRQs won't let the threaded handler run after the drain and queue a fault against the freed master_domain. Then, synchronize_irq() on the evtq. queue_remove_raw() advances MMIO CONS before the caller pushes an event to the IOPF queue, so the first step does not on its own guarantee every event has been queued. It must wait for the IRQ handler to finish to close that gap. Lastly, invoke iopf_queue_flush_dev() to drain the IOPF workqueue. Fixes: cfea71aea921 ("iommu/arm-smmu-v3: Put iopf enablement in the domain = attach path") Cc: stable@vger.kernel.org # v6.16 Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 4794a15f351c4..ffc9621cd2288 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3267,10 +3267,29 @@ void arm_smmu_attach_release(struct arm_smmu_attach= _state *state) struct arm_smmu_master_domain *master_domain =3D state->old_master_domain; struct arm_smmu_master *master =3D state->master; =20 + lockdep_assert_not_held(&arm_smmu_asid_lock); iommu_group_mutex_assert(master->dev); =20 if (!master_domain) return; + + if (master_domain->using_iopf) { + struct arm_smmu_device *smmu =3D master->smmu; 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charset="utf-8" From: Malak Marrid To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() must issue a CMDQ_OP_PRI_RESP back to the SMMU. However, either a stall event in the EVTQ or a PRI request in the PRIQ can surface to the IOPF infrastructure with fault.type =3D=3D IOMMU_FAULT_PAGE_= REQ, and a single master can in principle be both stall-capable and PRI-capable (e.g. FEAT_STALL_FORCE on a PCIe device with PRI), so master state is not a reliable discriminator. Add IOMMU_FAULT_PAGE_REQUEST_STALLS_TRANS to the generic flags so the fault reporter can mark a page request that is holding the device's transaction: arm_smmu_handle_event() sets it on STALL events arm_smmu_handle_ppr() leaves it clear for PRI events Note: streams[0].id remains the RID because arm_smmu_enable_iopf() rejects num_streams !=3D 1. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + include/linux/iommu.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 75 +++++++++++++++------ 3 files changed, 58 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 2bb810e4d5fce..1083621705f16 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1007,6 +1007,7 @@ struct arm_smmu_master { /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; + bool pri_enabled : 1; bool ats_enabled : 1; bool ste_ats_enabled : 1; bool stall_enabled; diff --git a/include/linux/iommu.h b/include/linux/iommu.h index e587d4ac4d331..83c4dfcf20637 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -76,6 +76,7 @@ struct iommu_fault_page_request { #define IOMMU_FAULT_PAGE_REQUEST_PASID_VALID (1 << 0) #define IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE (1 << 1) #define IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID (1 << 2) +#define IOMMU_FAULT_PAGE_REQUEST_STALLS_TRANS (1 << 3) u32 flags; u32 pasid; u32 grpid; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ffc9621cd2288..061f1d46fda0d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -921,32 +921,68 @@ static int arm_smmu_drain_queue_for_iopf(struct arm_s= mmu_device *smmu, return ret; } =20 -static void arm_smmu_page_response(struct device *dev, struct iopf_fault *= unused, +static void arm_smmu_page_response(struct device *dev, struct iopf_fault *= evt, struct iommu_page_response *resp) { struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); - u8 resume_resp; + struct arm_smmu_cmd cmd; + int sid; =20 - if (WARN_ON(!master->stall_enabled)) + if (WARN_ON_ONCE(evt->fault.type !=3D IOMMU_FAULT_PAGE_REQ)) return; =20 - switch (resp->code) { - case IOMMU_PAGE_RESP_INVALID: - case IOMMU_PAGE_RESP_FAILURE: - resume_resp =3D CMDQ_RESUME_0_RESP_ABORT; - break; - case IOMMU_PAGE_RESP_SUCCESS: - resume_resp =3D CMDQ_RESUME_0_RESP_RETRY; - break; - default: - resume_resp =3D CMDQ_RESUME_0_RESP_TERM; - break; + /* IOPF is gated to num_streams =3D=3D 1 in arm_smmu_enable_iopf() */ + sid =3D master->streams[0].id; + + if (evt->fault.prm.flags & IOMMU_FAULT_PAGE_REQUEST_STALLS_TRANS) { + u8 resume_resp; + + if (WARN_ON_ONCE(!master->stall_enabled)) + return; + switch (resp->code) { + case IOMMU_PAGE_RESP_INVALID: + case IOMMU_PAGE_RESP_FAILURE: + resume_resp =3D CMDQ_RESUME_0_RESP_ABORT; + break; + case IOMMU_PAGE_RESP_SUCCESS: + resume_resp =3D CMDQ_RESUME_0_RESP_RETRY; + break; + default: + resume_resp =3D CMDQ_RESUME_0_RESP_TERM; + break; + } + cmd =3D arm_smmu_make_cmd_resume(sid, resp->grpid, resume_resp); + } else { + enum pri_resp pri_resp; + bool ssv; + + if (WARN_ON_ONCE(!master->pri_enabled)) + return; + /* PCIe allows only one PRG Response per group */ + if (!(evt->fault.prm.flags & + IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) + return; + switch (resp->code) { + case IOMMU_PAGE_RESP_SUCCESS: + pri_resp =3D PRI_RESP_SUCC; + break; + case IOMMU_PAGE_RESP_FAILURE: + pri_resp =3D PRI_RESP_FAIL; + break; + case IOMMU_PAGE_RESP_INVALID: + pri_resp =3D PRI_RESP_DENY; + break; + default: + WARN_ON(true); + return; + } + ssv =3D !!(evt->fault.prm.flags & + IOMMU_FAULT_PAGE_REQUEST_PASID_VALID); + cmd =3D arm_smmu_make_cmd_pri_resp(sid, resp->pasid, ssv, + resp->grpid, pri_resp); } =20 - arm_smmu_cmdq_issue_cmd(master->smmu, - arm_smmu_make_cmd_resume(master->streams[0].id, - resp->grpid, - resume_resp)); + arm_smmu_cmdq_issue_cmd(master->smmu, cmd); /* * Don't send a SYNC, it doesn't do anything for RESUME or PRI_RESP. * RESUME consumption guarantees that the stalled transaction will be @@ -2081,7 +2117,8 @@ static int arm_smmu_handle_event(struct arm_smmu_devi= ce *smmu, u64 *evt, =20 flt->type =3D IOMMU_FAULT_PAGE_REQ; flt->prm =3D (struct iommu_fault_page_request){ - .flags =3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE, + .flags =3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE | + IOMMU_FAULT_PAGE_REQUEST_STALLS_TRANS, .grpid =3D event->stag, .perm =3D perm, .addr =3D event->iova, --=20 2.43.0 From nobody Mon Jun 8 16:28:14 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012041.outbound.protection.outlook.com [52.101.48.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE03367B84; 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charset="utf-8" Now, arm_smmu_page_response() can issue CMDQ_OP_PRI_RESP for page requests from the IOPF infrastructure. Forward PRI requests from the priq into the IOPF infrastructure for PRI-enabled masters by building an iopf_fault from the priq entry and calling iommu_report_device_fault(). For an unrecognised StreamID or a master without master->pri_enabled, fall through to the existing "unexpected PRI request" log + LAST-page DENY path to release the credit per the PCIe PRI spec. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 061f1d46fda0d..371a8bbdf6756 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2242,6 +2242,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void= *dev) =20 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) { + struct arm_smmu_master *master; u32 sid, ssid; u16 grpid; bool ssv, last; @@ -2252,6 +2253,37 @@ static void arm_smmu_handle_ppr(struct arm_smmu_devi= ce *smmu, u64 *evt) last =3D FIELD_GET(PRIQ_0_PRG_LAST, evt[0]); grpid =3D FIELD_GET(PRIQ_1_PRG_IDX, evt[1]); =20 + mutex_lock(&smmu->streams_mutex); + master =3D arm_smmu_find_master(smmu, sid); + if (master && master->pri_enabled) { + struct iopf_fault iopf_fault =3D {0}; + struct iommu_fault *fault =3D &iopf_fault.fault; + + fault->type =3D IOMMU_FAULT_PAGE_REQ; + if (last) + fault->prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + if (ssv) { + fault->prm.flags |=3D + IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + fault->prm.pasid =3D ssid; + } + fault->prm.grpid =3D grpid; + if (evt[0] & PRIQ_0_PERM_READ) + fault->prm.perm |=3D IOMMU_FAULT_PERM_READ; + if (evt[0] & PRIQ_0_PERM_WRITE) + fault->prm.perm |=3D IOMMU_FAULT_PERM_WRITE; + if (evt[0] & PRIQ_0_PERM_EXEC) + fault->prm.perm |=3D IOMMU_FAULT_PERM_EXEC; + if (evt[0] & PRIQ_0_PERM_PRIV) + fault->prm.perm |=3D IOMMU_FAULT_PERM_PRIV; + fault->prm.addr =3D FIELD_GET(PRIQ_1_ADDR_MASK, evt[1]) << 12; + + iommu_report_device_fault(master->dev, &iopf_fault); + mutex_unlock(&smmu->streams_mutex); + return; + } + mutex_unlock(&smmu->streams_mutex); + dev_info(smmu->dev, "unexpected PRI request received:\n"); dev_info(smmu->dev, "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016l= lx\n", --=20 2.43.0 From nobody Mon Jun 8 16:28:14 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012021.outbound.protection.outlook.com [52.101.43.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C95E36A030; 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charset="utf-8" arm_smmu_setup_irqs() has three failure paths that leave the priq without a handler: a missing priq IRQ line, devm_request_threaded_irq() failure on the priq IRQ, and devm_request_threaded_irq() failure on the combined IRQ. Each path warned but kept ARM_SMMU_FEAT_PRI set in smmu->features. With FEAT_PRI still set, arm_smmu_probe_device() calls pci_enable_pri() on PCIe endpoints, which then issue PRI Page Requests that pile up in a priq with no drainer; arm_smmu_setup_irqs() also enables IRQ_CTRL_PRIQ_IRQEN against a handler that does not exist. Separately, arm_smmu_device_reset() has already enabled CR0_PRIQEN before calling arm_smmu_setup_irqs(), so the hardware queue stays enabled regardless of what setup_irqs decides. Clear ARM_SMMU_FEAT_PRI from all three failure paths so subsequent code treats PRI as unavailable. And disable CR0_PRIQEN after the setup function returns. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 371a8bbdf6756..72fd5caa27368 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4738,11 +4738,14 @@ static void arm_smmu_setup_unique_irqs(struct arm_s= mmu_device *smmu) IRQF_ONESHOT, "arm-smmu-v3-priq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable priq irq\n"); + smmu->features &=3D ~ARM_SMMU_FEAT_PRI; + } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); + smmu->features &=3D ~ARM_SMMU_FEAT_PRI; } } } @@ -4771,8 +4774,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_devic= e *smmu) arm_smmu_combined_irq_thread, IRQF_ONESHOT, "arm-smmu-v3-combined-irq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); 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charset="utf-8" arm_smmu_init_queues() allocates smmu->evtq.iopf only when FEAT_SVA and ARM_SMMU_FEAT_STALLS are both advertised. A subsequent change will add PRI support on top of the IOPF infrastructure, so the IOPF workqueue must also exist on SMMUs supporting FEAT_PRI without FEAT_STALLS. Extend the allocation condition to include FEAT_PRI. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 72fd5caa27368..87e4880a145f1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4504,7 +4504,7 @@ static int arm_smmu_init_queues(struct arm_smmu_devic= e *smmu) return ret; =20 if ((smmu->features & ARM_SMMU_FEAT_SVA) && - (smmu->features & ARM_SMMU_FEAT_STALLS)) { + (smmu->features & (ARM_SMMU_FEAT_STALLS | ARM_SMMU_FEAT_PRI))) { smmu->evtq.iopf =3D iopf_queue_alloc(dev_name(smmu->dev)); if (!smmu->evtq.iopf) return -ENOMEM; --=20 2.43.0 From nobody Mon Jun 8 16:28:14 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012049.outbound.protection.outlook.com [52.101.48.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3C4836DA1C; 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charset="utf-8" From: Jean-Philippe Brucker The SMMUv3 driver, which can be built without CONFIG_PCI, will soon gain support for PRI. Partially revert commit c6e9aefbf9db ("PCI/ATS: Remove unused PRI and PASID stubs") to re-introduce the PRI stubs, and avoid adding more #ifdefs to the SMMU driver. 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charset="utf-8" From: Jean-Philippe Brucker The SMMUv3 driver, which is tristate, calls pci_enable_pri() and pci_reset_pri() from its probe path. Export them so the driver can be built as a module. Link: https://lore.kernel.org/iommu/20201112125519.3987595-9-jean-philippe@= linaro.org/ Acked-by: Bjorn Helgaas Reviewed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Jean-Philippe Brucker [nicolinc: drop stale or already-exported APIs] Signed-off-by: Nicolin Chen --- drivers/pci/ats.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index ec6c8dbdc5e9c..c844c0cee3cb7 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -266,6 +266,7 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs) =20 return 0; } +EXPORT_SYMBOL_GPL(pci_enable_pri); =20 /** * pci_disable_pri - Disable PRI capability @@ -345,6 +346,7 @@ int pci_reset_pri(struct pci_dev *pdev) =20 return 0; } +EXPORT_SYMBOL_GPL(pci_reset_pri); =20 /** * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit --=20 2.43.0 From nobody Mon Jun 8 16:28:14 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010054.outbound.protection.outlook.com [52.101.61.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9CE736729D; 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charset="utf-8" Now PRI requests can be correctly handled. Enable the PCI cap when probing a PCI device. Also flush the priq in arm_smmu_attach_release(). Set the per-device outstanding request budget to the full priq depth, same as intel-iommu's per-device PRQ_DEPTH choice. A fixed per-device cap won't prevent multiple PRI-capable devices from potentially exceeding the priq's capacity; priq overflow is recoverable per the SMMUv3 spec, and it is rare in practice. select PCI_PRI in Kconfig like other IOMMUs, gated on PCI so the build can stay clean for non-PCI ARM SMMUv3 configurations. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/Kconfig | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 +++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index 5fac08b89deea..855934d08f866 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -79,6 +79,7 @@ config ARM_SMMU_V3 select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select GENERIC_MSI_IRQ + select PCI_PRI if PCI select IOMMUFD_DRIVER if IOMMUFD help Support for implementations of the ARM System MMU architecture diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 87e4880a145f1..648db9a24b582 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3149,7 +3149,7 @@ static int arm_smmu_enable_iopf(struct arm_smmu_maste= r *master, * device-specific fault handlers and don't need IOPF, so this is not a * failure. */ - if (!master->stall_enabled) + if (!master->stall_enabled && !master->pri_enabled) return 0; =20 /* We're not keeping track of SIDs in fault events */ @@ -3352,6 +3352,12 @@ void arm_smmu_attach_release(struct arm_smmu_attach_= state *state) if (smmu->evtq.q.irq) synchronize_irq(smmu->evtq.q.irq); } + /* Drain the hardware priq */ + if (master->pri_enabled) { + arm_smmu_drain_queue_for_iopf(smmu, &smmu->priq.q); + if (smmu->priq.q.irq) + synchronize_irq(smmu->priq.q.irq); + } /* Pending events might be in the combined_irq handler */ if (smmu->combined_irq) synchronize_irq(smmu->combined_irq); @@ -4282,8 +4288,17 @@ static struct iommu_device *arm_smmu_probe_device(st= ruct device *dev) =20 if (dev_is_pci(dev)) { unsigned int stu =3D __ffs(smmu->pgsize_bitmap); + struct pci_dev *pdev =3D to_pci_dev(dev); =20 - pci_prepare_ats(to_pci_dev(dev), stu); + if (!pci_prepare_ats(pdev, stu) && pci_pri_supported(pdev) && + (smmu->features & ARM_SMMU_FEAT_PRI) && smmu->evtq.iopf) { + unsigned int reqs =3D 1 << smmu->priq.q.llq.max_n_shift; + + if (!pci_reset_pri(pdev) && !pci_enable_pri(pdev, reqs)) + master->pri_enabled =3D true; + else + dev_warn(master->dev, "failed to enable PRI\n"); + } } =20 return &smmu->iommu; @@ -4299,6 +4314,8 @@ static void arm_smmu_release_device(struct device *de= v) =20 WARN_ON(master->iopf_refcount); =20 + if (master->pri_enabled) + pci_disable_pri(to_pci_dev(master->dev)); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); if (arm_smmu_cdtab_allocated(&master->cd_table)) --=20 2.43.0