From nobody Mon Jun 8 19:46:26 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0844C280A20; Wed, 27 May 2026 02:48:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850085; cv=none; b=KFRU97rcwXI8Iy8scE19yuG4s4to9u78JPp3UFkOhRrRTCWfd8Shbi+TUCxzpz+IjI3/txFN7Yl/8jo1DUxkGVBAAxdRmwlMJCDnqjr0ySqjfl3ENgxablEM+kuNbwkfrkq/Z2scb32kR5M+PRe93jnZ6OWr/O/XF5P+pIXqHkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850085; c=relaxed/simple; bh=+YaVXT3Qfz3bidbipcfu4uSlJzjQVzjGSoN3K3/6gKc=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=c5HzIlFzJ4Kvqmf5hOCH95m/fzt4Yq+UUZvwyJyN7mMG5cp1lmy3rIcdY191LmWUAh04J/xiitClYAltvhIS/QXyEa7zgDzZbQay+rSsvlInMOE4IkvAlrSMoM+0tRHeg181wNnrKat1D0/T4f5nn0xLEm02L8rLU4afL+v4tsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1wS4JN-000000006y5-0JPD; Wed, 27 May 2026 02:48:01 +0000 Date: Wed, 27 May 2026 03:47:58 +0100 From: Daniel Golle To: John Crispin , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v3 1/4] net: dsa: mxl862xx: store firmware version for feature gating Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Query the firmware version at init (already done in wait_ready), cache it in priv->fw_version, and provide MXL862XX_FW_VER_MIN() for version-gated code paths throughout the driver. MXL862XX_FW_VER() packs major/minor/revision into a u32 with bitwise shifts so that versions compare with natural ordering, independent of host endianness. Signed-off-by: Daniel Golle Reviewed-by: Andrew Lunn --- v3: use bitwise shifts in macro instead of endian-specific union v2: no changes drivers/net/dsa/mxl862xx/mxl862xx.c | 3 +++ drivers/net/dsa/mxl862xx/mxl862xx.h | 23 +++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.c b/drivers/net/dsa/mxl862xx= /mxl862xx.c index b60482d93a85..2f22adedfbf6 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx.c +++ b/drivers/net/dsa/mxl862xx/mxl862xx.c @@ -257,6 +257,9 @@ static int mxl862xx_wait_ready(struct dsa_switch *ds) ver.iv_major, ver.iv_minor, le16_to_cpu(ver.iv_revision), le32_to_cpu(ver.iv_build_num)); + priv->fw_version.major =3D ver.iv_major; + priv->fw_version.minor =3D ver.iv_minor; + priv->fw_version.revision =3D le16_to_cpu(ver.iv_revision); return 0; =20 not_ready_yet: diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.h b/drivers/net/dsa/mxl862xx= /mxl862xx.h index 80053ab40e4c..e3db3711b245 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx.h +++ b/drivers/net/dsa/mxl862xx/mxl862xx.h @@ -3,6 +3,7 @@ #ifndef __MXL862XX_H #define __MXL862XX_H =20 +#include #include #include #include @@ -241,6 +242,25 @@ struct mxl862xx_port { spinlock_t stats_lock; /* protects stats accumulators */ }; =20 +/** + * struct mxl862xx_fw_version - firmware version for comparison and display + * @major: firmware major version + * @minor: firmware minor version + * @revision: firmware revision number + */ +struct mxl862xx_fw_version { + u8 major; + u8 minor; + u16 revision; +}; + +#define MXL862XX_FW_VER(maj, min, rev) \ + (((u32)(maj) << 24) | ((u32)(min) << 16) | (rev)) +#define MXL862XX_FW_VER_MIN(priv, maj, min, rev) \ + (MXL862XX_FW_VER((priv)->fw_version.major, (priv)->fw_version.minor, \ + (priv)->fw_version.revision) >=3D \ + MXL862XX_FW_VER(maj, min, rev)) + /* Bit indices for struct mxl862xx_priv::flags */ #define MXL862XX_FLAG_CRC_ERR 0 #define MXL862XX_FLAG_WORK_STOPPED 1 @@ -258,6 +278,8 @@ struct mxl862xx_port { * @drop_meter: index of the single shared zero-rate firmware meter * used to unconditionally drop traffic (used to block * flooding) + * @fw_version: cached firmware version, populated at probe and + * compared with MXL862XX_FW_VER_MIN() * @ports: per-port state, indexed by switch port number * @bridges: maps DSA bridge number to firmware bridge ID; * zero means no firmware bridge allocated for that @@ -275,6 +297,7 @@ struct mxl862xx_priv { struct work_struct crc_err_work; unsigned long flags; u16 drop_meter; + struct mxl862xx_fw_version fw_version; struct mxl862xx_port ports[MXL862XX_MAX_PORTS]; u16 bridges[MXL862XX_MAX_BRIDGES + 1]; u16 evlan_ingress_size; --=20 2.54.0 From nobody Mon Jun 8 19:46:26 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E09C62D6E64; Wed, 27 May 2026 02:48:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850099; cv=none; b=J5UsBDULi4yuRgJ7oBF9Bh2S4hiOOrLp0SefebCbPX06PxGt/cp4tLFX3H0lEIl0W9YHui4+PpY/Z/zJishA1CLIuMWsLiBXP6r7DGyUht4avHzI91qMhy1gCnlscl0xwIC/8/fMy3PjTOeraCI/HEXKnfVz6pQR1JlYuaST72U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850099; c=relaxed/simple; bh=wLeW9FnnQvyy/gxSnYr0f88az2252wM89IuvOK/QWl0=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=fREYHSgNcU0++yJWbNLNBpKD0FtIu0XLEKorQzM+0R0VLmAc28xE7glQTAdv7pedwyYouiLeX6e+JMyrCnHYvjHxBY5HN3vi0S+VwYGCZtu8rOoYDux6zJS3VXUpNIeoBvnhjOci6YeffHoz7R8GTnYljA7cNTObww7NEuHkSRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1wS4Ja-000000006yd-3hMi; Wed, 27 May 2026 02:48:14 +0000 Date: Wed, 27 May 2026 03:48:12 +0100 From: Daniel Golle To: John Crispin , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v3 2/4] net: dsa: mxl862xx: move phylink stubs to mxl862xx-phylink.c Message-ID: <826dfb92350e4ac48e1ac89c9dea4e04a4c491bc.1779849840.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the phylink MAC operations and get_caps callback from mxl862xx.c into a dedicated mxl862xx-phylink.c file. This prepares for the SerDes PCS implementation which adds substantial phylink/PCS code -- keeping it in a separate file avoids function-position churn in the main driver file. No functional change. Signed-off-by: Daniel Golle Reviewed-by: Maxime Chevallier --- v3: no changes v2: no changes drivers/net/dsa/mxl862xx/Makefile | 2 +- drivers/net/dsa/mxl862xx/mxl862xx-phylink.c | 51 +++++++++++++++++++++ drivers/net/dsa/mxl862xx/mxl862xx-phylink.h | 14 ++++++ drivers/net/dsa/mxl862xx/mxl862xx.c | 38 +-------------- 4 files changed, 67 insertions(+), 38 deletions(-) create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-phylink.c create mode 100644 drivers/net/dsa/mxl862xx/mxl862xx-phylink.h diff --git a/drivers/net/dsa/mxl862xx/Makefile b/drivers/net/dsa/mxl862xx/M= akefile index d23dd3cd511d..a7be0e6669df 100644 --- a/drivers/net/dsa/mxl862xx/Makefile +++ b/drivers/net/dsa/mxl862xx/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_MXL862) +=3D mxl862xx_dsa.o -mxl862xx_dsa-y :=3D mxl862xx.o mxl862xx-host.o +mxl862xx_dsa-y :=3D mxl862xx.o mxl862xx-host.o mxl862xx-phylink.o diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-phylink.c b/drivers/net/dsa/= mxl862xx/mxl862xx-phylink.c new file mode 100644 index 000000000000..f17c429d1f1d --- /dev/null +++ b/drivers/net/dsa/mxl862xx/mxl862xx-phylink.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Phylink and PCS support for MaxLinear MxL862xx switch family + * + * Copyright (C) 2024 MaxLinear Inc. + * Copyright (C) 2025 John Crispin + * Copyright (C) 2025 Daniel Golle + */ + +#include +#include + +#include "mxl862xx.h" +#include "mxl862xx-phylink.h" + +void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | + MAC_100 | MAC_1000 | MAC_2500FD; + + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); +} + +static void mxl862xx_phylink_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +{ +} + +static void mxl862xx_phylink_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ +} + +static void mxl862xx_phylink_mac_link_up(struct phylink_config *config, + struct phy_device *phydev, + unsigned int mode, + phy_interface_t interface, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ +} + +const struct phylink_mac_ops mxl862xx_phylink_mac_ops =3D { + .mac_config =3D mxl862xx_phylink_mac_config, + .mac_link_down =3D mxl862xx_phylink_mac_link_down, + .mac_link_up =3D mxl862xx_phylink_mac_link_up, +}; diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-phylink.h b/drivers/net/dsa/= mxl862xx/mxl862xx-phylink.h new file mode 100644 index 000000000000..c3d5215bdf60 --- /dev/null +++ b/drivers/net/dsa/mxl862xx/mxl862xx-phylink.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MXL862XX_PHYLINK_H +#define __MXL862XX_PHYLINK_H + +#include + +#include "mxl862xx.h" + +extern const struct phylink_mac_ops mxl862xx_phylink_mac_ops; +void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config); + +#endif /* __MXL862XX_PHYLINK_H */ diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.c b/drivers/net/dsa/mxl862xx= /mxl862xx.c index 2f22adedfbf6..a193f3c07d35 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx.c +++ b/drivers/net/dsa/mxl862xx/mxl862xx.c @@ -22,6 +22,7 @@ #include "mxl862xx-api.h" #include "mxl862xx-cmd.h" #include "mxl862xx-host.h" +#include "mxl862xx-phylink.h" =20 #define MXL862XX_API_WRITE(dev, cmd, data) \ mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), false, false) @@ -1424,16 +1425,6 @@ static void mxl862xx_port_teardown(struct dsa_switch= *ds, int port) priv->ports[port].setup_done =3D false; } =20 -static void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port, - struct phylink_config *config) -{ - config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | - MAC_100 | MAC_1000 | MAC_2500FD; - - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); -} - static int mxl862xx_get_fid(struct dsa_switch *ds, struct dsa_db db) { struct mxl862xx_priv *priv =3D ds->priv; @@ -2099,33 +2090,6 @@ static const struct dsa_switch_ops mxl862xx_switch_o= ps =3D { .get_stats64 =3D mxl862xx_get_stats64, }; =20 -static void mxl862xx_phylink_mac_config(struct phylink_config *config, - unsigned int mode, - const struct phylink_link_state *state) -{ -} - -static void mxl862xx_phylink_mac_link_down(struct phylink_config *config, - unsigned int mode, - phy_interface_t interface) -{ -} - -static void mxl862xx_phylink_mac_link_up(struct phylink_config *config, - struct phy_device *phydev, - unsigned int mode, - phy_interface_t interface, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ -} - -static const struct phylink_mac_ops mxl862xx_phylink_mac_ops =3D { - .mac_config =3D mxl862xx_phylink_mac_config, - .mac_link_down =3D mxl862xx_phylink_mac_link_down, - .mac_link_up =3D mxl862xx_phylink_mac_link_up, -}; - static int mxl862xx_probe(struct mdio_device *mdiodev) { struct device *dev =3D &mdiodev->dev; --=20 2.54.0 From nobody Mon Jun 8 19:46:26 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1928E2D6E64; Wed, 27 May 2026 02:48:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850113; cv=none; b=O7QrX6DJzNWIbXG6gkjhCi5CtlqRwdggHy3mPZ4CSebUHy5KqUtFKKLbD1hMQ+sowvb2FOUxoHhkgaQwyXSA2I+Lj+O7eWeUtvFzdf3zR00fsW7c9Mq/N+r8qeRFmq4AHfubD64B1lGkYRFIHDS+pLNQ+QlT1d/49eFLuKSSghs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850113; c=relaxed/simple; bh=mc1m8GBXAR45F8DczIz1DCns2rDHOv6U0tnNXZnS+a8=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=HS240GkKwn2SvfC+O5iU4D6AfC01d64Ac+sFnpLTsgMda7p1+qUN1LarcBor4yzS4axiudXkjZoL4Twmet5+NK/YlMNCJhtC8H4TGrzhKUx4AhhUoFTvPgZZupO3+kJ2OEi5JIh69rw1IYratZ7nAaaqiHt9rNP47cx0VlWc9Pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1wS4Jo-000000006zD-0BkK; Wed, 27 May 2026 02:48:28 +0000 Date: Wed, 27 May 2026 03:48:25 +0100 From: Daniel Golle To: John Crispin , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v3 3/4] net: dsa: mxl862xx: move API macros to mxl862xx-host.h Message-ID: <61254c2a904a6fed8e631d540734cec1a8a68334.1779849840.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the MXL862XX_API_WRITE, MXL862XX_API_READ and MXL862XX_API_READ_QUIET convenience macros from mxl862xx.c to mxl862xx-host.h next to the mxl862xx_api_wrap() prototype they wrap. This makes them available to other compilation units that include mxl862xx-host.h, which is needed once the SerDes PCS code in mxl862xx-phylink.c also calls firmware commands. No functional change. Signed-off-by: Daniel Golle Reviewed-by: Maxime Chevallier --- v3: no changes v2: no changes drivers/net/dsa/mxl862xx/mxl862xx-host.h | 8 ++++++++ drivers/net/dsa/mxl862xx/mxl862xx.c | 7 ------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-host.h b/drivers/net/dsa/mxl= 862xx/mxl862xx-host.h index 84512a30bc18..66d6ae198aff 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx-host.h +++ b/drivers/net/dsa/mxl862xx/mxl862xx-host.h @@ -9,6 +9,14 @@ void mxl862xx_host_init(struct mxl862xx_priv *priv); void mxl862xx_host_shutdown(struct mxl862xx_priv *priv); int mxl862xx_api_wrap(struct mxl862xx_priv *priv, u16 cmd, void *data, u16= size, bool read, bool quiet); + +#define MXL862XX_API_WRITE(dev, cmd, data) \ + mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), false, false) +#define MXL862XX_API_READ(dev, cmd, data) \ + mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), true, false) +#define MXL862XX_API_READ_QUIET(dev, cmd, data) \ + mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), true, true) + int mxl862xx_reset(struct mxl862xx_priv *priv); =20 #endif /* __MXL862XX_HOST_H */ diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.c b/drivers/net/dsa/mxl862xx= /mxl862xx.c index a193f3c07d35..0b1a23364eb5 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx.c +++ b/drivers/net/dsa/mxl862xx/mxl862xx.c @@ -24,13 +24,6 @@ #include "mxl862xx-host.h" #include "mxl862xx-phylink.h" =20 -#define MXL862XX_API_WRITE(dev, cmd, data) \ - mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), false, false) -#define MXL862XX_API_READ(dev, cmd, data) \ - mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), true, false) -#define MXL862XX_API_READ_QUIET(dev, cmd, data) \ - mxl862xx_api_wrap(dev, cmd, &(data), sizeof((data)), true, true) - /* Polling interval for RMON counter accumulation. At 2.5 Gbps with * minimum-size (64-byte) frames, a 32-bit packet counter wraps in ~880s. * 2s gives a comfortable margin. --=20 2.54.0 From nobody Mon Jun 8 19:46:26 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CA3B24A069; Wed, 27 May 2026 02:48:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850132; cv=none; b=VkQNHvA76te7L/QhuQYVqeceaPPB6QKz72XPnsQoWAuKakWpp0U8+RtYj/0E+HiqteT9XtfhyEmNKGOClPK5+WTFSdIrL+U+nLvef7zNYqoqLblnBZNPDao6n+sKoCMzXkBPHJH9/cV6wPy2oyc/ygoKXLhETjzNWmrM/qQT7VQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779850132; c=relaxed/simple; bh=1FVTGt+iHwwCACZllNuEtT03SMbmnbt1kvGDm7uscgU=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=inxNbUCIuCdY+qZ5wVZ/Q0CR7HoqzbIcWc7N1mNxrLVcUzsQS+65JZM8eXJ37IuHgTh5mzBJekM0M+pSA6ALozPQSYvUC7UuDQrDPCKOVsXGQ5q76wyanPhXRpbv/15btIwR1xsCjTChoWK6TO/PaBR8S89UgSAIrimsdAZGvG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1wS4K6-000000006zQ-3Jeu; Wed, 27 May 2026 02:48:46 +0000 Date: Wed, 27 May 2026 03:48:44 +0100 From: Daniel Golle To: John Crispin , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v3 4/4] net: dsa: mxl862xx: add support for SerDes ports Message-ID: <3d738c7bf198f9c3ea84e1edf551d6d9a1a647ce.1779849840.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MxL862xx has two XPCS/SerDes interfaces (XPCS0 for ports 9-12, XPCS1 for ports 13-16). Each can operate in various single-lane modes (SGMII, 1000Base-X, 2500Base-X, 10GBase-R, 10GBase-KR, USXGMII) or as QSGMII or 10G_QXGMII providing four sub-ports per interface. Implement phylink PCS operations using the firmware's XPCS API: - pcs_config: configure negotiation mode and CL37/SGMII advertising. - pcs_get_state: read link state and the link-partner ability word from firmware and decode using phylink's standard CL37, SGMII, and USXGMII decoders. - pcs_an_restart: restart CL37 or CL73 auto-negotiation. - pcs_link_up: force speed/duplex for SGMII. - pcs_inband_caps: report per-mode in-band status capabilities. Register a PCS instance for each SerDes interface and QSGMII/10G_QXGMII sub-ports during setup. Advertise the supported interface modes in phylink_get_caps based on port number. Lacking support for expressing PHY-side role modes in Linux only the MAC-side of SGMII, QSGMII, USXGMII and 10G_QXGMII are implemented for now. Signed-off-by: Daniel Golle --- v3: v2: * add __{LE,BE}_BITFIELD layouts to ABI structs * per-sub-port QSGMII AN restart via usx_subport / usx_lane_mode * shared-SerDes refcount in pcs_disable via per-XPCS slot bitmap * let every sub-port call pcs_config * cache phy_interface_t instead of firmware type * skip pcs_link_up when inband-AN enabled * gate phylink_get_caps SerDes modes on same FW version as select_pcs * interpret xpcs_pcs_cfg.result as signed (s16) * drop dead MXL862XX_PCS_PORT macro * drop misleading "downshift detection" line from commit message drivers/net/dsa/mxl862xx/mxl862xx-api.h | 302 +++++++++++++++++ drivers/net/dsa/mxl862xx/mxl862xx-cmd.h | 9 + drivers/net/dsa/mxl862xx/mxl862xx-phylink.c | 358 +++++++++++++++++++- drivers/net/dsa/mxl862xx/mxl862xx-phylink.h | 7 + drivers/net/dsa/mxl862xx/mxl862xx.c | 6 +- drivers/net/dsa/mxl862xx/mxl862xx.h | 31 ++ 6 files changed, 710 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-api.h b/drivers/net/dsa/mxl8= 62xx/mxl862xx-api.h index fb21ddc1bf1c..aef1a2f702b5 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx-api.h +++ b/drivers/net/dsa/mxl862xx/mxl862xx-api.h @@ -1366,4 +1366,306 @@ struct mxl862xx_rmon_port_cnt { __le64 tx_good_bytes; } __packed; =20 +/** + * enum mxl862xx_xpcs_if_mode - XPCS interface mode + * @MXL862XX_XPCS_IF_SGMII: SGMII + * @MXL862XX_XPCS_IF_1000BASEX: 1000BASE-X + * @MXL862XX_XPCS_IF_2500BASEX: 2500BASE-X + * @MXL862XX_XPCS_IF_USXGMII: USXGMII (single or quad) + * @MXL862XX_XPCS_IF_10GBASER: 10GBASE-R + * @MXL862XX_XPCS_IF_10GKR: 10GBASE-KR + * @MXL862XX_XPCS_IF_5GBASER: 5GBASE-R + * @MXL862XX_XPCS_IF_QSGMII: QSGMII + */ +enum mxl862xx_xpcs_if_mode { + MXL862XX_XPCS_IF_SGMII =3D 0, + MXL862XX_XPCS_IF_1000BASEX =3D 1, + MXL862XX_XPCS_IF_2500BASEX =3D 2, + MXL862XX_XPCS_IF_USXGMII =3D 3, + MXL862XX_XPCS_IF_10GBASER =3D 4, + MXL862XX_XPCS_IF_10GKR =3D 5, + MXL862XX_XPCS_IF_5GBASER =3D 6, + MXL862XX_XPCS_IF_QSGMII =3D 7, +}; + +/** + * enum mxl862xx_xpcs_neg_mode - PCS negotiation mode + * @MXL862XX_XPCS_NEG_NONE: no inband negotiation + * @MXL862XX_XPCS_NEG_INBAND_AN_OFF: inband selected but AN disabled + * @MXL862XX_XPCS_NEG_INBAND_AN_ON: inband with AN enabled + */ +enum mxl862xx_xpcs_neg_mode { + MXL862XX_XPCS_NEG_NONE =3D 0, + MXL862XX_XPCS_NEG_INBAND_AN_OFF =3D 1, + MXL862XX_XPCS_NEG_INBAND_AN_ON =3D 2, +}; + +/** + * enum mxl862xx_xpcs_role - PCS protocol role + * @MXL862XX_XPCS_ROLE_MAC: local end is MAC side (TX_CONFIG =3D 0) + * @MXL862XX_XPCS_ROLE_PHY: local end is PHY side (TX_CONFIG =3D 1) + * + * Selects the role the XPCS plays in protocols that have an asymmetric + * AN code word (Cisco SGMII / QSGMII / USXGMII). Drives + * VR_MII_AN_CTRL.TX_CONFIG: 0 means the local end receives the partner's + * AN word, 1 means it sources one. Ignored for symmetric protocols + * (1000BASE-X, 2500BASE-X, 10GBASE-R/KR). + */ +enum mxl862xx_xpcs_role { + MXL862XX_XPCS_ROLE_MAC =3D 0, + MXL862XX_XPCS_ROLE_PHY =3D 1, +}; + +/** + * enum mxl862xx_xpcs_usx_lane_mode - USXGMII lane mode + * @MXL862XX_XPCS_USX_SINGLE: single USXGMII lane + * @MXL862XX_XPCS_USX_QUAD: quad USXGMII (4 ports per lane) + */ +enum mxl862xx_xpcs_usx_lane_mode { + MXL862XX_XPCS_USX_SINGLE =3D 0, + MXL862XX_XPCS_USX_QUAD =3D 1, +}; + +/** + * union mxl862xx_xpcs_an_word - XPCS AN code word, tagged by interface mo= de + * @cl37: 16-bit base-page word exchanged over the CL37 hardware AN path + * (SR_MII_AN_ADV on write, SR_MII_LP_BABL on read). Carries the + * 802.3 CL37 base page for 1000BASE-X/2500BASE-X and the Cisco + * SGMII config word for SGMII/QSGMII. + * @usx: USXGMII 16-bit AN code word, MDIO_USXGMII_* layout + * @cl73: CL73 48-bit base page (10GBASE-KR), three 16-bit registers per + * 802.3 Annex 28C + * @cl73.adv1: CL73 SR_AN_ADV1 / SR_AN_LP_ABL1 + * @cl73.adv2: CL73 SR_AN_ADV2 / SR_AN_LP_ABL2 + * @cl73.adv3: CL73 SR_AN_ADV3 / SR_AN_LP_ABL3 + * + * The host picks the right member based on the interface field of the + * surrounding struct (and, for the asymmetric protocols, on the role). + */ +union mxl862xx_xpcs_an_word { + __le16 cl37; + __le16 usx; + struct { + __le16 adv1; + __le16 adv2; + __le16 adv3; + } cl73; +} __packed; + +/** + * enum mxl862xx_xpcs_duplex - PCS duplex mode + * @MXL862XX_XPCS_DUPLEX_HALF: half duplex + * @MXL862XX_XPCS_DUPLEX_FULL: full duplex + */ +enum mxl862xx_xpcs_duplex { + MXL862XX_XPCS_DUPLEX_HALF =3D 0, + MXL862XX_XPCS_DUPLEX_FULL =3D 1, +}; + +/** + * enum mxl862xx_xpcs_loopback_mode - XPCS loopback mode + * @MXL862XX_XPCS_LB_DISABLE: disable all loopback + * @MXL862XX_XPCS_LB_PCS_SERIAL: PCS TX-to-RX serial loopback + * @MXL862XX_XPCS_LB_PCS_PARALLEL: PCS RX-to-TX parallel loopback + * @MXL862XX_XPCS_LB_PMA_SERIAL: PMA TX-to-RX serial loopback + * @MXL862XX_XPCS_LB_PMA_PARALLEL: PMA RX-to-TX parallel loopback + */ +enum mxl862xx_xpcs_loopback_mode { + MXL862XX_XPCS_LB_DISABLE =3D 0, + MXL862XX_XPCS_LB_PCS_SERIAL =3D 1, + MXL862XX_XPCS_LB_PCS_PARALLEL =3D 2, + MXL862XX_XPCS_LB_PMA_SERIAL =3D 3, + MXL862XX_XPCS_LB_PMA_PARALLEL =3D 4, +}; + +/** + * struct mxl862xx_xpcs_pcs_cfg - PCS configuration parameters + * @port_id: XPCS port index (0-3) + * @interface: PCS interface mode. See &enum mxl862xx_xpcs_if_mode + * @neg_mode: PCS negotiation mode. See &enum mxl862xx_xpcs_neg_mode + * @permit_pause: Allow pause to MAC + * @usx_lane_mode: USXGMII lane mode. + * See &enum mxl862xx_xpcs_usx_lane_mode + * @role: PCS protocol role. See &enum mxl862xx_xpcs_role + * @usx_subport: Sub-port (0-3) within the XPCS. Used by the firmware + * to set MAC pause per sub-port; ignored for the + * XPCS-wide bringup, which is idempotent across slots. + * @advertising: AN code word the local end transmits. The active union + * member is selected by @interface (and, for the asymmetric + * protocols, by @role). Ignored when the local end does + * not transmit an AN word (role=3DMAC for SGMII/QSGMII/ + * USXGMII, 10GBASE-R, 5GBASE-R) or when @neg_mode is not + * INBAND_AN_ON. Pass all-zero to keep the firmware default + * advertisement. + * @result: Firmware result. >0 means the host must follow with an AN + * restart, 0 means no host follow-up is needed, <0 is an errno. + */ +struct mxl862xx_xpcs_pcs_cfg { +#ifdef __LITTLE_ENDIAN_BITFIELD + u8 port_id:2; + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 neg_mode:2; /* enum mxl862xx_xpcs_neg_mode */ + u8 permit_pause:1; + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 role:1; /* enum mxl862xx_xpcs_role */ + u8 usx_subport:2; +#elif defined(__BIG_ENDIAN_BITFIELD) + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 port_id:2; + u8 usx_subport:2; + u8 role:1; /* enum mxl862xx_xpcs_role */ + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 permit_pause:1; + u8 neg_mode:2; /* enum mxl862xx_xpcs_neg_mode */ +#else +#error "Unknown bitfield endianness" +#endif + union mxl862xx_xpcs_an_word advertising; + __le16 result; +} __packed; + +/** + * struct mxl862xx_xpcs_pcs_state - PCS link state + * @port_id: XPCS port index (0-3) (input) + * @interface: PCS interface mode (input). + * See &enum mxl862xx_xpcs_if_mode + * @usx_lane_mode: USX lane mode (input) + * @usx_subport: USX sub-port 0-3 (input) + * @link: Link up (1) / down (0) (output) + * @an_complete: Auto-negotiation complete (output) + * @duplex: Duplex mode (output). See &enum mxl862xx_xpcs_duplex + * @pcs_fault: PCS fault (output) + * @pause: Pause negotiation result, bit 0 symmetric, bit 1 asymmetric + * (output) + * @lp_eee_cap: Link partner supports EEE (output) + * @lp_eee_cs_cap: Link partner supports EEE clock-stop (output) + * @__rsv: reserved + * @__pad: padding + * @speed: Resolved speed in Mbit/s (output) + * @lpa: Link partner ability word (output). Same union as + * &union mxl862xx_xpcs_an_word; the host picks the member based on + * @interface. + */ +struct mxl862xx_xpcs_pcs_state { +#ifdef __LITTLE_ENDIAN_BITFIELD + u8 port_id:2; + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 usx_subport:2; + u8 link:1; + u8 an_complete:1; + u8 duplex:1; /* enum mxl862xx_xpcs_duplex */ + u8 pcs_fault:1; + u8 pause:2; + u8 lp_eee_cap:1; + u8 lp_eee_cs_cap:1; + u8 __rsv:4; +#elif defined(__BIG_ENDIAN_BITFIELD) + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 port_id:2; + u8 pcs_fault:1; + u8 duplex:1; /* enum mxl862xx_xpcs_duplex */ + u8 an_complete:1; + u8 link:1; + u8 usx_subport:2; + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 __rsv:4; + u8 lp_eee_cs_cap:1; + u8 lp_eee_cap:1; + u8 pause:2; +#else +#error "Unknown bitfield endianness" +#endif + u8 __pad; + __le16 speed; /* Mbit/s */ + union mxl862xx_xpcs_an_word lpa; +} __packed; + +/** + * struct mxl862xx_xpcs_pcs_disable - PCS disable parameters + * @port_id: XPCS port index + * @__pad: padding + * @result: Firmware result. 0 on success, <0 on error. + * + * Asserts IDDQ + PHY + XPCS resets to power down the SERDES when the + * port is admin-down or no module is plugged in. The next PCS config + * implicitly powers it back up and reprograms the desired interface. + */ +struct mxl862xx_xpcs_pcs_disable { + u8 port_id; + u8 __pad; + __le16 result; +} __packed; + +/** + * struct mxl862xx_xpcs_an_restart - AN restart parameters + * @port_id: XPCS port index (0-3) + * @interface: PCS interface mode. See &enum mxl862xx_xpcs_if_mode + * @usx_lane_mode: USX lane mode + * @usx_subport: Sub-port (0-3) within the XPCS. Selects the lane + * whose AN is restarted for QSGMII and QUSXGMII; + * ignored by single-lane modes. + * @__rsv: reserved + * @result: Firmware result. 0 on success, <0 on error. + * + * Restarts auto-negotiation on a single sub-port of the XPCS. The + * SERDES must already be configured. + */ +struct mxl862xx_xpcs_an_restart { +#ifdef __LITTLE_ENDIAN_BITFIELD + u8 port_id:2; + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 usx_subport:2; + u8 __rsv:4; +#elif defined(__BIG_ENDIAN_BITFIELD) + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 port_id:2; + u8 __rsv:4; + u8 usx_subport:2; + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ +#else +#error "Unknown bitfield endianness" +#endif + __le16 result; +} __packed; + +/** + * struct mxl862xx_xpcs_pcs_link_up - PCS link-up parameters + * @port_id: XPCS port index (0-3) + * @interface: PCS interface mode. See &enum mxl862xx_xpcs_if_mode + * @duplex: Duplex mode. See &enum mxl862xx_xpcs_duplex + * @usx_lane_mode: USX lane mode (USXGMII only; ignored otherwise). + * See &enum mxl862xx_xpcs_usx_lane_mode + * @usx_subport: USX sub-port 0-3 (QUSXGMII only; ignored otherwise) + * @__rsv0: reserved + * @speed: Resolved speed in Mbit/s + * @result: Firmware result. 0 on success, <0 is errno. + * + * Called once per link-up event after the host has resolved the + * line-side speed/duplex (from the PHY's read_status, from a preceding + * PCS get-state, or from a fixed-link description). + */ +struct mxl862xx_xpcs_pcs_link_up { +#ifdef __LITTLE_ENDIAN_BITFIELD + u8 port_id:2; + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 duplex:1; /* enum mxl862xx_xpcs_duplex */ + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 usx_subport:2; + u8 __rsv0:3; +#elif defined(__BIG_ENDIAN_BITFIELD) + u8 interface:6; /* enum mxl862xx_xpcs_if_mode */ + u8 port_id:2; + u8 __rsv0:3; + u8 usx_subport:2; + u8 usx_lane_mode:2; /* enum mxl862xx_xpcs_usx_lane_mode */ + u8 duplex:1; /* enum mxl862xx_xpcs_duplex */ +#else +#error "Unknown bitfield endianness" +#endif + __le16 speed; /* Mbit/s */ + __le16 result; +} __packed; + #endif /* __MXL862XX_API_H */ diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h b/drivers/net/dsa/mxl8= 62xx/mxl862xx-cmd.h index f1ea40aa7ea0..c87a955c13c4 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h +++ b/drivers/net/dsa/mxl862xx/mxl862xx-cmd.h @@ -24,6 +24,7 @@ #define MXL862XX_SS_MAGIC 0x1600 #define GPY_GPY2XX_MAGIC 0x1800 #define SYS_MISC_MAGIC 0x1900 +#define MXL862XX_XPCS_MAGIC 0x1a00 =20 #define MXL862XX_COMMON_CFGGET (MXL862XX_COMMON_MAGIC + 0x9) #define MXL862XX_COMMON_CFGSET (MXL862XX_COMMON_MAGIC + 0xa) @@ -71,6 +72,14 @@ =20 #define SYS_MISC_FW_VERSION (SYS_MISC_MAGIC + 0x2) =20 +#define MXL862XX_XPCS_PCS_CONFIG (MXL862XX_XPCS_MAGIC + 0x1) +#define MXL862XX_XPCS_PCS_GET_STATE (MXL862XX_XPCS_MAGIC + 0x2) +#define MXL862XX_XPCS_PCS_DISABLE (MXL862XX_XPCS_MAGIC + 0x4) +#define MXL862XX_XPCS_AN_RESTART (MXL862XX_XPCS_MAGIC + 0x5) +#define MXL862XX_XPCS_PCS_LINK_UP (MXL862XX_XPCS_MAGIC + 0x7) +#define MXL862XX_XPCS_LOOPBACK (MXL862XX_XPCS_MAGIC + 0x8) +#define MXL862XX_XPCS_RESET (MXL862XX_XPCS_MAGIC + 0x9) + #define MMD_API_MAXIMUM_ID 0x7fff =20 #endif /* __MXL862XX_CMD_H */ diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-phylink.c b/drivers/net/dsa/= mxl862xx/mxl862xx-phylink.c index f17c429d1f1d..4656947b83e0 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx-phylink.c +++ b/drivers/net/dsa/mxl862xx/mxl862xx-phylink.c @@ -7,20 +7,373 @@ * Copyright (C) 2025 Daniel Golle */ =20 +#include #include #include =20 #include "mxl862xx.h" +#include "mxl862xx-api.h" +#include "mxl862xx-cmd.h" +#include "mxl862xx-host.h" #include "mxl862xx-phylink.h" =20 void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { + struct mxl862xx_priv *priv =3D ds->priv; + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; =20 - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); + switch (port) { + case 1 ... 8: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; + case 9: + case 13: + if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 84)) + break; + __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GKR, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces); + fallthrough; + case 10 ... 12: + case 14 ... 16: + if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 84)) + break; + __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, config->supported_interfaces); + + break; + default: + break; + } + + if (port =3D=3D 9 || port =3D=3D 13) + config->mac_capabilities |=3D MAC_10000FD | MAC_5000FD; +} + +static struct mxl862xx_pcs *pcs_to_mxl862xx_pcs(struct phylink_pcs *pcs) +{ + return container_of(pcs, struct mxl862xx_pcs, pcs); +} + +static int mxl862xx_xpcs_if_mode(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + return MXL862XX_XPCS_IF_SGMII; + case PHY_INTERFACE_MODE_QSGMII: + return MXL862XX_XPCS_IF_QSGMII; + case PHY_INTERFACE_MODE_1000BASEX: + return MXL862XX_XPCS_IF_1000BASEX; + case PHY_INTERFACE_MODE_2500BASEX: + return MXL862XX_XPCS_IF_2500BASEX; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: + return MXL862XX_XPCS_IF_USXGMII; + case PHY_INTERFACE_MODE_10GBASER: + return MXL862XX_XPCS_IF_10GBASER; + case PHY_INTERFACE_MODE_10GKR: + return MXL862XX_XPCS_IF_10GKR; + default: + return -EINVAL; + } +} + +static int mxl862xx_xpcs_neg_mode(unsigned int neg_mode) +{ + if (!(neg_mode & PHYLINK_PCS_NEG_INBAND)) + return MXL862XX_XPCS_NEG_NONE; + if (neg_mode & PHYLINK_PCS_NEG_ENABLED) + return MXL862XX_XPCS_NEG_INBAND_AN_ON; + return MXL862XX_XPCS_NEG_INBAND_AN_OFF; +} + +static int mxl862xx_pcs_enable(struct phylink_pcs *pcs) +{ + struct mxl862xx_pcs *mpcs =3D pcs_to_mxl862xx_pcs(pcs); + + /* Bringup is done idempotently by pcs_config; just account this + * sub-port so pcs_disable powers the shared XPCS down only after + * the last sub-port has been released. + */ + atomic_inc(&mpcs->priv->serdes_refcount[mpcs->serdes_id]); + + return 0; +} + +static void mxl862xx_pcs_disable(struct phylink_pcs *pcs) +{ + struct mxl862xx_pcs *mpcs =3D pcs_to_mxl862xx_pcs(pcs); + struct mxl862xx_xpcs_pcs_disable dis =3D {}; + struct mxl862xx_priv *priv =3D mpcs->priv; + + /* The SerDes is shared across QSGMII/QUSXGMII sub-ports; only + * power it down once the last active sub-port goes away. + */ + if (!atomic_dec_and_test(&priv->serdes_refcount[mpcs->serdes_id])) + return; + + dis.port_id =3D mpcs->serdes_id; + + MXL862XX_API_WRITE(priv, MXL862XX_XPCS_PCS_DISABLE, dis); +} + +/* The XPCS firmware reports failures in the result field using its own + * libc errno values; ENOTSUP (134) in particular has no kernel errno. + * Translate the codes the firmware can actually return. + */ +static int mxl862xx_xpcs_errno(int result) +{ + switch (result) { + case -5: /* firmware -EIO */ + return -EIO; + case -134: /* firmware -ENOTSUP */ + return -EOPNOTSUPP; + default: /* firmware -EINVAL and anything unexpected */ + return -EINVAL; + } +} + +static int mxl862xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_m= ode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct mxl862xx_pcs *mpcs =3D pcs_to_mxl862xx_pcs(pcs); + struct mxl862xx_priv *priv =3D mpcs->priv; + struct mxl862xx_xpcs_pcs_cfg cfg =3D {}; + int if_mode, ret, adv; + + if_mode =3D mxl862xx_xpcs_if_mode(interface); + if (if_mode < 0) { + dev_err(priv->ds->dev, "unsupported interface: %s\n", + phy_modes(interface)); + return if_mode; + } + + /* The XPCS bringup is per-instance and idempotent in the + * firmware: every QSGMII/QUSXGMII sub-port may call pcs_config + * and the firmware will skip the bringup if the requested mode + * matches the cached one, then update MAC pause for the + * sub-port indicated by @usx_subport. + */ + cfg.port_id =3D mpcs->serdes_id; + cfg.usx_subport =3D mpcs->slot; + cfg.usx_lane_mode =3D (interface =3D=3D PHY_INTERFACE_MODE_10G_QXGMII) ? + MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE; + cfg.interface =3D if_mode; + cfg.neg_mode =3D mxl862xx_xpcs_neg_mode(neg_mode); + cfg.role =3D MXL862XX_XPCS_ROLE_MAC; + cfg.permit_pause =3D permit_pause_to_mac ? 1 : 0; + + if (neg_mode & PHYLINK_PCS_NEG_INBAND) { + adv =3D phylink_mii_c22_pcs_encode_advertisement(interface, + advertising); + if (adv >=3D 0) + cfg.advertising.cl37 =3D cpu_to_le16(adv); + } + + ret =3D MXL862XX_API_READ(priv, MXL862XX_XPCS_PCS_CONFIG, cfg); + if (ret) + return ret; + + ret =3D (s16)le16_to_cpu(cfg.result); + if (ret < 0) + return mxl862xx_xpcs_errno(ret); + + mpcs->interface =3D interface; + return ret > 0 ? 1 : 0; +} + +static void mxl862xx_pcs_get_state(struct phylink_pcs *pcs, + unsigned int neg_mode, + struct phylink_link_state *state) +{ + struct mxl862xx_pcs *mpcs =3D pcs_to_mxl862xx_pcs(pcs); + struct mxl862xx_priv *priv =3D mpcs->priv; + struct mxl862xx_xpcs_pcs_state st =3D {}; + int if_mode, ret; + u16 bmsr; + + if_mode =3D mxl862xx_xpcs_if_mode(state->interface); + if (if_mode < 0) + return; + + st.port_id =3D mpcs->serdes_id; + st.interface =3D if_mode; + st.usx_subport =3D mpcs->slot; + st.usx_lane_mode =3D (state->interface =3D=3D PHY_INTERFACE_MODE_10G_QXGM= II) ? + MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE; + + ret =3D MXL862XX_API_READ(priv, MXL862XX_XPCS_PCS_GET_STATE, st); + if (ret) + return; + + state->link =3D st.link && !st.pcs_fault; + state->an_complete =3D st.an_complete; + + switch (state->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + bmsr =3D (state->link ? BMSR_LSTATUS : 0) | + (state->an_complete ? BMSR_ANEGCOMPLETE : 0); + phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, + le16_to_cpu(st.lpa.cl37)); + break; + + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: + if (state->link) + phylink_decode_usxgmii_word(state, + le16_to_cpu(st.lpa.usx)); + break; + + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_10GKR: + if (state->link) { + state->speed =3D SPEED_10000; + state->duplex =3D DUPLEX_FULL; + } + break; + + default: + state->link =3D false; + break; + } +} + +static void mxl862xx_pcs_an_restart(struct phylink_pcs *pcs) +{ + struct mxl862xx_pcs *mpcs =3D pcs_to_mxl862xx_pcs(pcs); + struct mxl862xx_priv *priv =3D mpcs->priv; + struct mxl862xx_xpcs_an_restart an =3D {}; + int if_mode; + + if_mode =3D mxl862xx_xpcs_if_mode(mpcs->interface); + if (if_mode < 0) + return; + + an.port_id =3D mpcs->serdes_id; + an.interface =3D if_mode; + an.usx_subport =3D mpcs->slot; + an.usx_lane_mode =3D (mpcs->interface =3D=3D PHY_INTERFACE_MODE_10G_QXGMI= I) ? + MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE; + + MXL862XX_API_WRITE(priv, MXL862XX_XPCS_AN_RESTART, an); +} + +static void mxl862xx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg= _mode, + phy_interface_t interface, int speed, + int duplex) +{ + struct mxl862xx_pcs *mpcs =3D pcs_to_mxl862xx_pcs(pcs); + struct mxl862xx_xpcs_pcs_link_up lu =3D {}; + struct mxl862xx_priv *priv =3D mpcs->priv; + int if_mode; + + /* With inband-AN enabled (role=3DMAC), the XPCS auto-resolves + * speed/duplex from the partner's AN word and the firmware + * short-circuits link_up. Skip the firmware round-trip, same + * as pcs-mtk-lynxi. + */ + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) + return; + + if_mode =3D mxl862xx_xpcs_if_mode(interface); + if (if_mode < 0) + return; + + lu.port_id =3D mpcs->serdes_id; + lu.interface =3D if_mode; + lu.usx_subport =3D mpcs->slot; + lu.usx_lane_mode =3D (interface =3D=3D PHY_INTERFACE_MODE_10G_QXGMII) ? + MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE; + lu.duplex =3D (duplex =3D=3D DUPLEX_FULL) ? MXL862XX_XPCS_DUPLEX_FULL : + MXL862XX_XPCS_DUPLEX_HALF; + lu.speed =3D cpu_to_le16(speed); + + MXL862XX_API_WRITE(priv, MXL862XX_XPCS_PCS_LINK_UP, lu); +} + +static unsigned int mxl862xx_pcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: + case PHY_INTERFACE_MODE_10GKR: + return LINK_INBAND_ENABLE; + case PHY_INTERFACE_MODE_10GBASER: + return LINK_INBAND_DISABLE; + default: + return 0; + } +} + +static const struct phylink_pcs_ops mxl862xx_pcs_ops =3D { + .pcs_enable =3D mxl862xx_pcs_enable, + .pcs_disable =3D mxl862xx_pcs_disable, + .pcs_config =3D mxl862xx_pcs_config, + .pcs_get_state =3D mxl862xx_pcs_get_state, + .pcs_an_restart =3D mxl862xx_pcs_an_restart, + .pcs_link_up =3D mxl862xx_pcs_link_up, + .pcs_inband_caps =3D mxl862xx_pcs_inband_caps, +}; + +void mxl862xx_setup_pcs(struct mxl862xx_priv *priv, struct mxl862xx_pcs *p= cs, + int port) +{ + pcs->priv =3D priv; + pcs->serdes_id =3D MXL862XX_SERDES_PORT_ID(port); + pcs->slot =3D MXL862XX_SERDES_SLOT(port); + pcs->interface =3D PHY_INTERFACE_MODE_NA; + + pcs->pcs.ops =3D &mxl862xx_pcs_ops; + pcs->pcs.poll =3D true; + + __set_bit(PHY_INTERFACE_MODE_QSGMII, pcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, pcs->pcs.supported_interfaces); + if (pcs->slot !=3D 0) + return; + + __set_bit(PHY_INTERFACE_MODE_SGMII, pcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, pcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, pcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, pcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GKR, pcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_USXGMII, pcs->pcs.supported_interfaces); +} + +static struct phylink_pcs * +mxl862xx_phylink_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct mxl862xx_priv *priv =3D dp->ds->priv; + int port =3D dp->index; + + if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 84)) + return NULL; + + switch (port) { + case 9 ... 16: + return &priv->serdes_ports[port - 9].pcs; + default: + return NULL; + } } =20 static void mxl862xx_phylink_mac_config(struct phylink_config *config, @@ -48,4 +401,5 @@ const struct phylink_mac_ops mxl862xx_phylink_mac_ops = =3D { .mac_config =3D mxl862xx_phylink_mac_config, .mac_link_down =3D mxl862xx_phylink_mac_link_down, .mac_link_up =3D mxl862xx_phylink_mac_link_up, + .mac_select_pcs =3D mxl862xx_phylink_mac_select_pcs, }; diff --git a/drivers/net/dsa/mxl862xx/mxl862xx-phylink.h b/drivers/net/dsa/= mxl862xx/mxl862xx-phylink.h index c3d5215bdf60..03bb9caad9aa 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx-phylink.h +++ b/drivers/net/dsa/mxl862xx/mxl862xx-phylink.h @@ -7,8 +7,15 @@ =20 #include "mxl862xx.h" =20 +#define MXL862XX_SERDES_SLOT(port) \ + (((port) - MXL862XX_FIRST_SERDES_PORT) % MXL862XX_SERDES_SLOTS) +#define MXL862XX_SERDES_PORT_ID(port) \ + (((port) - MXL862XX_FIRST_SERDES_PORT) / MXL862XX_SERDES_SLOTS) + extern const struct phylink_mac_ops mxl862xx_phylink_mac_ops; void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config); +void mxl862xx_setup_pcs(struct mxl862xx_priv *priv, struct mxl862xx_pcs *p= cs, + int port); =20 #endif /* __MXL862XX_PHYLINK_H */ diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.c b/drivers/net/dsa/mxl862xx= /mxl862xx.c index 0b1a23364eb5..0af41efccbc6 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx.c +++ b/drivers/net/dsa/mxl862xx/mxl862xx.c @@ -622,7 +622,7 @@ static int mxl862xx_setup(struct dsa_switch *ds) int n_user_ports =3D 0, max_vlans; int ingress_finals, vid_rules; struct dsa_port *dp; - int ret; + int ret, i; =20 ret =3D mxl862xx_reset(priv); if (ret) @@ -632,6 +632,10 @@ static int mxl862xx_setup(struct dsa_switch *ds) if (ret) return ret; =20 + for (i =3D 0; i < ARRAY_SIZE(priv->serdes_ports); i++) + mxl862xx_setup_pcs(priv, &priv->serdes_ports[i], + i + MXL862XX_FIRST_SERDES_PORT); + /* Calculate Extended VLAN block sizes. * With VLAN Filter handling VID membership checks: * Ingress: only final catchall rules (PVID insertion, 802.1Q diff --git a/drivers/net/dsa/mxl862xx/mxl862xx.h b/drivers/net/dsa/mxl862xx= /mxl862xx.h index e3db3711b245..3cdb6866cd22 100644 --- a/drivers/net/dsa/mxl862xx/mxl862xx.h +++ b/drivers/net/dsa/mxl862xx/mxl862xx.h @@ -11,6 +11,9 @@ struct mxl862xx_priv; =20 #define MXL862XX_MAX_PORTS 17 +#define MXL862XX_FIRST_SERDES_PORT 9 +#define MXL862XX_SERDES_SLOTS 4 + #define MXL862XX_DEFAULT_BRIDGE 0 #define MXL862XX_MAX_BRIDGES 48 #define MXL862XX_MAX_BRIDGE_PORTS 128 @@ -242,6 +245,26 @@ struct mxl862xx_port { spinlock_t stats_lock; /* protects stats accumulators */ }; =20 +/** + * struct mxl862xx_pcs - link SerDes interfaces to bridge ports + * @pcs: &struct phylink_pcs instance + * @priv: pointer to &struct mxl862xx_priv + * @serdes_id: SerDes instance index (0 or 1) + * @slot: slot within the SerDes (0-3 for QSGMII/QUSXGMII, 0 otherwis= e) + * @interface: cached PHY interface, last value passed to pcs_config(). + * %PHY_INTERFACE_MODE_NA before the first successful + * pcs_config(). Used by pcs_an_restart() to populate the + * firmware command and by pcs_disable() to skip the + * firmware power-down for shared (QSGMII/QUSXGMII) modes. + */ +struct mxl862xx_pcs { + struct phylink_pcs pcs; + struct mxl862xx_priv *priv; + int serdes_id; + int slot; + phy_interface_t interface; +}; + /** * struct mxl862xx_fw_version - firmware version for comparison and display * @major: firmware major version @@ -280,6 +303,12 @@ struct mxl862xx_fw_version { * flooding) * @fw_version: cached firmware version, populated at probe and * compared with MXL862XX_FW_VER_MIN() + * @serdes_ports: SerDes interfaces incl. sub-interfaces in case of + * 10G_QXGMII or QSGMII + * @serdes_refcount: per-XPCS count of sub-ports enabled by phylink; + * pcs_disable powers an XPCS down when the count + * reaches zero. atomic_t so concurrent sub-port + * enable/disable need no extra lock. * @ports: per-port state, indexed by switch port number * @bridges: maps DSA bridge number to firmware bridge ID; * zero means no firmware bridge allocated for that @@ -298,6 +327,8 @@ struct mxl862xx_priv { unsigned long flags; u16 drop_meter; struct mxl862xx_fw_version fw_version; + struct mxl862xx_pcs serdes_ports[8]; + atomic_t serdes_refcount[2]; struct mxl862xx_port ports[MXL862XX_MAX_PORTS]; u16 bridges[MXL862XX_MAX_BRIDGES + 1]; u16 evlan_ingress_size; --=20 2.54.0