From nobody Sun May 24 20:33:09 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010051.outbound.protection.outlook.com [40.93.198.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16A81426EA2; Thu, 21 May 2026 20:34:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779395695; cv=fail; b=M48kvbupa7Q/1N69IWUCiXIKlIIu2ieoBRLxPpF5/brSKcbUW5xSc67PYw3f4H25WdSnmy3ORLLEU+EZB0a4AQslxTIYFhguwd3hSTTzHdKga0cLyijVgEA5KtaY99XycZIMVkYF7sTJxqnGkODHyf18f24G7AeKWRD4NNUXQdM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779395695; c=relaxed/simple; bh=snRoL70ooWR2ZhTkTvoKCAS7KxtDTIY5Prj5eGhwy1I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b+k7xNtqKaM+PyXsa97bcjdC2pZQpIoY88oAbAk+3lxXIV/aFdvNo+XVlIQAhBtmCsLOn83QNjmDaL4zUX0ZljcYoVUfte1gmRnR8BrzODUX+uJkYEUBYn3vYBb8MRPUuk9X3K5XKnPYLpswhq4uUWFWFIz4k/HCWqyhJiVPnxM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=YXnb4hZ4; arc=fail smtp.client-ip=40.93.198.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="YXnb4hZ4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=GbAwJe2hi5zGeS/iddyzDjFrvl1XtFlC8bd1/sfN93cvLAPycUdY5lwLo543XtnAb0itMO0X7IJcWAZIxWyoBgRuJtRy2V0dZxNTRdGBMUsMKGUzHxFjtvxFzg254aHVnlOACICaAaC9XWKan9q1v2klqAqYmzRNrWFwecqDvKfm6BxcepNgHgtvJB+skU1acTSG/sEZXUIhfxTGwf5O+psfhaurDRx/HydDwgJDOV4u3XVea4opgyeHIPfEn9BgCRNSqefigV6PnQfisM57BPCDKCVZKwdwI1Lk0HsOaJooqb1o44PBOJVMOYj+w40aqTE//Ia/tT1J4xfTTe5Wtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Bz9LFpVSBDmQQM6m97pEcPTv5QBlbG4U+sjXAe9f4tQ=; b=hrRkiwEz6l4YbcY1uT4mxpkvmQVPZ2ye9EXcHoHcktLZp0oWuv5edefAjVUrEpMIcfsHGv4/Xw+hNGsyZ7JO3zYCsfgJFSyxaGPwz1IsljQ6K+GUsTMxDTcLuEVCnUfWJ/ImYByX9oL2h5SdTgyMyY6CNnfIcH6KgBoGuU9AZ0GyCamVoJ43HkFvhqjTN1piTtxMokyoSbEmnKKpGEmYeMJZCBN9lIXxG5SF2twpeAxWFUnEDuwJ48LnQz425be3HGGjOsAWGT/i5/32cS4wtPIppD959EYZZOLlwjhDlKcX4JlfBn87bQVp0ioB51Z6sw5a2s6/DEaAXRWq5lxlWg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=huawei.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Bz9LFpVSBDmQQM6m97pEcPTv5QBlbG4U+sjXAe9f4tQ=; b=YXnb4hZ4Cnyqoxjo5eTpNw3dVDnmWWnT8x8g8hB7jPi4XwJqWeOle8OdTyvRSC/abd1EAyayFuLsshlRz9fdcNd8rDz6iLD2aJs7Nw1BtEpQOEaim/aVrdjqFrg7rXniS2nHCtOCWZDRiw3uejI6ZN2u6BoSTByS6LgNzlyulxfJhJWUyjvFGn+irK54/m0iSZuq8ERTT4fyjOPRDpwrwKWME5VpFA0IYxitP232fercfcsXqC8OzAhyChS5AQ3XcCFxD5hOGCxz5vjU8OVOU9fabIBo5tWKJb3pEXRt4V9l0g1gnXi6TbV+zR4iYjaXFJyudcaEY7bqhVKC1+U/fQ== Received: from SJ0PR13CA0192.namprd13.prod.outlook.com (2603:10b6:a03:2c3::17) by LV8PR12MB9084.namprd12.prod.outlook.com (2603:10b6:408:18e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Thu, 21 May 2026 20:34:48 +0000 Received: from SJ1PEPF00001CE4.namprd03.prod.outlook.com (2603:10b6:a03:2c3:cafe::85) by SJ0PR13CA0192.outlook.office365.com (2603:10b6:a03:2c3::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.71.6 via Frontend Transport; Thu, 21 May 2026 20:34:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF00001CE4.mail.protection.outlook.com (10.167.242.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Thu, 21 May 2026 20:34:46 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 21 May 2026 13:34:29 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 21 May 2026 13:34:28 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 21 May 2026 13:34:27 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 1/3] PCI: Add pci_ats_required() for CXL.cache capable devices Date: Thu, 21 May 2026 13:34:20 -0700 Message-ID: <05044d2113e20d81f96677ba53605311662b6b10.1779392420.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|LV8PR12MB9084:EE_ X-MS-Office365-Filtering-Correlation-Id: 18e6b24d-789e-444e-205e-08deb7786600 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|18002099003|56012099003|22082099003|11063799006|5023799004; X-Microsoft-Antispam-Message-Info: bVdGijgXRJTcwj4E1cnyNB9O0Ast5Tt8llh5/9XelTyzEustUAqawiTcrX36UjxdGFWQdi4lK6KDaGzyOlxtA/MbBpS5uPo0dQ9XJmOclnSwDq+V8LIKHP8EZk0HpNESVjHPMiPAno6A6X0AuntYL9S13NpHe+20SCnTYVShNcTggAjuKEex94pwTcx/5Dg66i3sv6VcPBDVtOrTiKhQ9txbRV14iEhLJ2Yj02KR5eW0gnMdgEhW6aKaB3baQLNz3VU+nfOzAzyWos3FKrzIhxm+3P3s4oZ8fMxnS6/v8H0x9QPk4tgGwly26TVVxdpczucmqY1QgxVl++G2MBZJqIXKawkS79XqusSg5zpL86ePNZS3laHnigEEvfsx+z18U0Eh8EFDmAAwa09GGU8m+O6MFrup3cUgwmwAM9X9/VTnkc3w96eAmuVIl/FhOn2N9+4BBvWL2A+LJFXXjV4iKOXAxQTBIb9eKdYjkdTwmnxcnz9UlO7YfoqBNxg9GyKfAe45rWRXq2sXgqvEDbj6tarROhuk7TeeQU6lBZ3NYL7nFymjm+WX1ARd+S312R6di7lUtOmvWXQmc4awJZulBZOnhPiNxJKy+EhrDjNumyjnyMTPbccxZ0PuEZ24a3fAE4zY2QZV4hBGqHFvj2lSitAaq/m+pVjygOjkDY4Ho2UB5GkQ4e/r583x8V04qf8SX0qosGRztRNXSpXxIZtUXmOmVT1myRaHP0MXvyP4NFA= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(7416014)(1800799024)(18002099003)(56012099003)(22082099003)(11063799006)(5023799004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: feOjQsnWVmN4IKPAPhEMeSIPN9k/U2ePlow6qWoUzmcYI3+McC4tkUlx1onLCik98chMx3tt7dUE2EeZGBgjFrmoXmqWNrnYiG+fSknr0gQ3iVU+4cT2z2OI9hwMxZjLn3lVUfHmnOVxKedirluBwRgFT2NZVq+xWswzGrIO+m/eZOzJ5zk9YCOIBDHqCb94Nx78Y3XaHm6YPT6E+3hPncJdhxV6MVP99lm66/FiVoswZsl6Em7spnQunae57k1bXx9ZX9Ji1fHbEqELjIxjW5+Gxe9O+9eM/71fgKFoC0tksG0iLvvmy/W/y5/VAx3D/sb9dp+OA6vcED1ywLOFIyH6IDASbYOROvx8aGOiBZERBvyuPSBytVfxXT/VfBS7SK/mpfOnqLFLRwLCXBDk5oW615HNnk9d5Y8S3bkUIQ6tXiGgiR71STudwSHhiQ63 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 20:34:46.8275 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18e6b24d-789e-444e-205e-08deb7786600 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9084 Content-Type: text/plain; charset="utf-8" Controlled by IOMMU drivers, ATS can be enabled "on demand", when a given PASID on a device is attached to an I/O page table. This is working, even when a device has no translation on its RID (i.e., RID is IOMMU bypassed). However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "ATS always on" in IOMMU term. For example, CXL spec r4.0 notes in sec 3.2.5.13 Memory Type on CXL.cache: "To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io." In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory. Introduce a new pci_ats_required() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on". Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file. Note that pci_ats_required() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS. Cc: linux-cxl@vger.kernel.org Suggested-by: Vikram Sethi Suggested-by: Jason Gunthorpe Reviewed-by: Jonathan Cameron Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Tested-by: Nirmoy Das Acked-by: Nirmoy Das Reviewed-by: Dave Jiang Acked-by: Bjorn Helgaas Signed-off-by: Nicolin Chen Reviewed-by: Yi Liu --- include/linux/pci-ats.h | 3 +++ include/uapi/linux/pci_regs.h | 1 + drivers/pci/ats.c | 46 +++++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h index 75c6c86cf09dc..f3723b6861294 100644 --- a/include/linux/pci-ats.h +++ b/include/linux/pci-ats.h @@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps); void pci_disable_ats(struct pci_dev *dev); int pci_ats_queue_depth(struct pci_dev *dev); int pci_ats_page_aligned(struct pci_dev *dev); +bool pci_ats_required(struct pci_dev *dev); #else /* CONFIG_PCI_ATS */ static inline bool pci_ats_supported(struct pci_dev *d) { return false; } @@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; } +static inline bool pci_ats_required(struct pci_dev *dev) +{ return false; } #endif /* CONFIG_PCI_ATS */ =20 #ifdef CONFIG_PCI_PRI diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 14f634ab9350d..6ac45be1008b8 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1349,6 +1349,7 @@ /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */ #define PCI_DVSEC_CXL_DEVICE 0 #define PCI_DVSEC_CXL_CAP 0xA +#define PCI_DVSEC_CXL_CACHE_CAPABLE _BITUL(0) #define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2) #define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4) #define PCI_DVSEC_CXL_CTRL 0xC diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index ec6c8dbdc5e9c..84cd06d74fc9c 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -205,6 +205,52 @@ int pci_ats_page_aligned(struct pci_dev *pdev) return 0; } =20 +/* + * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source reques= ts on + * CXL.cache, devices need to get the Host Physical Address (HPA) from the= Host + * by means of an ATS request on CXL.io. + * + * In other words, CXL.cache devices cannot access host physical memory wi= thout + * ATS. + * + * Check Cache_Capable instead of Cache_Enable because CXL.cache may be en= abled + * after the caller uses this to make its ATS decision. + */ +static bool pci_cxl_ats_required(struct pci_dev *pdev) +{ + int offset; + u16 cap; + + offset =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_DEVICE); + if (!offset) + return false; + + if (pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap)) + return false; + + return cap & PCI_DVSEC_CXL_CACHE_CAPABLE; +} + +/** + * pci_ats_required - Whether the PCI device requires ATS + * @pdev: the PCI device + * + * Returns true, if the PCI device requires ATS for basic functional opera= tion. + */ +bool pci_ats_required(struct pci_dev *pdev) +{ + if (!pci_ats_supported(pdev)) + return false; + + /* A VF inherits its PF's requirement for ATS function */ + if (pdev->is_virtfn) + pdev =3D pci_physfn(pdev); + + return pci_cxl_ats_required(pdev); +} +EXPORT_SYMBOL_GPL(pci_ats_required); + #ifdef CONFIG_PCI_PRI void pci_pri_init(struct pci_dev *pdev) { --=20 2.43.0 From nobody Sun May 24 20:33:09 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011014.outbound.protection.outlook.com [40.93.194.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EC9C3F54CB; Thu, 21 May 2026 20:34:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.14 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779395696; cv=fail; b=ZnNHhdrHX0oTzBewu5/ZViBjczk9jyS2edhAH53Nnh2nRuwKNx3zxbzJ32J6zclyMrvdgtQCnKyYAjooeJ20tYUcs2v/TrnH2DzeL0zBBORt0oG5k+HTXxfkQmwvYqSdXXu+8OMu1QpaztxhyrQtDOAZLPlVtPyMy8/wATwfUxQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779395696; c=relaxed/simple; bh=gaAsxiJ564c5Hp53Ica0POGqbtpJBt5/zSrE8ni5r7I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h9o9R9QyMrvyhuE07I27aiYPouGcMSihLTzHCSR5gLNaLnWUXfkFmoycBiXT3JJZ+F7A60RF0V7YJW1F38MCC/pnxqLZp0iBwD3sAL2adnVWpuT3uHuTTLSpDCy5gwCrmEzP0vOqpbRZ3/fg553MXO4j6CI7EImnoa6vhwdKHJ4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=i9ENSrRG; arc=fail smtp.client-ip=40.93.194.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="i9ENSrRG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PAERD0qRxbNjj5+hz7UU0+AO+8c9bHEiQbIGBaYqKCuYxDHL63jRtEFkCjpwXbmxaBvE72Ckf8XOzQIuXQSWzCGs2EBBlSLwTULLJUzfGjhBfCwwmh2OjW6AiAX7dwi9LRXXKS3vtirHl4/mIu8YBAp8OuOwn2vmCGCILQGAQiHKXHyk0Eon3euxN973pGDDv4LGG4Z2wohpYfj1qYmfHN33mDTzVhUXFOwM6cUzcEh7Chz1a6Tj39Sidwnv2CkYgqmPASiCnTH5HZMOdC4iv+gmlA98x8/+Khz7QsLzQpldGZsoa7TgSyocnPClNaCyGBxricQQDAHMrsc2bt8duA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Lgf0aEtRtFeV2l/YODfzgk7aHRNpedUPkIfnvVDlEmg=; b=keku6MyFyTVqszY5lwXmomjwIFjtIwwTmdtQxMNGZq/n4YVod50QubbE/lHgJTiRUQWlkB9lVhnvt7EWJybgRr99z+dFKwcQFcB+0wwJSccxj8MgX/dfEw4AC85+Er2TDrUHpq3jCKV/XA5NkD8lzAyaBbFqmBTi9LG/JZMjEzwECwmK92QUs4A9DWGpEkp46I4FDj2QXphqTq2f0OojHKCo9Xt0GQgWFRC6xPSZ6MC6y1rogpFR3gBQlau5ks3nXeAL6lMpP4k2xoo6aYAVe+sAiyYy8xVd55YKr6a2SRBpxFwpKugehaBA8JhihEYqn1yLCwbzU4OTJhHxMbwp1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=huawei.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Lgf0aEtRtFeV2l/YODfzgk7aHRNpedUPkIfnvVDlEmg=; b=i9ENSrRGR8U/JPNVZWwPxJaPHE52A42gzAybMmZK+1EpAdbBqa40y9z4feQFMtT5f7h7DMvP6QPhTVM8UYfYkU5bhGEd0bruEHCBGe4kpOZPY5KYD4b4vV6YeriKqW/cFAxcvMq9ev37Kh4BfVERPOu93w/53aN4DmwkRVvBUKnX/C4sNdeQlnrOXC/BTAzCIu3rW/Bacb443CZDA7MP0LYx+6QgyuuaHSCHSyp7U6NiQZfKFzrDrflhcZtXHrShO+giNxxw+VWu6iSamUDc1s7pIy3Ytbipi5RywsECNF+72NstXUOBmjaVNFgewIW542NVRxB9YVRCW4pFJytyYQ== Received: from BYAPR21CA0014.namprd21.prod.outlook.com (2603:10b6:a03:114::24) by CYXPR12MB9428.namprd12.prod.outlook.com (2603:10b6:930:d5::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.17; Thu, 21 May 2026 20:34:49 +0000 Received: from CO1PEPF00012E60.namprd05.prod.outlook.com (2603:10b6:a03:114:cafe::14) by BYAPR21CA0014.outlook.office365.com (2603:10b6:a03:114::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Thu, 21 May 2026 20:34:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF00012E60.mail.protection.outlook.com (10.167.249.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Thu, 21 May 2026 20:34:49 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 21 May 2026 13:34:30 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 21 May 2026 13:34:29 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 21 May 2026 13:34:28 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 2/3] PCI: Allow ATS to be always on for pre-CXL devices Date: Thu, 21 May 2026 13:34:21 -0700 Message-ID: <0dd7e22f44bf35a33a590e0916983f9f7fe00de3.1779392420.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E60:EE_|CYXPR12MB9428:EE_ X-MS-Office365-Filtering-Correlation-Id: a68e3630-d7d5-4437-19ab-08deb7786772 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|7416014|1800799024|82310400026|11063799006|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: zyJTvBSxcszM9kdqX6q3Yc9YPhVinx15X+SpJyK4UNHL3FlspnwhFe7bYyNtkPPPzQWMoZXQI2H7e1Kbszj0f2aPInjhgnh+tFn37Ugt88e/hjqKHlcmDWuusXtMPjUj86FrjLQLZU5KclVuuRb8nXAmS2SZlHLdagogQuXRD606OyER0ACPIWgwAbjO2lcGvvDZUELcltuvlOmRNlaX9zzwML3bRUvgRj/oRaIsfopz7S8USEujV+yWsjB7s3Q1ejH/cI1hMS9aWuLXAepcDFLcFW+PXrR4YVKxUTIv+vgVuAbtxW3lNiglKtzHrw6bScZXklQIT7kl1rrdCKTSkXVB/9eEwOCHWvBgDW6XQDimrFU9r1hrcj0Qeum0ANS2LNXY0ocyep2v08p2xvVtJJhVPGHusJuMNUiAHHTP5jj3tBObtcvgOqQo/0TEz2SHPvapprTOJx18hIXKAHQn9tlhfGuccfcivxxIyPABGHZzu4kh/Z+Z1S5M7OGlx4IaRnp8O62MsIWjMc9dErl6NdDnj63ulxpTFVE52hINU0H7wP5KlHlcUpdjEPTv7/yOZeUyPVbC+HAMO9HJD7oMu3vA3yFW0KKcwhk+fVnI+SHP7PzyliKFtWYRxCWxupYXoJwablQk6rHBlS1H7fC+cpQxDD15ZvhcCofidHR3ETmqraag0cbs8gcTzSHgSJ/0x6hU3biZal7UaEDgcPosK41V0xOr8ClhetvvxCBr6j0= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(7416014)(1800799024)(82310400026)(11063799006)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9dvzMmrApIXuVpijaCnYVE4zQNEwkiYhzn0Cuuq6hF6Qw3S77g9nTeq9Ro4f4W9CaFa1uWeSTX0fvd9uvTZ5HAeVjdZknOjw1YJ5Y5oaPCis8ebP8Dsd/V0iDyBRkCv+v7841ae1AV98CxF45DTzXOAlhq7dAHj1LldP4ObSqucW0sBJfRpgCVV9praDkSkPm8d8e8+s69uuANDQdDLNTvRz1nObrq8+gr9rvTXYlx8g4Kyok3ZnFjm55b3a61XRzbGoO08TMpFCnKPaJ+2PqyLWPfqjVn6fs6vZVJP1j3awVTRRLhBkDTj6C2NpBWQ092Iba3uAhIlpwxYxPb7tFo5V0461O2gIL1czTAVIPMc7RqtUkX4xLRgHiwxMdJumhlS9lRrsTUmmklKxuN3nMOKFMAlnALrKKkhnV90vW3NLkD3P09KexB3fUPBFpg0x X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 20:34:49.1629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a68e3630-d7d5-4437-19ab-08deb7786772 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E60.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9428 Content-Type: text/plain; charset="utf-8" Some NVIDIA GPU/NIC devices, though they don't implement CXL config space, have many CXL-like properties. Call this kind "pre-CXL". Similar to CXL.cache capability, these pre-CXL devices also require the ATS function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on" v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases. Introduce pci_dev_specific_ats_required() quirk function to scan a list of IDs for these devices. Then, include it in pci_ats_required(). Suggested-by: Jason Gunthorpe Reviewed-by: Nirmoy Das Tested-by: Nirmoy Das Reviewed-by: Jonathan Cameron Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Reviewed-by: Dave Jiang Acked-by: Bjorn Helgaas Signed-off-by: Nicolin Chen Reviewed-by: Yi Liu --- drivers/pci/pci.h | 9 +++++++++ drivers/pci/ats.c | 3 ++- drivers/pci/quirks.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4a14f88e543a2..e8ad27abb1cfe 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1155,6 +1155,15 @@ static inline int pci_dev_specific_reset(struct pci_= dev *dev, bool probe) } #endif =20 +#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_PCI_ATS) +bool pci_dev_specific_ats_required(struct pci_dev *dev); +#else +static inline bool pci_dev_specific_ats_required(struct pci_dev *dev) +{ + return false; +} +#endif + #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, struct resource *res); diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 84cd06d74fc9c..96efa00d97433 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -247,7 +247,8 @@ bool pci_ats_required(struct pci_dev *pdev) if (pdev->is_virtfn) pdev =3D pci_physfn(pdev); =20 - return pci_cxl_ats_required(pdev); + return pci_cxl_ats_required(pdev) || + pci_dev_specific_ats_required(pdev); } EXPORT_SYMBOL_GPL(pci_ats_required); =20 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index caaed1a01dc02..c0242f3e9f063 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5715,6 +5715,48 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457,= quirk_intel_e2000_no_ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_= ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_= ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_= ats); + +static bool quirk_nvidia_gpu_ats_required(struct pci_dev *pdev) +{ + switch (pdev->device) { + case 0x2e00 ... 0x2e3f: /* GB20B */ + return true; + } + return false; +} + +static const struct pci_dev_ats_required { + u16 vendor; + u16 device; + bool (*ats_required)(struct pci_dev *dev); +} pci_dev_ats_required[] =3D { + /* NVIDIA GPUs */ + { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, quirk_nvidia_gpu_ats_required }, + /* NVIDIA CX10 Family NVlink-C2C */ + { PCI_VENDOR_ID_MELLANOX, 0x2101, NULL }, + { 0 } +}; + +/* + * Some NVIDIA devices do not implement CXL config space, but present as P= CIe + * devices that can issue CXL-like cache operations like CXL.cache. Thus, = they + * require ATS to obtain host physical addresses, like pci_cxl_ats_require= d(). + */ +bool pci_dev_specific_ats_required(struct pci_dev *pdev) +{ + const struct pci_dev_ats_required *i; + + for (i =3D pci_dev_ats_required; i->vendor; i++) { + if (i->vendor !=3D pdev->vendor) + continue; + if (i->ats_required && i->ats_required(pdev)) + return true; + if (!i->ats_required && i->device =3D=3D pdev->device) + return true; + } + + return false; +} #endif /* CONFIG_PCI_ATS */ =20 /* Freescale PCIe doesn't support MSI in RC mode */ --=20 2.43.0 From nobody Sun May 24 20:33:09 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013047.outbound.protection.outlook.com [40.107.201.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD68E72617; Thu, 21 May 2026 20:35:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779395705; cv=fail; b=mbhg5dGF+68HstEy3AC+vk42GkD1Gwkx6OubI4hOBDmQOp7x9gFrVewp5BSBrHSm9VgykhHOHyYWTf6feaQwx1QCwSqtcIICxQJjcLXkFQ94DhPbH/P/YtmXirxn5quUv6cy90DUWZiDh0rirn/V5bxyJsvLq1SMFZftNNjHmm4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779395705; c=relaxed/simple; bh=FiE4jItu1qy5dNxuIhidvzk0xs8KQgOmv7PwL3ZzEOY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JQusEfocV5bUUZNxYpPSTba8NE/JekJU1e50aLbtTtEfne4RsVKUugmk5qnBThirCUxqo0sDW+xYjLWxpAvAYJfR5JCIB8WuuFhT8K0QoBg1ibQjT9gft4oJYHS4yTdkBgd+jgYCJ52LOuxUQtWhJlhQawfDSuzl0yOdEaZikxM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=LZlDc7Nh; arc=fail smtp.client-ip=40.107.201.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="LZlDc7Nh" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gqypivKSVnWlIL+IQ7dRvBj6kmNxgsOchpCjIq9g5rv+pf11Q7P/iFzOBcf2eN+rj0vfO5UTD/JV9moLRgsl5TCZVc2sIeATVGSHZFIpdJVdYmitieYvri+N4I6urkW2ZNFsln8+29d7P6eXci8AfO+W+a5uorZ7LxNgs/yOMGv7PoPZq6+FghpaxU7b9WqMgEfVKQrTZMG0Ot/ZTrkGkTU4WIDVZbML6GAG6L7cUav2pY067vuwmzkdHbgI2pWyy964GvjYs120RmirzvnFyq/eoLgv65SS4S12P8Y+GjKZgCD2NjobdmF3ie3dj+vn2+vSpCHI2wprS4tblOrAfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nMiRy1q/DvI1QURi3LOPF48icrBzVsTuf5SYBSm9o98=; b=MRZEWvcPeUGPDwyPbS2Efa5NXjlFnY/2KCZe7+cLakxH6knwjbMqiA2evwd4m2hpxLMJjR/Sq71FfaXdjHojW48f5swTGZeIXYnCSX/fchiD/mTyKoIg5E1GEvefDfm/GqZkqL4XUw6pAUDR3+0p3g5R1OtPrAYgLOOR4Zy8USoscpu5r6GvACJlPM3WYdR9kFXmCuE0WIF8rWtyWJLlnxAZR1FglBIsjuq8Kp3z5nPc1b2pHWB1v8CXtJlmCgOPmreTdjkeRPFwVzbt90JBagJAszLsQHPO4quGq8DPwXXaAxMjhOnrOF82AjiO/1hJ7T43J5OB3SQZH1VVslkNpw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=huawei.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nMiRy1q/DvI1QURi3LOPF48icrBzVsTuf5SYBSm9o98=; b=LZlDc7Nh5R0weoxcBt2tgVKtvmeox722e+weEffAWYRGg1/Yj9iC6D/l8O05FsGtUUXDe89ex+JgY8Z/kVvD52ks6LCdO0ULLoiJQ4OL/2btJQvzgM0rDzl/LBEuXUSj5HA17pmfoOm1JKydBBvDaigJsrR0XJ8O1ALKOoFslJdrBoGOgsfNOiuQBug0lKm563Or6fnhPOyKaga4f3DhiK3s3z4sgVbT1Pkzk0cRkipMrHPOMQrChQTc8xebtVUBeFTRuMJvj2nW0GTWIZ/dYvlLFuLBk92ywwCHpRVIiOQDPBL7muwkUJeQAUYkNXFYdka2T0h5HQN4nhZPUIfGmw== Received: from SJ0PR05CA0160.namprd05.prod.outlook.com (2603:10b6:a03:339::15) by DS0PR12MB6584.namprd12.prod.outlook.com (2603:10b6:8:d0::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Thu, 21 May 2026 20:34:52 +0000 Received: from CO1PEPF00012E64.namprd05.prod.outlook.com (2603:10b6:a03:339:cafe::66) by SJ0PR05CA0160.outlook.office365.com (2603:10b6:a03:339::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.71.8 via Frontend Transport; Thu, 21 May 2026 20:34:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF00012E64.mail.protection.outlook.com (10.167.249.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Thu, 21 May 2026 20:34:51 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 21 May 2026 13:34:31 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 21 May 2026 13:34:30 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 21 May 2026 13:34:30 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 3/3] iommu/arm-smmu-v3: Allow ATS to be always on Date: Thu, 21 May 2026 13:34:22 -0700 Message-ID: <18bb6f421b3be891caa8f1fb50f3a4d56b52d5be.1779392420.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E64:EE_|DS0PR12MB6584:EE_ X-MS-Office365-Filtering-Correlation-Id: 8206b34f-a270-4f0b-5833-08deb77868c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|7416014|18002099003|56012099003|22082099003|11063799006; X-Microsoft-Antispam-Message-Info: UCKk6YZ6/90OMqcV42ZlUJnWLYxGC9qVbyF2DxtcmTPpTmUkzzhNWlME9FooAecrLGzeLlsnHsyM7TLgvKSTWeIXqkg8sgRt8cHvGCU1zjenORtvpMvFvGSp7B8nyY9ktax4I/iWK+8RHPtaXWznY7efxKPoSo6ghqmVx8ZZRXT3PnD3r5ul+sKUOUnKa4ityO8HkDvw/fKKVO0wIzA0/m0ztFqd6GtvziBXxQ9YkubuSmu2S61hp/sTjr113MSbdgHF0oAzlUPbcZauJHofL6K6xffQ+hNpQwUa3t0fRtBnRxdziC1cI7pl7jl41CIwqu0sXwXxhnOQbkjLpTVoDRIdggLwdc+Ffo/mRVF92Gs2dBlvlRg0iykkom5TOwUyTNePixBb9/euGyjfOI+MbkMjO8em+lK+RymUcO/+mweotxBweqVe6vz9vdzXBECFwpcoiSHYofyIMSwaTsfcRFF387xTQYwzBFQW89dg8x9gBEpy1HxmDCIRbjPWs3bENXR92J/SzWaG/AdVu3EQJe6g+sE/Y9hnZTlJFhgE75WNJRAN5C7hCc//NKXkul0/lP8BJ370DxByiQl5gWy9NcwcKZaGBem2+USqEkI1RK30MZ32DvQR48mVCJ9dtUD6BYx+0FLZ5DtgurgMg3+dW/GTBuVjiAKwNaUgVr1Pbd4CWPnc6FzBHJau0sd13HsJWRgTYvkGIwgC+lN5bwbCe2z8kz0FibjsbkK1c/32Z84= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(7416014)(18002099003)(56012099003)(22082099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CUsWtcEwBwC4eVpfWJCMALJ3Z5lxBwDSkO+Efx0vkiUks0JnO5zA4EXJvz7Nn9El5yh8YE2+J4pMwhpXq4AJ7ppcXC/fkgueXOONCj6dmoB7s5Zwf8MikmzHaC24aZZ4j5i4tn1zQbhFWfgEMk4HoW7iiOc7gBylgC5jOhzFIoUfnz6LCTr9T6uQdTfXvL+9kz2yz/T1tGNbbIfo9QHEEaARy7bhorCpGHRgZ+zeEhh0a94cBY7nAORwdmfD2zLOk203ueMIzJhg9K1gE5RlR3WBvSHhf0PgLE7IKqkuZePk6lWll/z1RmaA1wwn1FZ/IpU1If3zcwsQHqaPfGNCiWzkWSjvBK2/6cWrq7tpH6TtwIhdBd/heLnSwrmi/FrCnU2Vb9nZIv67B+CjemdDbVx/rAVp4cxk48lYkpr5NeBViD1JaMBgYWL7N+azcgC/ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 20:34:51.3341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8206b34f-a270-4f0b-5833-08deb77868c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E64.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6584 Content-Type: text/plain; charset="utf-8" When a device's default substream attaches to an identity domain, the SMMU driver currently sets the device's STE between two modes: Mode 1: Cfg=3DTranslate, S1DSS=3DBypass, EATS=3D1 Mode 2: Cfg=3Dbypass (EATS is ignored by HW) When there is an active PASID (non-default substream), mode 1 is used. And when there is no PASID support or no active PASID, mode 2 is used. The driver will also downgrade an STE from mode 1 to mode 2, when the last active substream becomes inactive. However, there are PCIe devices that demand ATS to be always on. For these devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2. Change the driver accordingly: - always use the mode 1 - never downgrade to mode 2 - allocate and retain a CD table (see note below) Note that these devices might not support PASID, i.e. doing non-PASID ATS. In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to a !0 value in order to keep the S1DSS field effective. Thus, when a master requires ats_always_on, set its s1cdmax to at least 1, meaning that the CD table will have a dummy entry (SSID=3D1) that will never be used. Now for these devices, arm_smmu_cdtab_allocated() will always return true, v.s. false prior to this change. When its default substream is attached to an IDENTITY domain, its first CD is NULL in the table, which is a totally valid case. Thus, add "!master->ats_always_on" to the condition. Reviewed-by: Jonathan Cameron Tested-by: Nirmoy Das Acked-by: Nirmoy Das Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Reviewed-by: Dave Jiang Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 81 ++++++++++++++++++--- 2 files changed, 73 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ef42df4753ec4..8c3600f4364c5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -943,6 +943,7 @@ struct arm_smmu_master { bool ats_enabled : 1; bool ste_ats_enabled : 1; bool stall_enabled; + bool ats_always_on; unsigned int ssid_bits; unsigned int iopf_refcount; }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e8d7dbe495f03..4afdb775e0722 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1742,8 +1742,11 @@ void arm_smmu_clear_cd(struct arm_smmu_master *maste= r, ioasid_t ssid) if (!arm_smmu_cdtab_allocated(&master->cd_table)) return; cdptr =3D arm_smmu_get_cd_ptr(master, ssid); - if (WARN_ON(!cdptr)) + if (!cdptr) { + /* Only ats_always_on allows a NULL CD on default substream */ + WARN_ON(!master->ats_always_on || ssid); return; + } arm_smmu_write_cd_entry(master, ssid, cdptr, &target); } =20 @@ -1756,6 +1759,22 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_= master *master) struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->cd_table; =20 cd_table->s1cdmax =3D master->ssid_bits; + + /* + * When a device doesn't support PASID (non default SSID), ssid_bits is + * set to 0. This also sets S1CDMAX to 0, which disables the substreams + * and ignores the S1DSS field. + * + * On the other hand, if a device demands ATS to be always on even when + * its default substream is IOMMU bypassed, it has to use EATS that is + * only effective with an STE (CFG=3DS1translate, S1DSS=3DBypass). For su= ch + * use cases, S1CDMAX has to be !0, in order to make use of S1DSS/EATS. + * + * Set S1CDMAX no lower than 1. This would add a dummy substream in the + * CD table but it should never be used by an actual CD. + */ + if (master->ats_always_on) + cd_table->s1cdmax =3D max_t(u8, cd_table->s1cdmax, 1); max_contexts =3D 1 << cd_table->s1cdmax; =20 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || @@ -3854,9 +3873,12 @@ static int arm_smmu_blocking_set_dev_pasid(struct io= mmu_domain *new_domain, if (!arm_smmu_ssids_in_use(&master->cd_table)) { struct iommu_domain *sid_domain =3D iommu_driver_get_domain_for_dev(master->dev); + bool ats_always_on =3D master->ats_always_on && + sid_domain->type !=3D IOMMU_DOMAIN_BLOCKED; + bool downgrade =3D sid_domain->type =3D=3D IOMMU_DOMAIN_IDENTITY || + sid_domain->type =3D=3D IOMMU_DOMAIN_BLOCKED; =20 - if (sid_domain->type =3D=3D IOMMU_DOMAIN_IDENTITY || - sid_domain->type =3D=3D IOMMU_DOMAIN_BLOCKED) + if (!ats_always_on && downgrade) sid_domain->ops->attach_dev(sid_domain, dev, sid_domain); } @@ -3875,6 +3897,8 @@ static void arm_smmu_attach_dev_ste(struct iommu_doma= in *domain, .old_domain =3D old_domain, .ssid =3D IOMMU_NO_PASID, }; + bool ats_always_on =3D master->ats_always_on && + s1dss !=3D STRTAB_STE_1_S1DSS_TERMINATE; =20 /* * Do not allow any ASID to be changed while are working on the STE, @@ -3886,7 +3910,7 @@ static void arm_smmu_attach_dev_ste(struct iommu_doma= in *domain, * If the CD table is not in use we can use the provided STE, otherwise * we use a cdtable STE with the provided S1DSS. */ - if (arm_smmu_ssids_in_use(&master->cd_table)) { + if (ats_always_on || arm_smmu_ssids_in_use(&master->cd_table)) { /* * If a CD table has to be present then we need to run with ATS * on because we have to assume a PASID is using ATS. For @@ -4215,6 +4239,44 @@ static void arm_smmu_remove_master(struct arm_smmu_m= aster *master) kfree(master->build_invs); } =20 +static int arm_smmu_master_prepare_ats(struct arm_smmu_master *master) +{ + bool s1p =3D master->smmu->features & ARM_SMMU_FEAT_TRANS_S1; + unsigned int stu =3D __ffs(master->smmu->pgsize_bitmap); + struct pci_dev *pdev; + int ret; + + if (!dev_is_pci(master->dev)) + return 0; + pdev =3D to_pci_dev(master->dev); + + if (!arm_smmu_ats_supported(master)) { + if (pci_ats_required(pdev)) { + dev_err_once(master->dev, "SMMU doesn't support ATS\n"); + return -EOPNOTSUPP; + } + return 0; + } + + ret =3D pci_prepare_ats(pdev, stu); + if (ret || !pci_ats_required(pdev)) + return ret; + + /* + * S1DSS is required for ATS to be always on for identity domain cases. + * However, the S1DSS field is ignored if !IDR0_S1P or !IDR1_SSIDSIZE. + */ + if (!s1p || !master->smmu->ssid_bits) { + dev_err_once(master->dev, + "SMMU doesn't support ATS to be always on\n"); + return -EOPNOTSUPP; + } + + master->ats_always_on =3D true; + + return arm_smmu_alloc_cd_tables(master); +} + static struct iommu_device *arm_smmu_probe_device(struct device *dev) { int ret; @@ -4263,14 +4325,15 @@ static struct iommu_device *arm_smmu_probe_device(s= truct device *dev) smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled =3D true; =20 - if (dev_is_pci(dev)) { - unsigned int stu =3D __ffs(smmu->pgsize_bitmap); - - pci_prepare_ats(to_pci_dev(dev), stu); - } + ret =3D arm_smmu_master_prepare_ats(master); + if (ret) + goto err_disable_pasid; =20 return &smmu->iommu; =20 +err_disable_pasid: + arm_smmu_disable_pasid(master); + arm_smmu_remove_master(master); err_free_master: kfree(master); return ERR_PTR(ret); --=20 2.43.0