From nobody Fri Jun 12 21:29:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 238283B102B for ; Tue, 12 May 2026 14:26:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595991; cv=none; b=XkBwOTmkqX1+Ip89bIODZvfV2ZJgBB0FOjedvmFnMoJsKJ9AVpn25vb7d3LD0NPO+MmCDDgyVBX5mR5vF/jHiIMLieHzCzg4bI6ln6KbTtX9o9SXKvYFseL+8JZsMVAvCCMk7GvveUmdpqTQ1o5lkRSqMpvc+9d/6Eti1B4PXPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595991; c=relaxed/simple; bh=h+3qov3k+VwgkdZvrPuDzMAklnb5ZHuO2HBKmVLnsjg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IXk+bOmHBZUOrO5Pq6Mmc+lUzCfwNznpoINQ4LgUdUoU52zi0dHLka9L+vhMHJM/mSUlBlPRAN/Df+cZol0aQgm265bPz5UtSSSfdobebZXAOloHegFYNdVeURgf11TU0BzEwN7ue5A4YMsk1jy88/y0bFzKCi9N46Rf1l7gWHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B4JyUvE9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B4JyUvE9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 628C6C2BCB0; Tue, 12 May 2026 14:26:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595990; bh=h+3qov3k+VwgkdZvrPuDzMAklnb5ZHuO2HBKmVLnsjg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4JyUvE9HtW+dVH53U19iwP4XVJ0D/TlJKzCPAQ8h1bOj83JrtiZQyfhJqCZJbQNL j4UI78vhv1hcZI8r43ZtkzAgUazJ3JbnmjoCEyE4u0aEZIKu/DkNpeVALcCtELvAeD r14U5B5Lnr/6XfjaVH8z19y0AryhJQLBt/7HC5emcZ6KGwalJNRqzpca0ubDLNS9WK 88JXSjYAms4HVXmEJruTiYS8iyNbmo5BCoW2r4MyX5neE1F04F50V5U2+qynkwkECV 8xaTVR4/F8jj+V8XLD4vbl8KPn18Vq9XsDJEhnyS6RZvp/Ay3Ib1UiRHc9OG5QyJlA xJWprhJRpk+8w== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Tue, 12 May 2026 19:49:15 +0530 Message-ID: <9e5fb0818b73e4ac72e2137b1cff90685a3ad528.1778594390.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 20c2de5c697b..ad73a002f8cd 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) =20 preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset =3D 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset =3D 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); =20 - if (offset =3D=3D APIC_EILVT_NR_MAX) { + if (offset =3D=3D APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } --=20 2.54.0 From nobody Fri Jun 12 21:29:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E2BB3B1EC2 for ; Tue, 12 May 2026 14:26:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595983; cv=none; b=Hj+HsVDU+gHSIwev6SdsydpxbG8fpKugNco8hi5ruzTooRz+QwRuKpQ4RKPrS5rPdseVl0YRUkStMcJerLHmTZ2LWF+zMnf24imbtuCSCHqkQm2HWKFxyR6UGAgZDTSiHIvs9+yCECjSUGdTQvXdr9F5n8fHRFrTjCXdcbUvL48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595983; c=relaxed/simple; bh=yQY/GsFxh7GejqJJ6NJ9j2O6/F0XXnw6R5O0ycuRTWA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GIq/bLRczv+GuWmDyd9NT12u7+m0O7/FPQBblZcljP4v4fdkxctFWkX6Cy0jNaVlsmkFcycMQfFvX4x7Cyc6q6ifjiDnuR82CjUDNNdoS6GQmYH8jpdANP+hYHWnoUa77dh2219Js3ZOn5hZd8K1Q8aECfTiN3YHsk+zUdPUXBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eF5XxOhq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eF5XxOhq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60977C2BCB0; Tue, 12 May 2026 14:26:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595983; bh=yQY/GsFxh7GejqJJ6NJ9j2O6/F0XXnw6R5O0ycuRTWA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eF5XxOhqVWoXj2uC/f0Kd8qR1+PeWmomXTY2PT8C2mPTOrISy6vp+dMmJpATIR6sn RsXT6M0nYUo9/r3H0+Wek0fKDVDiArmDfbL1ThSJF6njobovZtXyUAu5jDADdXQtyx k5110yplwjJl+TfgZOTCfXGGz1E1RJSdY5aCemj7ZCKyTxAyte+K4evPlopxBKD5gR RwL/HRC2IdNV3TGD6IwhsK5FagzZF1syZAQnYpPB/1JWcUkLlu3IR764awUXUN+qbE AY2cwDYOVtBHrlBgXnAzXSvXBv5DSTuK2JYUD0P64Y8Sl7Tx0VAfCTSo3uuoiZT7Rx oB+GWUFyDGAlw== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Date: Tue, 12 May 2026 19:49:16 +0530 Message-ID: <78a4c3ddce65e2a79f23aea6fdc05faf4346d290.1778594390.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable to track the EILVT register count. The number of EILVT registers is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Export the new variable for KVM since it needs this for supporting extended APIC register space on AMD. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- http://lore.kernel.org/r/20260204074452.55453-3-manali.shukla@amd.com as=20 a related series adding support for KVM and needing access to the EILVT=20 register count. - Naveen arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 12 ++++++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..8b03c7a14706 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -74,6 +74,8 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; =20 +extern unsigned int apic_eilvt_count; + /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 8c614750a19b..ecbf15399399 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -342,6 +342,8 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) */ =20 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +unsigned int apic_eilvt_count __ro_after_init; +EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { @@ -410,6 +412,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type= , u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); =20 +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic_eilvt_count =3D APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic_eilvt_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -2344,6 +2355,7 @@ static void __init apic_bsp_setup(bool upmode) if (upmode) apic_bsp_up_setup(); setup_local_APIC(); + init_eilvt(); =20 enable_IO_APIC(); end_local_APIC_setup(); --=20 2.54.0 From nobody Fri Jun 12 21:29:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BD0E3AEB4A for ; Tue, 12 May 2026 14:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595987; cv=none; b=cj56n8BuIt0plpxKa8O4g2giE9TgoxLFf9kCGobEUKmniNBGKUgZfCA+fc9DqoDTkRWsuccJvxIETWymdgyMrtnL596ebiBneWAXNJeRkKGSzYS6AkMXqbaiXDr/P6nhC1CWHaT/70dZ+YwPbDI0cs1GVIIKjswf4M+iFciNu1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595987; c=relaxed/simple; bh=qpMdxz9TgEC1c+q/t9iob6swPriRIunzLAqBFHJNEyU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t2oIkxWwl+/uXpUAuGKSrf7yn0D3SEivN1GzpTohp/uEhiTK1QJJpjKDObG9lqaeiJABlcWsMVfw9giwmxun18PScQaYsEmCZrFhnO23BCmqPukd6NZQrwuuHOuTNoZYW8ZnQ5ZY20Zxa3qLCBP7CUTDoU20dxkcPIscURnDNU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Yl5wkkL+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Yl5wkkL+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64547C2BCB0; Tue, 12 May 2026 14:26:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595987; bh=qpMdxz9TgEC1c+q/t9iob6swPriRIunzLAqBFHJNEyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Yl5wkkL+ifgh5ntiohXlc4oImksZEJtnMNpFgf/bLrsTtLv24PT9zVovGypxO4lrD /pdzXW0J8698aqeiLHnhOObtr474ZJsCW6V+GQgd7tAHAlL5nPPhkqDb3Y7qaw7ASX RQM5bcjybkxtSH7VMRvEHCu/iI5LdKGT+su+kg7Qia8IPpMxwSGX8rDOUJduSn10Zy OapMd16OxPxWv7DLI202bLeFZufIShSRfNNcOsnMMBMzbq9Kk6V7oUmorUXp/qSj0M qecrduONL+4pkEV9xByI3IpTHUb6PC6IGRn9k6zwD1LYzlNJHBC1ezcLPJuQey+ylv vRv4gRvu62zSw== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Date: Tue, 12 May 2026 19:49:17 +0530 Message-ID: <0cf8b5dc628faaca27920994eb9ad229d94e7d1c.1778594390.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to using apic_eilvt_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index ecbf15399399..0313989e1632 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * necessarily a BIOS bug. */ =20 -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; unsigned int apic_eilvt_count __ro_after_init; EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); =20 @@ -356,7 +356,7 @@ static unsigned int reserve_eilvt_offset(int offset, un= signed int new) { unsigned int rsvd, vector; =20 - if (offset >=3D APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >=3D apic_eilvt_count) return ~0; =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); @@ -419,6 +419,9 @@ static __init void init_eilvt(void) =20 if (!apic_eilvt_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; + + if (apic_eilvt_count) + eilvt_offsets =3D kzalloc_objs(atomic_t, apic_eilvt_count); } =20 /* --=20 2.54.0