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Wed, 6 May 2026 09:06:18 +0000 (GMT) From: Sayali Patil To: linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com Cc: linux-kernel@vger.kernel.org, Ritesh Harjani , Mahesh Salgaonkar , sshegde@linux.ibm.com, chleroy@kernel.org Subject: [PATCH 1/3] powerpc/time: remove preempt_disable/enable from arch_irq_work_raise() Date: Wed, 6 May 2026 14:36:12 +0530 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=XPQAjwhE c=1 sm=1 tr=0 ts=69fb0491 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=ES_PRLIWHEyu4WWh1w8A:9 X-Proofpoint-ORIG-GUID: 3Wb57npoFTKTbM3wDPzFmvXjkmZgL2UQ X-Proofpoint-GUID: dLKAQyOrL7NW9a9Ui_QOPVs6EZvcGSny X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA2MDA4OCBTYWx0ZWRfXzktigx1BSbPZ IHtLBu/QItIlVMumA4Qy+w3rweontkKbf461YJiWTk6ylknOPLa11FEnwbcSZR3V9WXlkEasQaH Fem+F+v9P7C04YfrngaSvsJ8kYeig0nCjfR88B4lM2uoiyDx6SaY/COEYTkKye2STS8lzla5wq5 uD+kLosauHxIdpqPgdiVjhuIWs25QQx7pKJbOAg+m0YlMA9Sz8ovy3JNpQPhdN66OWkKtAv2Eqq NgJiD1HmrcI51L5pIHHWNGvyegTEKB+XzPqISi+Vws6qW5Mw6iFzjaN3cFtORhfDzUEX4juaB4a PmCn9AOVXcwm/ggx/tzxG6KV7K3xD128f2UI7gwYqhdLjBEn3ivo/FIUrWYpi2uhVEv/ul88OP8 hdSCg2GjD26PJ3QlWxNvRQ5hvbBnmFhWh3unFuJiOL+cKeZuBDo3RudQ16jlvj+vKbSSKxObKJS Lup+/C+sIIOL9WpBwuQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-05_03,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 spamscore=0 priorityscore=1501 impostorscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605060088 Content-Type: text/plain; charset="utf-8" A kernel panic is observed when handling machine check exceptions from real mode. BUG: Unable to handle kernel data access on read at 0xc00000006be21300 Oops: Kernel access of bad area, sig: 11 [#1] NIP [c000000000029e40] arch_irq_work_raise+0x10/0x70 LR [c00000000003ffc8] machine_check_queue_event+0xa8/0x150 Call Trace: [c0000000179d3c70] [c00000000003ff64] machine_check_queue_event+0x44/0x150 [c0000000179d3d30] [c0000000000084e0] machine_check_early_common+0x1f0/0x= 2c0 The crash occurs because arch_irq_work_raise() calls preempt_disable() from machine check exception (MCE) handlers running in real mode. In this context, accessing the preempt_count can fault, leading to the panic. The preempt_disable()/preempt_enable() pair in arch_irq_work_raise() was originally added by commit 0fe1ac48bef0 ("powerpc/perf_event: Fix oops due to perf_event_do_pending call") to avoid races while raising irq work from exception context. Later, commit 471ba0e686cb ("irq_work: Do not raise an IPI when queueing work on the local CPU") added preemption protection in irq_work_queue() path, while commit 20b876918c06 ("irq_work: Use per cpu atomics instead of regular atomics") added equivalent protection in irq_work_queue_on() before reaching arch_irq_work_raise(): irq_work_queue() / irq_work_queue_on() -> preempt_disable() -> __irq_work_queue_local() -> irq_work_raise() -> arch_irq_work_raise() As a result, callers other than mce_irq_work_raise() already execute with preemption disabled, making the additional preempt_disable()/preempt_enable() pair in arch_irq_work_raise() redundant. Remove it to avoid accessing preempt_count from real mode context. Fixes: cc15ff327569 ("powerpc/mce: Avoid using irq_work_queue() in realmode= ") Suggested-by: Mahesh Salgaonkar Signed-off-by: Sayali Patil Acked-by: Shrikanth Hegde Reviewed-by: Ritesh Harjani (IBM) --- arch/powerpc/kernel/time.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 4bbeb8644d3d..a99eb43f6ce9 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -471,10 +471,8 @@ void arch_irq_work_raise(void) * which could get tangled up if we're messing with the same state * here. */ - preempt_disable(); set_irq_work_pending_flag(); set_dec(1); - preempt_enable(); } =20 static void set_dec_or_work(u64 val) --=20 2.52.0 From nobody Sat Jun 13 17:00:45 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CCB135F5E4 for ; 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Wed, 6 May 2026 09:06:21 +0000 (GMT) From: Sayali Patil To: linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com Cc: linux-kernel@vger.kernel.org, Ritesh Harjani , Mahesh Salgaonkar , sshegde@linux.ibm.com, chleroy@kernel.org Subject: [PATCH 2/3] lkdtm/powerpc: add isync after slbmte to enforce SLB update ordering Date: Wed, 6 May 2026 14:36:13 +0530 Message-ID: <4539b61bb6ff2e4fb89e89f760c11714d9ad26a1.1778057685.git.sayalip@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA2MDA4OCBTYWx0ZWRfX0969AEjLd5I9 pZwDRhH2/H9CX6fF1mYDcR/Hs+hviNB9RZwuJc0PjTk+UNEDANwp3/aEwsKSYgwmyX7nnKl5FaY Dd18Ljwcj3b+s8SzGlrGkVyC1mWbFSHPG8g7wYjBDvNRjkT2gDH97DDcrKSpMmbpJwO88QtRawC Zt74FGLSkZgN+dypHFnhLaAJXdBXy0QIHXhYC6xVbl+uNqkETVmOa9japrzUV357XikV4FQz9S/ 5tMa7KgZFR3EyCzGdDV++nlRKMTHwtuAZv3vn9UaghiOgCOU98WA08CqhXu+sA9IqNgNjHEfqqV A4TYf7OquV1sEzblQENfxNxw5FIa9xj625CuURPA0jBLoYxH+yiGiDF8NGyQ65/C3aXINUvoINo tRlAVG6zygM4iSpPzDjn5XP5yo+hNmNDR4mWVEfwcCGGd2L/cxSDNN1jYan8dHqSPNQqw3ZJz3+ AVD6zwC7RrfaEL8PSsg== X-Proofpoint-ORIG-GUID: CMX9D9jXvKVn5u_CIba_zCvW4JPIw-i- X-Proofpoint-GUID: mp04mQzhU-H8FN_c6NOy0rVnx9qpngQq X-Authority-Analysis: v=2.4 cv=W7UIkxWk c=1 sm=1 tr=0 ts=69fb0495 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=pGLkceISAAAA:8 a=VnNF1IyMAAAA:8 a=kezLWu8HVOdeeWrntvsA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-05_03,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605060088 Content-Type: text/plain; charset="utf-8" The slbmte instruction modifies the Segment Lookaside Buffer, but without a context synchronizing operation the CPU is not guaranteed to observe the updated SLB state for subsequent instructions. This can result in use of stale translation state when memory is accessed immediately after SLB modifications. Add isync after each slbmte in the PPC_SLB_MULTIHIT test to ensure proper ordering of SLB updates before subsequent memory accesses. This aligns with Power ISA context synchronization requirements for changes in address translation state and improves the reliability of SLB multihit injection tests in hash MMU mode. Suggested-by: Ritesh Harjani (IBM) Signed-off-by: Sayali Patil --- drivers/misc/lkdtm/powerpc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/misc/lkdtm/powerpc.c b/drivers/misc/lkdtm/powerpc.c index be385449911a..ef07e5201edf 100644 --- a/drivers/misc/lkdtm/powerpc.c +++ b/drivers/misc/lkdtm/powerpc.c @@ -17,11 +17,14 @@ static void insert_slb_entry(unsigned long p, int ssize= , int page_size) : "r" (mk_vsid_data(p, ssize, flags)), "r" (mk_esid_data(p, ssize, SLB_NUM_BOLTED)) : "memory"); + isync(); =20 asm volatile("slbmte %0,%1" : : "r" (mk_vsid_data(p, ssize, flags)), "r" (mk_esid_data(p, ssize, SLB_NUM_BOLTED + 1)) : "memory"); + isync(); + preempt_enable(); } =20 @@ -84,6 +87,7 @@ static void insert_dup_slb_entry_0(void) : "r" (vsid), "r" (esid | SLB_NUM_BOLTED) : "memory"); + isync(); =20 asm volatile("slbmfee %0,%1" : "=3Dr" (esid) : "r" (i)); asm volatile("slbmfev %0,%1" : "=3Dr" (vsid) : "r" (i)); @@ -93,6 +97,7 @@ static void insert_dup_slb_entry_0(void) : "r" (vsid), "r" (esid | (SLB_NUM_BOLTED + 1)) : "memory"); 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charset="utf-8" Add a new LKDTM trigger (PPC_RADIX_TLBIEL) that executes a process-scoped radix TLBIEL instruction to exercise the radix MMU behaviour and associated machine check exception (MCE) handling paths. This provides a way to validate MCE handling in radix mode. Currently, there is no dedicated LKDTM test that exercises this path or allows triggering radix-specific machine check behaviour for validation. The test is only enabled on ppc64 systems with radix MMU support and If radix is not active, the trigger is skipped and reported as XFAIL. Co-developed-by: Ritesh Harjani (IBM) Signed-off-by: Ritesh Harjani (IBM) Signed-off-by: Sayali Patil --- drivers/misc/lkdtm/Makefile | 2 +- drivers/misc/lkdtm/powerpc.c | 39 +++++++++++++++++++++++++ tools/testing/selftests/lkdtm/tests.txt | 1 + 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/misc/lkdtm/Makefile b/drivers/misc/lkdtm/Makefile index 03ebe33185f9..4e58d16fc01e 100644 --- a/drivers/misc/lkdtm/Makefile +++ b/drivers/misc/lkdtm/Makefile @@ -11,7 +11,7 @@ lkdtm-$(CONFIG_LKDTM) +=3D usercopy.o lkdtm-$(CONFIG_LKDTM) +=3D kstack_erase.o lkdtm-$(CONFIG_LKDTM) +=3D cfi.o lkdtm-$(CONFIG_LKDTM) +=3D fortify.o -lkdtm-$(CONFIG_PPC_64S_HASH_MMU) +=3D powerpc.o +lkdtm-$(CONFIG_PPC_BOOK3S_64) +=3D powerpc.o =20 KASAN_SANITIZE_stackleak.o :=3D n =20 diff --git a/drivers/misc/lkdtm/powerpc.c b/drivers/misc/lkdtm/powerpc.c index ef07e5201edf..3d56b56f5e0c 100644 --- a/drivers/misc/lkdtm/powerpc.c +++ b/drivers/misc/lkdtm/powerpc.c @@ -105,6 +105,31 @@ static void insert_dup_slb_entry_0(void) preempt_enable(); } =20 +static void tlbiel_va(unsigned long va, + unsigned long pid, + unsigned long ap, + unsigned long ric) +{ + unsigned long rb, rs, prs, r; + + rb =3D va & ~(PPC_BITMASK(52, 63)); + rb |=3D ap << PPC_BITLSHIFT(58); + rs =3D pid << PPC_BITLSHIFT(31); + + prs =3D 1; /* process scoped */ + r =3D 1; /* radix format */ + + /* + * Trigger an MCE by issuing radix tlbiel with an invalid operand combina= tion. + * Using PRS=3D1 (process-scoped) with kernel address does not correspond= to + * any valid process-scoped translation. + * This results in an invalid tlbiel operation, causing hardware to + * raise a machine check. + */ + asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); +} + static void lkdtm_PPC_SLB_MULTIHIT(void) { if (!radix_enabled()) { @@ -124,8 +149,22 @@ static void lkdtm_PPC_SLB_MULTIHIT(void) } } =20 +static void lkdtm_PPC_RADIX_TLBIEL(void) +{ + unsigned long addr =3D PAGE_OFFSET; + + if (radix_enabled()) { + pr_info("Injecting Radix TLB invalidation MCE\n"); + tlbiel_va(addr, 0, 0, RIC_FLUSH_ALL); + pr_info("Recovered from radix tlbiel attempt\n"); + } else { + pr_err("XFAIL: This test is for ppc64 and with radix mode MMU only\n"); + } +} + static struct crashtype crashtypes[] =3D { CRASHTYPE(PPC_SLB_MULTIHIT), + CRASHTYPE(PPC_RADIX_TLBIEL), }; =20 struct crashtype_category powerpc_crashtypes =3D { diff --git a/tools/testing/selftests/lkdtm/tests.txt b/tools/testing/selfte= sts/lkdtm/tests.txt index 3245032db34d..d8180bbe31e8 100644 --- a/tools/testing/selftests/lkdtm/tests.txt +++ b/tools/testing/selftests/lkdtm/tests.txt @@ -86,3 +86,4 @@ FORTIFY_STR_MEMBER detected buffer overflow FORTIFY_MEM_OBJECT detected buffer overflow FORTIFY_MEM_MEMBER detected field-spanning write PPC_SLB_MULTIHIT Recovered +#PPC_RADIX_TLBIEL Triggers unrecoverable MCE --=20 2.52.0