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([121.160.151.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed5f30ddsm502899b3a.26.2026.04.28.20.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 20:51:39 -0700 (PDT) From: Chanhong Jung To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: gpio: fairchild,74hc595: add lines-initial-states property Date: Wed, 29 Apr 2026 12:51:33 +0900 Message-Id: <20260429035134.1023330-2-happycpu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 74HC595 and 74LVC594 shift registers latch their outputs until the first serial write, so boards that depend on a specific power-on pattern (for example active-low indicators, reset lines, or other signals that must come up non-zero) have no way to express that today: the Linux driver always writes zeros from its zero-initialised buffer during probe. Document support for the existing lines-initial-states bitmask, already defined for nxp,pcf8575, so the same convention covers this output-only device. Bit N corresponds to GPIO line N. Because the 74HC595/74LVC594 family is push-pull output only (no input mode, no high-impedance state under software control), bit=3D0 drives the line low and bit=3D1 drives it high; this differs from nxp,pcf8575, where the 0/1 polarity reflects the quasi-bidirectional nature of that part. The bitmask covers up to 32 lines, which fits the typical 1-4 chip cascades that appear in tree. Should longer chains require seeding in the future, the property can be extended to a uint32-array without breaking the bit-N-equals-line-N convention. Suggested-by: Linus Walleij Signed-off-by: Chanhong Jung Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/gpio/fairchild,74hc595.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml = b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 23410aeca..451538df6 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -45,6 +45,18 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of daisy-chained shift registers =20 + lines-initial-states: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask that specifies the initial state of each output line, written + by the driver before the gpiochip is registered. Bit N corresponds to + GPIO line N, following the convention already documented for + nxp,pcf8575. Because the 74HC595/74LVC594 family is push-pull output + only, a bit set to zero drives the line low and a bit set to one + drives it high. The bitmask covers up to 32 lines (four cascaded + registers); outputs beyond that come up zeroed. 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([121.160.151.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8ec003dcsm18151031b3a.52.2026.04.22.09.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2026 09:05:12 -0700 (PDT) From: Chanhong Jung To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: gpio: fairchild,74hc595: add registers-default property Date: Thu, 23 Apr 2026 01:05:03 +0900 Message-Id: <33d515f13769c685e6811463a14e111252a7c58d.1776872453.git.happycpu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 74HC595 and 74LVC594 shift registers latch their outputs until the first serial write, so boards that depend on a specific power-on pattern (for example active-low indicators, reset lines, or other signals that must come up non-zero) have no way to express that today: the Linux driver always writes zeros from its zero-initialised buffer during probe. Describe a new optional 'registers-default' property that carries a u8 array - one byte per cascaded register, in the same order used by the driver's internal buffer (first byte targets the last register in the chain). The Linux driver change that consumes this property follows. This property is already recognised by the corresponding U-Boot driver (drivers/gpio/74x164_gpio.c), so documenting it here brings the two bindings back in sync and allows boards to initialise the chain once from the bootloader DT and keep the same value after the kernel takes over. Signed-off-by: Chanhong Jung --- .../devicetree/bindings/gpio/fairchild,74hc595.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml = b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 23410aeca..c6221ed75 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -45,6 +45,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of daisy-chained shift registers =20 + registers-default: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Initial state of the daisy-chained outputs, written by the driver + before the gpiochip is registered. One byte per cascaded register, + in the same order used by the driver's buffer (the first byte + targets the last register in the chain). When absent, outputs come + up zeroed. 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([121.160.151.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed5f30ddsm502899b3a.26.2026.04.28.20.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 20:51:42 -0700 (PDT) From: Chanhong Jung To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] gpio: 74x164: support lines-initial-states for boot-time output state Date: Wed, 29 Apr 2026 12:51:34 +0900 Message-Id: <20260429035134.1023330-3-happycpu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 74HC595 and 74LVC594 chains retain their output state from the first serial write onwards. Today the driver always kicks that first write from a zero-initialised buffer, so every output comes up low until user space issues a write. Boards that rely on the chain to drive signals whose power-on state matters (active-low indicators, reset lines, etc.) have no way to express the desired initial pattern via DT. Read the optional lines-initial-states bitmask, recently documented for this binding, into chip->buffer before the first __gen_74x164_write_config() so the chain comes up in a known state on the very first SPI transaction. Bit N maps to GPIO line N (matching the nxp,pcf8575 convention); on this output-only device, bit=3D0 drives the line low and bit=3D1 drives it high. Property absence keeps the existing zeroing behaviour intact. Suggested-by: Linus Walleij Signed-off-by: Chanhong Jung Reviewed-by: Linus Walleij --- drivers/gpio/gpio-74x164.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c index c226524ef..5ca61cf52 100644 --- a/drivers/gpio/gpio-74x164.c +++ b/drivers/gpio/gpio-74x164.c @@ -112,7 +112,7 @@ static int gen_74x164_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; struct gen_74x164_chip *chip; - u32 nregs; + u32 nregs, init_state; int ret; =20 /* @@ -134,6 +134,21 @@ static int gen_74x164_probe(struct spi_device *spi) =20 chip->registers =3D nregs; =20 + /* + * Optionally seed the chain with a board-specified pattern so the + * outputs come up in a known state on the first SPI write. The + * property follows the nxp,pcf8575 convention where bit N maps to + * GPIO line N. On this output-only device, bit=3D0 drives the line + * low and bit=3D1 drives it high. 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([121.160.151.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8ec003dcsm18151031b3a.52.2026.04.22.09.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2026 09:05:15 -0700 (PDT) From: Chanhong Jung To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] gpio: 74x164: support 'registers-default' DT property for initial state Date: Thu, 23 Apr 2026 01:05:04 +0900 Message-Id: <77cc91a966bfcbeaad825b8be607dbd7a85dbbdb.1776872453.git.happycpu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 74HC595 and 74LVC594 chains retain their output state from the first serial write onwards. Today the driver always kicks that first write from a zero-initialised buffer, so every output comes up low until user space issues a write. Boards that rely on the chain to drive signals whose power-on state matters (active-low indicators, reset lines, etc.) have no way to express the desired initial pattern via DT, and must reinvent it from user space each time after probe. Read the new optional 'registers-default' u8 array into chip->buffer after the buffer's size becomes known (so __counted_by() is satisfied) and before the first __gen_74x164_write_config(). Absence of the property keeps the current zeroing behaviour; an invalid size is rejected with dev_err_probe() so that dtbs_check violations surface loudly at probe time. The matching binding change documents the property's layout. The corresponding U-Boot driver (drivers/gpio/74x164_gpio.c) has honoured the same property for years, so the two bootstages can now agree on the initial state without user-space involvement. Signed-off-by: Chanhong Jung --- drivers/gpio/gpio-74x164.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c index c226524ef..b433a4a61 100644 --- a/drivers/gpio/gpio-74x164.c +++ b/drivers/gpio/gpio-74x164.c @@ -134,6 +134,20 @@ static int gen_74x164_probe(struct spi_device *spi) =20 chip->registers =3D nregs; =20 + /* + * Optionally seed the chain with a board-specified pattern so that + * the outputs come up in a known state on the first SPI write. When + * the property is absent, the buffer stays zeroed by devm_kzalloc() + * and the existing behaviour is preserved. + */ + if (device_property_present(dev, "registers-default")) { + ret =3D device_property_read_u8_array(dev, "registers-default", + chip->buffer, nregs); + if (ret) + return dev_err_probe(dev, ret, + "Invalid 'registers-default'\n"); + } + chip->gpiod_oe =3D devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); if (IS_ERR(chip->gpiod_oe)) return PTR_ERR(chip->gpiod_oe); --=20 2.34.1