From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0324335972; Tue, 21 Apr 2026 18:12:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795123; cv=none; b=a4t4hMIDD/kOqgmBtjR09MHEg5rpPTwryZa18uAfXHLvac26IdCaNZdE6/k1Dydhbc/K4TVjEcO5KJAsk1BwtoYVBuE5N4r+FxqdvU9GrqHdQUg8d/9LYgBbINNpyOfOU2sbo3ieYiKZj7kmvevw6XHzLodyDomBDozhcUQdDD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795123; c=relaxed/simple; bh=5VEixkE58MNW6N7cqIB2r0d5ZtOUBNpC57TW2bIdFYQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dt4vZ45zcMXn9E1sQWJrfLUh0Y3AXkyymJIdUANZFAN3TGYgQwcixcwxv+SgJQpj0nWLxRpLIKXR2JAPQGRgoQ601JmxE+xy5VDQ8kdU0g/S5wiwntGE+R/lrOOCB9AnsOh0f47Uq6/RCZelMvgcejs3JWZkbYbBhClWiXitTr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 02FABC2BCB4; Tue, 21 Apr 2026 18:11:57 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 01/14] firmware: arm_scmi: quirk: Handle bad power domains on R-Car X5H Date: Tue, 21 Apr 2026 20:11:34 +0200 Message-ID: <393522103906f8b2a6311c13c7c793bdcebbc96c.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas R-Car X5H SCP FW SDKv4.28.0, v4.31.0, and v4.32.0 advertise a few power domains that crash the system when touched or powered off. Add a quirk to prevent such crashes. As the SCMI power domain IDs are identical for all three versions, the quirk can be shared. Signed-off-by: Geert Uytterhoeven --- Preventing power off could be handled in the MDLC driver, but no-touch cannot. --- drivers/firmware/arm_scmi/power.c | 20 ++++++++++++++++++++ drivers/firmware/arm_scmi/quirks.c | 3 +++ drivers/firmware/arm_scmi/quirks.h | 1 + 3 files changed, 24 insertions(+) diff --git a/drivers/firmware/arm_scmi/power.c b/drivers/firmware/arm_scmi/= power.c index bb5062ab8280e02b..81b9035aa5a2eafe 100644 --- a/drivers/firmware/arm_scmi/power.c +++ b/drivers/firmware/arm_scmi/power.c @@ -12,6 +12,7 @@ =20 #include "protocols.h" #include "notify.h" +#include "quirks.h" =20 /* Updated only after ALL the mandatory features for that version are merg= ed */ #define SCMI_PROTOCOL_SUPPORTED_VERSION 0x30001 @@ -150,6 +151,23 @@ scmi_power_domain_attributes_get(const struct scmi_pro= tocol_handle *ph, return ret; } =20 +#define QUIRK_RCAR_X5H_4_28_BAD_DOMAINS \ + ({ \ + switch (domain) { \ + /* Do not touch */ \ + case 29: /* PD_RC08 */ \ + case 92: /* PD_ACL0 */ \ + case 116: /* PD_CMN */ \ + return -EPERM; \ + \ + /* Do not power off */ \ + case 76: /* PD_AC00 */ \ + if (state =3D=3D SCMI_POWER_STATE_GENERIC_OFF) \ + return -EPERM; \ + break; \ + } \ + }) + static int scmi_power_state_set(const struct scmi_protocol_handle *ph, u32 domain, u32 state) { @@ -157,6 +175,8 @@ static int scmi_power_state_set(const struct scmi_proto= col_handle *ph, struct scmi_xfer *t; struct scmi_power_set_state *st; =20 + SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, QUIRK_RCAR_X5H_4_28_BAD_DOMAI= NS); + ret =3D ph->xops->xfer_get_init(ph, POWER_STATE_SET, sizeof(*st), 0, &t); if (ret) return ret; diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi= /quirks.c index 2b38ba3f59a13c9e..c1a2f58505c1a757 100644 --- a/drivers/firmware/arm_scmi/quirks.c +++ b/drivers/firmware/arm_scmi/quirks.c @@ -172,6 +172,8 @@ struct scmi_quirk { /* Global Quirks Definitions */ DEFINE_SCMI_QUIRK(clock_rates_triplet_out_of_spec, NULL, NULL, NULL); DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-"); +DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL, + "0x10a0000-0x10e0000", "renesas,r8a78000"); =20 /* * Quirks Pointers Array @@ -182,6 +184,7 @@ DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", = NULL, "0x20000-"); static struct scmi_quirk *scmi_quirks_table[] =3D { __DECLARE_SCMI_QUIRK_ENTRY(clock_rates_triplet_out_of_spec), __DECLARE_SCMI_QUIRK_ENTRY(perf_level_get_fc_force), + __DECLARE_SCMI_QUIRK_ENTRY(power_rcar_x5h_4_28_bad_domains), NULL }; =20 diff --git a/drivers/firmware/arm_scmi/quirks.h b/drivers/firmware/arm_scmi= /quirks.h index d8ba60b956522d04..108c8d11f6043a61 100644 --- a/drivers/firmware/arm_scmi/quirks.h +++ b/drivers/firmware/arm_scmi/quirks.h @@ -48,5 +48,6 @@ static inline void scmi_quirks_enable(struct device *dev,= const char *vend, /* Quirk delarations */ DECLARE_SCMI_QUIRK(clock_rates_triplet_out_of_spec); DECLARE_SCMI_QUIRK(perf_level_get_fc_force); +DECLARE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains); =20 #endif /* _SCMI_QUIRKS_H */ --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 785D83876D0; Tue, 21 Apr 2026 18:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795128; cv=none; b=pB1WIPbdwokq+3ICseQWDhpu7JjyRR3cLRBU1HfJIbEehevMczwOm+w0WzsUFPXHv7oeuX4apptw52mJExFXZEm7LFRHK+QCYkrloI66ifdEtQh5aopzfqYT4QM5UFf2oWdr1WMnFMeEkdk9x3JrxEvnE3v4IRQR90pouMGe8VE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795128; c=relaxed/simple; bh=EKhm5N5EJOzTY3hGdBFEEWKdxcNbPJhJMZfobrbkHg0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fQGl16DC33pipWxiDVK9l+maGSugCyb+OtXBmUzuKcz6wvKk51YOs7lUoD31FFslEAyIsYgcajFF8eXX9BnsdCGeXQxhq0TNG8wIP7nRxekCPobT1ZVfAkLbO3HYKB0xpsVt2S4YmNvO2L6hC52+D9KkpCp1yugrNdkLRZOw07U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18295C2BCB0; Tue, 21 Apr 2026 18:12:02 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 02/14] firmware: arm_scmi: quirk: Handle bad clocks on R-Car X5H Date: Tue, 21 Apr 2026 20:11:35 +0200 Message-ID: <24bea8791a53e6c969ef97b506cfec25054099c8.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas R-Car X5H SCP FW SDKv4.28.0, v4.31.0, and v4.32.0 expose a few clocks that do not support the CLOCK_ATTRIBUTES or CLOCK_DESCRIBE_RATES command. Since commit 0d8b0c8068a8ff5f ("firmware: arm_scmi: Harden clock protocol initialization") in scmi/for-linux-next (next-20260319 and later), scmi_clock_attributes_get() or scmi_clock_describe_rates_get() failures are no longer ignored, but prevent the SCMI clock driver from initializing. Hence add a quirk to ignore such failures, like before. As the quirk handling is harmless for unaffected systems, make it generic for all R-Car X5H systems using SCP FW SDKv4.28.0 or later. Signed-off-by: Geert Uytterhoeven --- drivers/firmware/arm_scmi/clock.c | 14 ++++++++++++++ drivers/firmware/arm_scmi/quirks.c | 3 +++ drivers/firmware/arm_scmi/quirks.h | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/= clock.c index ce6f968925af38c0..d530882a0bac88c3 100644 --- a/drivers/firmware/arm_scmi/clock.c +++ b/drivers/firmware/arm_scmi/clock.c @@ -1232,6 +1232,18 @@ static const struct scmi_protocol_events clk_protoco= l_events =3D { .num_events =3D ARRAY_SIZE(clk_events), }; =20 +#define QUIRK_RCAR_X5H_NO_ATTRIBUTES \ + ({ \ + if (ret =3D=3D -EREMOTEIO || ret =3D=3D -EOPNOTSUPP) \ + continue; \ + }) + +#define QUIRK_RCAR_X5H_NO_RATES \ + ({ \ + if (ret =3D=3D -EOPNOTSUPP) \ + ret =3D 0; \ + }) + static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph) { int clkid, ret; @@ -1256,10 +1268,12 @@ static int scmi_clock_protocol_init(const struct sc= mi_protocol_handle *ph) for (clkid =3D 0; clkid < cinfo->num_clocks; clkid++) { cinfo->clkds[clkid].id =3D clkid; ret =3D scmi_clock_attributes_get(ph, clkid, cinfo); + SCMI_QUIRK(clock_rcar_x5h_no_attributes, QUIRK_RCAR_X5H_NO_ATTRIBUTES); if (ret) return ret; =20 ret =3D scmi_clock_describe_rates_get(ph, clkid, cinfo); + SCMI_QUIRK(clock_rcar_x5h_no_attributes, QUIRK_RCAR_X5H_NO_RATES); if (ret) return ret; } diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi= /quirks.c index c1a2f58505c1a757..e27c21b14220ab5f 100644 --- a/drivers/firmware/arm_scmi/quirks.c +++ b/drivers/firmware/arm_scmi/quirks.c @@ -171,6 +171,8 @@ struct scmi_quirk { =20 /* Global Quirks Definitions */ DEFINE_SCMI_QUIRK(clock_rates_triplet_out_of_spec, NULL, NULL, NULL); +DEFINE_SCMI_QUIRK(clock_rcar_x5h_no_attributes, "Renesas", NULL, "0x10a000= 0-", + "renesas,r8a78000"); DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-"); DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL, "0x10a0000-0x10e0000", "renesas,r8a78000"); @@ -183,6 +185,7 @@ DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Ren= esas", NULL, */ static struct scmi_quirk *scmi_quirks_table[] =3D { __DECLARE_SCMI_QUIRK_ENTRY(clock_rates_triplet_out_of_spec), + __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_no_attributes), __DECLARE_SCMI_QUIRK_ENTRY(perf_level_get_fc_force), __DECLARE_SCMI_QUIRK_ENTRY(power_rcar_x5h_4_28_bad_domains), NULL diff --git a/drivers/firmware/arm_scmi/quirks.h b/drivers/firmware/arm_scmi= /quirks.h index 108c8d11f6043a61..67818b6cf0909f8e 100644 --- a/drivers/firmware/arm_scmi/quirks.h +++ b/drivers/firmware/arm_scmi/quirks.h @@ -47,6 +47,7 @@ static inline void scmi_quirks_enable(struct device *dev,= const char *vend, =20 /* Quirk delarations */ DECLARE_SCMI_QUIRK(clock_rates_triplet_out_of_spec); +DECLARE_SCMI_QUIRK(clock_rcar_x5h_no_attributes); DECLARE_SCMI_QUIRK(perf_level_get_fc_force); DECLARE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains); =20 --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F35F3A9DA9; Tue, 21 Apr 2026 18:12:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795133; cv=none; b=Ize3EPi4s4mg0x/QWNsisRIabILLTlu5J9hw0lUH/EL/jh6rRVld5q1dErSD816uSDQPUjxnuU3rM8sODItEGV/sKbcPtoxr31WtYJpZ1E4D5SbfxEiU6ddaIG0yS7SBpz+s0AD2iK8dUz93oEMu+qLkJQFjfxhonZ1pdpavILo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795133; c=relaxed/simple; bh=NkOwwlNHq7+Ht8Nh8QJy30xjiiGIR5iUBXMJt/v+Al8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HwX9VFtbuCeb2rWwr9pgAFcWKo/zELcr0UGVyELeUybtjLuetWo94sg30W0EqScfDOL5zDhqrlb3NJ5o27R+IVCrXaOoyViOShyxzxjFDlKkZZPJHbfr28mIEeUP1a1OVrbMIxiB238/uR0SsxTR5SktRg+e9A9PjG07VrhbbsM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EED0C2BCB8; Tue, 21 Apr 2026 18:12:08 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 03/14] firmware: arm_scmi: quirk: Handle critical clocks on R-Car X5H Date: Tue, 21 Apr 2026 20:11:36 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas R-Car X5H SCP FW SDKv4.28.0, v4.31.0, and v4.32.0 advertise a few clocks that crash the system when disabled. Add quirks to prevent such crashes. As SCMI clock IDs are identical for SDKv4.31.0 and v4.32.0, the quirk for these two versions can be shared. Signed-off-by: Geert Uytterhoeven --- Some of these could be handled by improving hardware descriptions in DT, or by the CPG and MDLC drivers. --- drivers/firmware/arm_scmi/clock.c | 23 +++++++++++++++++++++++ drivers/firmware/arm_scmi/quirks.c | 6 ++++++ drivers/firmware/arm_scmi/quirks.h | 2 ++ 3 files changed, 31 insertions(+) diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/= clock.c index d530882a0bac88c3..4fec8c3216df7a51 100644 --- a/drivers/firmware/arm_scmi/clock.c +++ b/drivers/firmware/arm_scmi/clock.c @@ -920,6 +920,26 @@ scmi_clock_config_set_v2(const struct scmi_protocol_ha= ndle *ph, u32 clk_id, return ret; } =20 +#define QUIRK_RCAR_X5H_4_28_CRIT_CLOCKS \ + ({ \ + switch (clk_id) { \ + case 468: /* MDLC_INTAP0 */ \ + case 498: /* MDLC_APRTMGINT0 */ \ + case 840: /* CLK_ZD_APU0 */ \ + return -EPERM; \ + } \ + }) + +#define QUIRK_RCAR_X5H_4_31_CRIT_CLOCKS \ + ({ \ + switch (clk_id) { \ + case 464: /* MDLC_INTAP0 */ \ + case 494: /* MDLC_APRTMGINT0 */ \ + case 836: /* CLK_ZD_APU0 */ \ + return -EPERM; \ + } \ + }) + static int scmi_clock_enable(const struct scmi_protocol_handle *ph, u32 cl= k_id, bool atomic) { @@ -950,6 +970,9 @@ static int scmi_clock_disable(const struct scmi_protoco= l_handle *ph, u32 clk_id, if (clk->state_ctrl_forbidden) return -EACCES; =20 + SCMI_QUIRK(clock_rcar_x5h_4_28_crit_clocks, QUIRK_RCAR_X5H_4_28_CRIT_CLOC= KS); + SCMI_QUIRK(clock_rcar_x5h_4_31_crit_clocks, QUIRK_RCAR_X5H_4_31_CRIT_CLOC= KS); + return ci->clock_config_set(ph, clk_id, CLK_STATE_DISABLE, NULL_OEM_TYPE, 0, atomic); } diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi= /quirks.c index e27c21b14220ab5f..4ca6d06f85ebc7b2 100644 --- a/drivers/firmware/arm_scmi/quirks.c +++ b/drivers/firmware/arm_scmi/quirks.c @@ -173,6 +173,10 @@ struct scmi_quirk { DEFINE_SCMI_QUIRK(clock_rates_triplet_out_of_spec, NULL, NULL, NULL); DEFINE_SCMI_QUIRK(clock_rcar_x5h_no_attributes, "Renesas", NULL, "0x10a000= 0-", "renesas,r8a78000"); +DEFINE_SCMI_QUIRK(clock_rcar_x5h_4_28_crit_clocks, "Renesas", NULL, "0x10a= 0000", + "renesas,r8a78000"); +DEFINE_SCMI_QUIRK(clock_rcar_x5h_4_31_crit_clocks, "Renesas", NULL, + "0x10d0000-0x10e0000", "renesas,r8a78000"); DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-"); DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL, "0x10a0000-0x10e0000", "renesas,r8a78000"); @@ -186,6 +190,8 @@ DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Ren= esas", NULL, static struct scmi_quirk *scmi_quirks_table[] =3D { __DECLARE_SCMI_QUIRK_ENTRY(clock_rates_triplet_out_of_spec), __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_no_attributes), + __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_4_28_crit_clocks), + __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_4_31_crit_clocks), __DECLARE_SCMI_QUIRK_ENTRY(perf_level_get_fc_force), __DECLARE_SCMI_QUIRK_ENTRY(power_rcar_x5h_4_28_bad_domains), NULL diff --git a/drivers/firmware/arm_scmi/quirks.h b/drivers/firmware/arm_scmi= /quirks.h index 67818b6cf0909f8e..56adb5fa87de0127 100644 --- a/drivers/firmware/arm_scmi/quirks.h +++ b/drivers/firmware/arm_scmi/quirks.h @@ -48,6 +48,8 @@ static inline void scmi_quirks_enable(struct device *dev,= const char *vend, /* Quirk delarations */ DECLARE_SCMI_QUIRK(clock_rates_triplet_out_of_spec); DECLARE_SCMI_QUIRK(clock_rcar_x5h_no_attributes); +DECLARE_SCMI_QUIRK(clock_rcar_x5h_4_28_crit_clocks); +DECLARE_SCMI_QUIRK(clock_rcar_x5h_4_31_crit_clocks); DECLARE_SCMI_QUIRK(perf_level_get_fc_force); DECLARE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains); =20 --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49DC228504D; Tue, 21 Apr 2026 18:12:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795138; cv=none; b=WWU8oweTcqEd3oXgPzEYeraicBga2OouaI3i/Dn527k1HF0Rv836nngXkxknUPbP9jOpeCzXIGw0/jIopLoVloLvamZibPh/PoKVS67gLc8lrxbxfDzHBbVtmJzjOeQM2J3nHo5aT4mUxQbEQln9eZ17bAc5ywh62V1ap7d+0D0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795138; c=relaxed/simple; bh=fblMpjqFfnjUAr+HNDhVWeUb9w8+sGgLDBS5LTLkD1M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ddakym7sqJIUpFDGKXHSOnfVV4Z8u2Lz7duIEAG6cjPZbiWy8GSzCTEOpTPm3XQz3x5U6mLHXgzMoZBptYLtpVGRvBdcLxRiRQ2X6DIXeZARrSBjXi6kXeu4t/KlX06YD4DqOwXnAeotP4JYbpi56nJucUBgRi93+x5/8OTiMok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F5B2C2BCB0; Tue, 21 Apr 2026 18:12:13 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 04/14] arm64: dts: renesas: ironhide: Enable SCMI devpd, sys, and reset Date: Tue, 21 Apr 2026 20:11:37 +0200 Message-ID: <2eb3c62df7b6ccedb525569fe34c10403e2fdcf5.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SCP FW SDKv4.28.0 and later for Renesas R-Car X5H Ironhide not only implements the SCMI base and clock management protocols, but also the SCMI power domain, system power, and reset domain management protocols. Enable support for the latter by adding the corresponding SCMI protocol subnodes. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64= /boot/dts/renesas/r8a78000-ironhide.dts index e2470257d2f32a03..2fb9557a7eb9dbb7 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts @@ -31,10 +31,24 @@ scmi: scmi { #address-cells =3D <1>; #size-cells =3D <0>; =20 + scmi_devpd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi_sys: protocol@12 { + reg =3D <0x12>; + }; + scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; }; + + scmi_reset: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; }; }; =20 --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60AAA35972; Tue, 21 Apr 2026 18:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795143; cv=none; b=YCzT/PborJy5BBSRGb+Q4XkqnDrAd/UvqkeCC1E+EAMEPrGLD0wiRlcqbM/YBj1koYVseqGDwmGG+E+qb2YLWxGQy0X1ahw23oZ7pldgrjujrZOWKT19N4dPF8NqEHcCOhtwp6ZBVHSIge2n3HYgX5Va51cmqAyc8cjb2QyechU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795143; c=relaxed/simple; bh=X663d4IHOAyYFQoCnPaOg4te2XgqLTCjAjyVj26Dxeg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K26S61DcHqufLH9PIsijzvbPIeKzzGOjvveiRz9El6oXZoaGMzkb8e9cRZc3IJfJNX6DnEEvVCoFcN2j175MDyu3r6zFHjMhCzCWv1A/MRX1A4S5D6J+gSQaTjlcnmckvcgFK0NdJFQPY4dknqmxO+vNwl8KaILfDdobw/ZfIWM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A668C2BCB0; Tue, 21 Apr 2026 18:12:18 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 05/14] firmware: arm_scmi: Add scmi_get_base_info() Date: Tue, 21 Apr 2026 20:11:38 +0200 Message-ID: <72e2a0e7a5abda02fe36b3f5851842f7a77b2593.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently non-SCMI drivers cannot find out what the specific versions of each SCMI provider implementation on the running system are. However, different versions may use different ABIs (e.g. different clock IDs), or behave different, requiring remapping or workarounds in other drivers. Add a public function to obtain base protocol information for the selected SCMI provider. This will be used by the R-Car X5H Clock Pulse Generator and Module Controller drivers. Signed-off-by: Geert Uytterhoeven --- drivers/firmware/arm_scmi/driver.c | 31 ++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 8 ++++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi= /driver.c index 3e0d975ec94c4485..dfa8961775aa952d 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -3504,6 +3504,37 @@ int scmi_inflight_count(const struct scmi_handle *ha= ndle) } } =20 +/** + * scmi_get_base_info() - Get SCMI base protocol information + * + * @of_node: pointer to a device node for an SCMI provider + * @version: pointer to write base protocol information + * + * Check if an SCMI device has been instantiated for the passed device node + * pointer, and, if found, return its base info. + + * Return: 0 on Success or -ENOENT. + */ +int scmi_get_base_info(struct device_node *of_node, + struct scmi_base_info *version) +{ + struct scmi_info *info; + int ret =3D -ENOENT; + + mutex_lock(&scmi_list_mutex); + list_for_each_entry(info, &scmi_list, node) { + if (info->dev->of_node =3D=3D of_node) { + *version =3D info->version; + ret =3D 0; + break; + } + } + mutex_unlock(&scmi_list_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(scmi_get_base_info); + static int __init scmi_driver_init(void) { scmi_quirks_initialize(); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 49cc39e0cbca5a0b..52eba920de264bd7 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -972,6 +972,8 @@ struct scmi_driver { int scmi_driver_register(struct scmi_driver *driver, struct module *owner, const char *mod_name); void scmi_driver_unregister(struct scmi_driver *driver); +int scmi_get_base_info(struct device_node *of_node, + struct scmi_base_info *version); #else static inline int scmi_driver_register(struct scmi_driver *driver, struct module *owner, @@ -981,6 +983,12 @@ scmi_driver_register(struct scmi_driver *driver, struc= t module *owner, } =20 static inline void scmi_driver_unregister(struct scmi_driver *driver) {} + +static inline int scmi_get_base_info(struct device_node *of_node, + struct scmi_base_info *version) +{ + return -ENOENT; +} #endif /* CONFIG_ARM_SCMI_PROTOCOL */ =20 #define scmi_register(driver) \ --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B60235972; Tue, 21 Apr 2026 18:12:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795148; cv=none; b=Xcr9d2HBbDH+hArLQ5uTfK1mUfK3NudnkXu3IjnVvNIto1PMUcqXNkeHdxvQ4/2qcGpJ/U8RUvyf2cnxham3OQOqxMKMDBizc7JkBTL6tOAOnnFS0FF/ycWfFBqzmx/9JzN7ZSaNrOr2dozhqD8pQ4DDNgGBldnsu20rlikjwBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795148; c=relaxed/simple; bh=J7n4y54VacqyWcZf9mvl8m2nBKYygVLXUdYoceQi8fI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aE7Zc1DYaN6jN+KruNY0shE8cnuT/hAdg65nJ6O84YL0xUfBiMiM6m9aYzPinbhznZRxYvkY6K/r/2VaV4aHJoptCdtsSi5ViO2bN2yFd3pv93t2MPYPngr2YEF21oQ7aM7/unBdk8w1XMZQPTG+AIE1YWoLTqv2WkjzRfU29Sw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 764A8C2BCB4; Tue, 21 Apr 2026 18:12:23 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 06/14] of: property: fw_devlink: Add support for firmware Date: Tue, 21 Apr 2026 20:11:39 +0200 Message-ID: <25ce04eb49a5caba4117dbf776edf70a00f07384.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Let fw_devlink create device links between consumers and suppliers of firmware, and enforce these dependencies. This prevents probing of drivers before the firmware they depend on becomes available, thus avoiding unneeded probe deferrals. Signed-off-by: Geert Uytterhoeven --- Written for the upcoming R-Car X5H Clock Pulse Generator and Module Controller drivers and their dependency on SCMI, but the existing Raspberry Pi power domain driver should benefit from this, too. --- drivers/of/property.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/of/property.c b/drivers/of/property.c index 136946f8b746f745..34aeba20040348d6 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1378,6 +1378,7 @@ DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-cells") DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells") DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells") DEFINE_SIMPLE_PROP(extcon, "extcon", NULL) +DEFINE_SIMPLE_PROP(firmware, "firmware", NULL) DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", "#nvmem-cell-cells") DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells") DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL) @@ -1527,6 +1528,7 @@ static const struct supplier_bindings of_supplier_bin= dings[] =3D { { .parse_prop =3D parse_power_domains, }, { .parse_prop =3D parse_hwlocks, }, { .parse_prop =3D parse_extcon, }, + { .parse_prop =3D parse_firmware, }, { .parse_prop =3D parse_nvmem_cells, }, { .parse_prop =3D parse_phys, }, { .parse_prop =3D parse_wakeup_parent, }, --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C4CA35972; Tue, 21 Apr 2026 18:12:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795153; cv=none; b=mE++r653Gz9O9UUXw8rh91TKxkZ80GYOXPw2LmvJ7gkhX96x0GANp0VXHv0YmhpY2OA24JpMZucsVFrjEZazQj3Shjzucz4tqLrk6W+PaOKEyRs+EPd0mxHOQKwB3vbiLBf6fywhMU1K7pViMy+5pYxaMUC82/EOA2j+DNPtTwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795153; c=relaxed/simple; bh=mDGCKRZdRELPOfMUgw7CSc0CSBsJ4l99yngFmZ0BVrw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YtPwwh+1chs/LGJFeG09HyEc9eFflrYpOqED2GgIIs2E6/5eAms33qPDx9+kkpLe9I3PPdBORpjy7Qk2XgWAEIPDovCVYJLHfqMMpu3egjZlYjxx+ggNrf0P5g4A25etwTQLjHcMIdm954ujEgEBvzv6s28oooRs51q2qk4jECs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85567C2BCB0; Tue, 21 Apr 2026 18:12:28 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 07/14] pmdomain: Make genpd_get_from_provider() public Date: Tue, 21 Apr 2026 20:11:40 +0200 Message-ID: <567a45c25e575ef1bf5fa9b27a78e94d21c61851.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike the corresponding function in the clock subsystem (of_clk_get_from_provider()), genpd_get_from_provider() is private, and thus cannot be used by PM Domain drivers. Make it public, so it be used by the R-Car X5H Module Controller driver. Signed-off-by: Geert Uytterhoeven --- drivers/pmdomain/core.c | 4 ++-- include/linux/pm_domain.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/core.c b/drivers/pmdomain/core.c index 4d32fc676aaf53cf..23c7cd480a7e026d 100644 --- a/drivers/pmdomain/core.c +++ b/drivers/pmdomain/core.c @@ -2900,8 +2900,7 @@ EXPORT_SYMBOL_GPL(of_genpd_del_provider); * Returns a valid pointer to struct generic_pm_domain on success or ERR_P= TR() * on failure. */ -static struct generic_pm_domain *genpd_get_from_provider( - const struct of_phandle_args *genpdspec) +struct generic_pm_domain *genpd_get_from_provider(const struct of_phandle_= args *genpdspec) { struct generic_pm_domain *genpd =3D ERR_PTR(-ENOENT); struct of_genpd_provider *provider; @@ -2923,6 +2922,7 @@ static struct generic_pm_domain *genpd_get_from_provi= der( =20 return genpd; } +EXPORT_SYMBOL_GPL(genpd_get_from_provider); =20 /** * of_genpd_add_device() - Add a device to an I/O PM domain diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index b299dc0128d65ee5..568aebf51d830210 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -458,6 +458,7 @@ int of_genpd_add_provider_simple(struct device_node *np, int of_genpd_add_provider_onecell(struct device_node *np, struct genpd_onecell_data *data); void of_genpd_del_provider(struct device_node *np); +struct generic_pm_domain *genpd_get_from_provider(const struct of_phandle_= args *genpdspec); int of_genpd_add_device(const struct of_phandle_args *args, struct device = *dev); int of_genpd_add_subdomain(const struct of_phandle_args *parent_spec, const struct of_phandle_args *subdomain_spec); @@ -488,6 +489,12 @@ static inline int of_genpd_add_provider_onecell(struct= device_node *np, =20 static inline void of_genpd_del_provider(struct device_node *np) {} =20 +static inline struct generic_pm_domain *genpd_get_from_provider( + const struct of_phandle_args *genpdspec) +{ + return ERR_PTR(-ENODEV); +} + static inline int of_genpd_add_device(const struct of_phandle_args *args, struct device *dev) { --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A6AE3A9DAB; Tue, 21 Apr 2026 18:12:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795158; cv=none; b=OiSArZ4cCcs+1dDkDMzD/qexnM56f+vSn4Pbwy6zrGKlLB2BL3cSNThlgn7WZefqP5Uod+jQup4yn6EAVRkQMxjALCb3RxsXW7EMKXL/w0pNcsC1d5dW6BH4tIYMuENYvFdILFlgtBC6/hRIRlSl7cHmRFrqvYf+CPvZudWrkp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795158; c=relaxed/simple; bh=Otww8j8idL7DQsJ/09F2hxIYpv1fu0aeOBNW9omx36U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W0VPQ+Sy/Hud0gNh/OtY/d+GBvxZrjmlehlJIMyDJ3Ql8bPTQ+TyR27jJiURbnzSyoHuD1tyFsTcL6PFBKGe0JQB4nKIqYfrnsfHK1+NDTRgzwkfD7bQLZ5ND65rbLV85nj+rQADqUpxstfP3ei3KzF5//5ygJSCtYLXaIaGKmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C7D0C2BCB5; Tue, 21 Apr 2026 18:12:33 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 08/14] reset: Add reset_controller_get_provider() Date: Tue, 21 Apr 2026 20:11:41 +0200 Message-ID: <87edde434e1760bbe9e2741856724301d02a4fc8.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The reset subsystem differs from the clock subsystem in multiple ways: 1. It does not provide a public way to lookup resets from a reset provider (clock has of_clk_get_from_provider()), 2. The xlate callback does not return a reset object, but merely an index, which is converted to a reset object by the reset core. Hence add a public helper reset_controller_get_provider(), which just returns the provider, and will be used by the R-Car X5H Module Controller driver. Signed-off-by: Geert Uytterhoeven --- drivers/reset/core.c | 11 +++++++++++ include/linux/reset-controller.h | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/reset/core.c b/drivers/reset/core.c index 38e189d04d09b270..57c427bb33b322e2 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -1135,6 +1135,17 @@ __reset_find_rcdev(const struct fwnode_reference_arg= s *args, bool gpio_fallback) return NULL; } =20 +struct reset_controller_dev * +reset_controller_get_provider(struct fwnode_handle *fwnode) +{ + struct fwnode_reference_args args =3D { .fwnode =3D fwnode }; + + guard(mutex)(&reset_list_mutex); + + return __reset_find_rcdev(&args, false); +} +EXPORT_SYMBOL_GPL(reset_controller_get_provider); + struct reset_control * __fwnode_reset_control_get(struct fwnode_handle *fwnode, const char *id, i= nt index, enum reset_control_flags flags) diff --git a/include/linux/reset-controller.h b/include/linux/reset-control= ler.h index 52a5a4e81f184407..0c17a36466115ba6 100644 --- a/include/linux/reset-controller.h +++ b/include/linux/reset-controller.h @@ -74,6 +74,7 @@ void reset_controller_unregister(struct reset_controller_= dev *rcdev); struct device; int devm_reset_controller_register(struct device *dev, struct reset_controller_dev *rcdev); +struct reset_controller_dev *reset_controller_get_provider(struct fwnode_h= andle *fwnode); #else static inline int reset_controller_register(struct reset_controller_dev *r= cdev) { @@ -89,6 +90,11 @@ static inline int devm_reset_controller_register(struct = device *dev, { return 0; } + +static inline struct reset_controller_dev *reset_controller_get_provider(s= truct fwnode_handle *fwnode) +{ + return NULL; +} #endif =20 #endif --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EA30347BC6; Tue, 21 Apr 2026 18:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795163; cv=none; b=ab81uiH6v9P7xcCkrruwffknFz+pRPgw6I2yvjrQ8a/jcG/sL4r+sDFSAZhrIRNLMGDnGZsVidItmb5KBB5A79HXBunSRojZOD+zDPjfNifTohkJ0oIH1s86PkYvgv4WcXXBt50T29bbdUsU4oz10CXOrtzRwUNCShQwSQANBb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795163; c=relaxed/simple; bh=CrSp/pZoa+rfAfIByGc+fsW1M4yQUQHnQztAQ+i9N9E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GqK3aiOxQxIUiiKKMtA8qhs50tTwZ4pyoyfiMZnqVd6MCREL2YhBOfVzjqY1aBEhMUrww1HhE1qG7ODXp1ggJc1sAbMHmzEwra07qbmUZI8vi+4i4xV9TqA9Ndg7NmMntaBYGdpBVywweSKJql73ROHe9vUc4oCGuDM68YDcOZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id AEC01C2BCB4; Tue, 21 Apr 2026 18:12:38 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 09/14] dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator Date: Tue, 21 Apr 2026 20:11:42 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for the Renesas R-Car X5H Clock Pulse Generator, and add definitions for a very limited and preliminary set of clocks. Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Tested-by: Marek Vasut --- .../bindings/clock/renesas,r8a78000-cpg.yaml | 62 +++++++++++++++++++ .../dt-bindings/clock/renesas,r8a78000-cpg.h | 15 +++++ 2 files changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7800= 0-cpg.yaml create mode 100644 include/dt-bindings/clock/renesas,r8a78000-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.y= aml b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml new file mode 100644 index 0000000000000000..fc499e7cf52e4f0c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car X5H Clock Pulse Generator + +maintainers: + - Geert Uytterhoeven + +description: + The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillator= s, + PLL circuits, clock dividers and clock control circuits. It provides va= rious + clocks for other modules. + +properties: + compatible: + const: renesas,r8a78000-cpg + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: extal + - const: extalr + + '#clock-cells': + description: + The single clock specifier cell must be the clock number, as defined= in + . + const: 1 + + firmware: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Reference to the SCMI firmware device node on systems where SCMI mus= t be + used instead of direct hardware access. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@c1320000 { + compatible =3D "renesas,r8a78000-cpg"; + reg =3D <0xc1320000 0x10000>; + clocks =3D <&extal_clk>, <&extalr_clk>; + clock-names =3D "extal", "extalr"; + #clock-cells =3D <1>; + firmware =3D <&scmi>; + }; diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-= bindings/clock/renesas,r8a78000-cpg.h new file mode 100644 index 0000000000000000..8c8bc4d1feac6d26 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Glider bv + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ + +/* R-Car X5H CPG Clocks */ + +// FIXME Preliminary +#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0 +#define R8A78000_CPG_SGASYNCD16_PERW_BUS 1 +#define R8A78000_CPG_MSOCK_PERW_BUS 2 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */ --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B55FC3AA187; Tue, 21 Apr 2026 18:12:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795168; cv=none; b=P+PV5dTh9lUMI9ZdZX20Q+Vb2pNZJBOVi2sQnQLUHqBAWjvlvLE2zCfLU31brlHq64ZDHUI2CBwEyDmoi/IJZ2nJBh7BKCrCdDqKflA+g2DHCOiIMVQLsd+el9x/WexKUu2mCZWTac3Qrsc5H3psX4+99hAOM8ViIX7HjhB/VIU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795168; c=relaxed/simple; bh=QrKi5FpD9xDv9alKjpbtADx04oQH6RcZFwBpFy0y4bA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lgaEaYudq81skSYk+hFw529EUW43DTrN4gWdxyuTG2uin22g6REmo8EcI/Q36k1zYzV61JAs7k4DMkCD30PqqTwYmvCVv5tY6Ru0O5EJ7ak4W/GR91cfo4a8b6WFFTpNd1moDfTqgrHekup/ItBe4M2xrBl/YJvA9xvXvmQTEg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD3D1C2BCC9; Tue, 21 Apr 2026 18:12:43 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 10/14] dt-bindings: power: Document Renesas R-Car X5H Module Controller Date: Tue, 21 Apr 2026 20:11:43 +0200 Message-ID: <053c312d07445517d8f9c84bfe3cc8fb72d4cd9a.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Renesas R-Car X5H Module Controllers, and add definitions for power domains not backed by registers. Signed-off-by: Geert Uytterhoeven --- .../bindings/power/renesas,r8a78000-mdlc.yaml | 63 +++++++++++++++++++ .../dt-bindings/power/renesas,r8a78000-mdlc.h | 16 +++++ 2 files changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/renesas,r8a7800= 0-mdlc.yaml create mode 100644 include/dt-bindings/power/renesas,r8a78000-mdlc.h diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.= yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml new file mode 100644 index 0000000000000000..c3075bb308962f59 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/renesas,r8a78000-mdlc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car X5H Module Controller + +maintainers: + - Geert Uytterhoeven + +description: + Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provid= es + Power Gating for up to 64 Power Domains, and Module Standby and Reset fo= r up + to 256 modules in the Power Domain of each Module hierarchy. + +properties: + compatible: + const: renesas,r8a78000-mdlc + + reg: + maxItems: 1 + + '#power-domain-cells': + description: | + - The first power domain specifier cell must be either the Module + Power Domain Gating (MPDG) register index (0x00-0x3f) from the + datasheet, or a Power Domain number, as defined in + , + - The second power domain specifier cell must be the module number + (0x00-0xff), composed of the Module System Reset (MSRES) register = index + in the high nibble, and the Module Reset Destination bitfield inde= x in + the low nibble. + const: 2 + + '#reset-cells': + description: + The single reset specifier cell must be the module number (0x00-0xff= ). + const: 1 + + firmware: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Reference to the SCMI firmware device node on systems where SCMI mus= t be + used instead of direct hardware access. + +required: + - compatible + - reg + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + system-controller@c3060000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0xc3060000 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + firmware =3D <&scmi>; + }; diff --git a/include/dt-bindings/power/renesas,r8a78000-mdlc.h b/include/dt= -bindings/power/renesas,r8a78000-mdlc.h new file mode 100644 index 0000000000000000..31aa4935a7c5cf94 --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a78000-mdlc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Glider bv + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ + +/* R-Car X5H MDLC Power Domains */ + +#define R8A78000_MDLC_PD_AON 0x40 +#define R8A78000_MDLC_PD_SCP 0x41 +#define R8A78000_MDLC_PD_APL 0x42 +#define R8A78000_MDLC_PD_CMN 0x43 +#define R8A78000_MDLC_PD_ACL 0x44 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ */ --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 960A33A9DA9; Tue, 21 Apr 2026 18:12:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795173; cv=none; b=eZLaNSrXcJAz3o+IUMjJvZp3KlfH6d8ICinXmmH0LJ2UBfmuEMwPzMiXwvfy55P8Ih/aPvhkv5ssQlqiSkn2fdp3TcsrUNAADZaZtXSpLjbLjkF2XUY8FfGuYqoM7hHCQN7y3XC5wUwCWZsUYAUBxD7Ej9yjiltQgZA2pzZHgfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795173; c=relaxed/simple; bh=6pRZnJIC94Jf+41v26DXBQWXtwH5INF5YRQAL64SmLI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=deEK6aJ37dbvT+vnzDCKR8u5qHnsJHduSmjFCDl/GnT6HT2YCznEXjfeE1wz4TRVQetnF7DRItlY4CuAOgpm+DCIBuCgVpPgErMqaVr6f4nK0grlUc3A/cIxuoJsNYGCS6lh6XJ+VWDaNb5SlObV2vw/o7h7kJU7UbR1dkc9rgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAD1BC2BCB0; Tue, 21 Apr 2026 18:12:48 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 11/14] clk: renesas: Add R-Car X5H CPG SCMI remapping driver Date: Tue, 21 Apr 2026 20:11:44 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a proof-of-concept Clock Pulse Generator driver for the R-Car X5H (R8A78000) SoC, using tables to remap from hardware clock IDs to SCMI clock IDs. Some SCMI clocks do not support the SCMI CLOCK_ATTRIBUTES command, and are thus not usable from Linux. Register a bunch of fixed-rate clocks, and use them as replacements for SCMI clocks that are known to be unusable. For now this contains preliminary support for SCP FW SDKv4.28.0, v4.31.0, and v4.32.0. As SCMI clock IDs are identical for SDKv4.31.0 and v4.32.0, r8a78000_cpg_fw_4_31_0[] applies to both of them. Suggested-by: Marek Vasut Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a78000-cpg.c | 335 +++++++++++++++++++++++++++++ 3 files changed, 340 insertions(+) create mode 100644 drivers/clk/renesas/r8a78000-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 0203ecbb38825f13..f0482bdfc4616cfa 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -34,6 +34,7 @@ config CLK_RENESAS select CLK_R8A779F0 if ARCH_R8A779F0 select CLK_R8A779G0 if ARCH_R8A779G0 select CLK_R8A779H0 if ARCH_R8A779H0 + select CLK_R8A78000 if ARCH_R8A78000 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 @@ -176,6 +177,9 @@ config CLK_R8A779H0 bool "R-Car V4M clock support" if COMPILE_TEST select CLK_RCAR_GEN4_CPG =20 +config CLK_R8A78000 + bool "R-Car X5H clock support" if COMPILE_TEST + config CLK_R9A06G032 bool "RZ/N1D clock support" if COMPILE_TEST =20 diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index bd2bed91ab291d72..4f76f8c402ffe9a3 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) +=3D r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) +=3D r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779G0) +=3D r8a779g0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779H0) +=3D r8a779h0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A78000) +=3D r8a78000-cpg.o obj-$(CONFIG_CLK_R9A06G032) +=3D r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G043) +=3D r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) +=3D r9a07g044-cpg.o diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78= 000-cpg.c new file mode 100644 index 0000000000000000..844d909bbee2adbb --- /dev/null +++ b/drivers/clk/renesas/r8a78000-cpg.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car X5H Clock Pulse Generator + * + * Copyright (C) 2026 Glider bv + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct clk_map_in { + int dt_id; /* DT binding clock ID */ + u32 fw_id; /* SCMI firmware clock ID */ +}; + +struct clk_map { + int dt_id; /* DT binding clock ID */ + u32 fw_id; /* SCMI firmware clock ID */ + struct clk_hw *hw; +}; + +struct fw_map { + u32 impl_ver; + const struct clk_map_in *map; +}; + +enum fixed_clk { + FIXED_CLK_66M, + FIXED_CLK_266M, + NUM_FIXED_CLKS +}; + +static const unsigned long fixed_clk_rates[NUM_FIXED_CLKS] =3D { + [FIXED_CLK_66M] =3D 66666000, + [FIXED_CLK_266M] =3D 266660000, +}; + +#define FIXED_CLK_OFFSET 0x80000000 +#define FIXED_CLK(rate) FIXED_CLK_OFFSET + FIXED_CLK_ ## rate + +/** + * struct r8a78000_cpg_priv - Clock Pulse Generator Private Data + * + * @dev: CPG device + * @scmi_clk_np: Device node in DT for the SCMI firmware clock protocol + * @map: Mapping from DT clock IDs to SCMI clocks + * @fixed_hws: Fixed rate clocks used to replace SCMI clocks that do not + * support the SCMI CLOCK_ATTRIBUTES command + */ +struct r8a78000_cpg_priv { + struct device *dev; + struct device_node *scmi_clk_np; + const struct clk_map *map; + struct clk_hw *fixed_hws[NUM_FIXED_CLKS]; +}; + +static const struct clk_map *clk_map_find(const struct clk_map *map, u32 i= d) +{ + if (!map) + return NULL; + + for (; map->dt_id >=3D 0; map++) { + if (map->dt_id =3D=3D id) + return map; + } + + return NULL; +} + +static struct clk_hw *r8a78000_clk_get(struct of_phandle_args *spec, + void *data) +{ + struct r8a78000_cpg_priv *priv =3D data; + struct device *dev =3D priv->dev; + const struct clk_map *map; + struct clk_hw *hw; + u32 id; + + if (spec->args_count !=3D 1) + return ERR_PTR(-EINVAL); + + id =3D spec->args[0]; + + map =3D clk_map_find(priv->map, id); + if (!map) { + dev_err(dev, "Unknown clock %u\n", id); + return ERR_PTR(-ENOENT); + } + + if (map->fw_id < FIXED_CLK_OFFSET) + dev_dbg(dev, "Mapping DT clock %u to SCMI clock %u\n", id, + map->fw_id); + else + dev_dbg(dev, "Mapping DT clock %u to fixed clock %u\n", id, + map->fw_id - FIXED_CLK_OFFSET); + + hw =3D map->hw; + if (!hw) { + /* CLOCK_ATTRIBUTES is not supported */ + dev_err(dev, "Clock %u is not available\n", id); + return ERR_PTR(-ENOENT); + } + + dev_dbg(dev, "clock %u is %s at %lu Hz\n", id, clk_hw_get_name(hw), + clk_hw_get_rate(hw)); + + return hw; +} + +static struct device_node *scmi_find_proto(struct device_node *scmi, u32 p= roto) +{ + for_each_available_child_of_node_scoped(scmi, child) { + u32 reg; + + if (of_property_read_u32(child, "reg", ®)) + continue; + + if (reg =3D=3D proto) + return_ptr(child); + } + + return NULL; +} + +static void unregister_fixed_clks(void *data) +{ + struct r8a78000_cpg_priv *priv =3D data; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(priv->fixed_hws); i++) + clk_hw_unregister_fixed_rate(priv->fixed_hws[i]); +} + +static int register_fixed_clks(struct r8a78000_cpg_priv *priv) +{ + struct device *dev =3D priv->dev; + unsigned long rate; + struct clk_hw *hw; + const char *name; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(fixed_clk_rates); i++) { + rate =3D fixed_clk_rates[i]; + name =3D devm_kasprintf(dev, GFP_KERNEL, "cpg-%lu", rate); + if (!name) + return -ENOMEM; + + hw =3D clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); + if (IS_ERR(hw)) { + while (i-- > 0) + clk_hw_unregister_fixed_rate(priv->fixed_hws[i]); + return PTR_ERR(hw); + } + + priv->fixed_hws[i] =3D hw; + } + + return devm_add_action_or_reset(dev, unregister_fixed_clks, priv); +} + +static const struct clk_map *fill_clk_map(struct r8a78000_cpg_priv *priv, + const struct clk_map_in *map_in) +{ + struct of_phandle_args scmi_spec; + struct device *dev =3D priv->dev; + struct clk_map *map; + struct clk_hw *hw; + struct clk *clk; + unsigned int i; + + for (i =3D 0; map_in[i].dt_id >=3D 0; i++) { } + + map =3D devm_kcalloc(dev, i + 1, sizeof(*map), GFP_KERNEL); + if (!map) + return ERR_PTR(-ENOMEM); + + for (i =3D 0; ; i++) { + map[i].dt_id =3D map_in[i].dt_id; + if (map[i].dt_id < 0) + break; + + map[i].fw_id =3D map_in[i].fw_id; + if (map[i].fw_id >=3D FIXED_CLK_OFFSET) { + enum fixed_clk idx =3D map[i].fw_id - FIXED_CLK_OFFSET; + + map[i].hw =3D priv->fixed_hws[idx]; + continue; + } + + scmi_spec.np =3D priv->scmi_clk_np; + scmi_spec.args_count =3D 1; + scmi_spec.args[0] =3D map[i].fw_id; + + clk =3D of_clk_get_from_provider(&scmi_spec); + if (IS_ERR(clk)) + return dev_err_cast_probe(dev, clk, + "Failed to get SCMI clock %u\n", + map[i].fw_id); + + hw =3D __clk_get_hw(clk); + if (IS_ERR(hw)) + return dev_err_cast_probe(dev, hw, + "Failed to get SCMI clock hw %u\n", + map[i].fw_id); + + if (!hw) { + /* CLOCK_ATTRIBUTES is not supported */ + dev_warn(dev, "SCMI clock %u is NULL\n", map[i].fw_id); + continue; + } + + dev_dbg(priv->dev, "SCMI clock %u is %s at %lu Hz\n", + map[i].fw_id, clk_hw_get_name(hw), clk_hw_get_rate(hw)); + + map[i].hw =3D hw; + } + + return map; +} + +static int r8a78000_cpg_probe(struct platform_device *pdev) +{ + struct device_node *scmi __free(device_node) =3D NULL; + struct device *dev =3D &pdev->dev; + struct scmi_base_info version; + const struct fw_map *fw_map; + struct r8a78000_cpg_priv *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + + scmi =3D of_parse_phandle(dev->of_node, "firmware", 0); + if (!scmi) { + dev_err(dev, "Cannot find SCMI firmware node\n"); + return -ENODEV; + } + + priv->scmi_clk_np =3D scmi_find_proto(scmi, SCMI_PROTOCOL_CLOCK); + if (!priv->scmi_clk_np) { + dev_err(dev, "Cannot find SCMI clock management protocol\n"); + return -ENODEV; + } + + ret =3D scmi_get_base_info(scmi, &version); + if (ret) { + return dev_err_probe(dev, -EPROBE_DEFER, + "SCMI not yet available\n"); + } + + if (strcmp(version.vendor_id, "Renesas") || + strcmp(version.sub_vendor_id, "None")) { + return dev_err_probe(dev, -ENODEV, + "Unsupported SCMI firmware %s/%s\n", + version.vendor_id, version.sub_vendor_id); + } + + for (fw_map =3D of_device_get_match_data(dev); fw_map->map; fw_map++) { + if (fw_map->impl_ver =3D=3D version.impl_ver) + break; + } + + if (!fw_map->map) { + return dev_err_probe(dev, -ENODEV, + "Unsupported SCMI version 0x%08x\n", + version.impl_ver); + } + + ret =3D register_fixed_clks(priv); + if (ret) + return ret; + + /* + * We cannot do lazy look-up in r8a78000_clk_get(), as that function is + * called with of_clk_mutex already held. + */ + priv->map =3D fill_clk_map(priv, fw_map->map); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + return devm_of_clk_add_hw_provider(dev, r8a78000_clk_get, priv); +} + +static const struct clk_map_in r8a78000_cpg_fw_4_28_0[] =3D { + { R8A78000_CPG_SGASYNCD4_PERW_BUS, FIXED_CLK(266M) }, + { R8A78000_CPG_SGASYNCD16_PERW_BUS, FIXED_CLK(66M) }, + { R8A78000_CPG_MSOCK_PERW_BUS, 1671 }, + { -1 } +}; + +static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] =3D { + { R8A78000_CPG_SGASYNCD4_PERW_BUS, FIXED_CLK(266M) }, + { R8A78000_CPG_SGASYNCD16_PERW_BUS, FIXED_CLK(66M) }, + { R8A78000_CPG_MSOCK_PERW_BUS, 1667 }, + { -1 } +}; + +static const struct fw_map r8a78000_cpg_fw_map[] =3D { + { 0x010a0000, r8a78000_cpg_fw_4_28_0 }, /* SCP FW SDKv4.28.0 */ + { 0x010d0000, r8a78000_cpg_fw_4_31_0 }, /* SCP FW SDKv4.31.0 */ + { 0x010e0000, r8a78000_cpg_fw_4_31_0 }, /* SCP FW SDKv4.32.0 */ + { 0, NULL } +}; + +static const struct of_device_id r8a78000_cpg_match[] =3D { + { + .compatible =3D "renesas,r8a78000-cpg", + .data =3D &r8a78000_cpg_fw_map, + }, + { /* sentinel */ } +}; + +static struct platform_driver r8a78000_cpg_driver =3D { + .probe =3D r8a78000_cpg_probe, + .driver =3D { + .name =3D "r8a78000-cpg", + .of_match_table =3D r8a78000_cpg_match, + .suppress_bind_attrs =3D true, + }, +}; + +builtin_platform_driver(r8a78000_cpg_driver) + +MODULE_DESCRIPTION("R-Car X5H CPG Driver"); --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D7273A9DA9; Tue, 21 Apr 2026 18:12:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795179; cv=none; b=gkeT2NE75Fgs8lv66+7I1/Ptgk+FqqZiUF6kFGv+BVqDxZoThaFU1Tkug16VY4GMDDFOLPOVo6jcSueFXUy6WESOBbHRrbjS9r4Q3mOCmjapK9JbAqOq1MuzmxF/dkJhLkeIqaBsqgf49+8nyObEVuIjrslrvbxxN8x4A7A3UFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795179; c=relaxed/simple; bh=bX1BXPGHQKtfelHjEMxYF0I0s7biqFSAGcFA0hENItM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UjAGELq/13tOzbrSUSc4tASyQQATSuX0SB4V5pMmm6xWazgCimNdY2YQ0aR8v1Gq3d5YW0tesErTmdsXxarylMzpDbq/pVGWavVyoWQRET4ENkVIbX1XaDasP2+TtJoR0ErLtbIx0WOUtz7iZABIWeFFZhB8Da12A3TZ6c3qn0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id E1B36C2BCB4; Tue, 21 Apr 2026 18:12:53 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 12/14] pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping driver Date: Tue, 21 Apr 2026 20:11:45 +0200 Message-ID: <8715d56610f5fa04be0f4463d3e88af2c3cd216e.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a proof-of-concept Module Controller driver for the R-Car X5H (R8A78000) SoC, using tables to remap from hardware power domain, module, and reset IDs to SCMI power domains, clocks, and resets. Note that SCMI clocks representing hardware modules are fake clocks, with a zero clock rate, that can just be enabled and disabled. Hence these are controlled from the clock domain's start/stop callbacks. For now this contains preliminary support for SCP FW SDKv4.28.0, v4.31.0, and v4.32.0: - As the SCMI power domain IDs are idential for all three versions, r8a78000_mdlc_*_power_fw_4_28_0[] apply to all of them, - As the SCMI clock and reset IDs are identical for the last two versions (except for the addition of two reset IDs in v4.32.0), r8a78000_mdlc_fw_4_31_0[] applies to both of them. Note that v4.32 has two new reset IDs without corresponding clock IDs, so "/* SCMI clock and reset IDs are identical */" is no longer 100% true. However, these new resets seem to be meant for board control, not SoC control. Suggested-by: Marek Vasut Signed-off-by: Geert Uytterhoeven --- drivers/pmdomain/renesas/Kconfig | 4 + drivers/pmdomain/renesas/Makefile | 1 + drivers/pmdomain/renesas/r8a78000-mdlc.c | 1021 ++++++++++++++++++++++ drivers/soc/renesas/Kconfig | 1 + 4 files changed, 1027 insertions(+) create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kc= onfig index b507c3e0d723efc6..f2f52d3c29a083f1 100644 --- a/drivers/pmdomain/renesas/Kconfig +++ b/drivers/pmdomain/renesas/Kconfig @@ -13,6 +13,10 @@ config SYSC_RMOBILE bool "System Controller support for R-Mobile" if COMPILE_TEST =20 # SoC +config MDLC_R8A78000 + bool "Module Controller support for R8A78000 (R-Car X5H)" if COMPILE_TEST + select RESET_CONTROLLER + config SYSC_R8A7742 bool "System Controller support for R8A7742 (RZ/G1H)" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/M= akefile index 0391e6e67440a786..17849aad37a5ac4f 100644 --- a/drivers/pmdomain/renesas/Makefile +++ b/drivers/pmdomain/renesas/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # SoC +obj-$(CONFIG_MDLC_R8A78000) +=3D r8a78000-mdlc.o obj-$(CONFIG_SYSC_R8A7742) +=3D r8a7742-sysc.o obj-$(CONFIG_SYSC_R8A7743) +=3D r8a7743-sysc.o obj-$(CONFIG_SYSC_R8A7745) +=3D r8a7745-sysc.o diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/re= nesas/r8a78000-mdlc.c new file mode 100644 index 0000000000000000..74d2509657e97dbf --- /dev/null +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c @@ -0,0 +1,1021 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car X5H Module Controller + * + * Copyright (C) 2026 Glider bv + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct power_map_in { + int hw_id; /* Hardware power domain ID */ + u32 fw_id; /* SCMI firmware power domain ID */ +}; + +struct power_map { + int hw_id; /* Hardware power domain ID */ + u32 fw_id; /* SCMI firmware power domain ID */ + struct generic_pm_domain *genpd; +}; + +struct mod_map { + int hw_id; /* Hardware module ID */ + u32 fw_id; /* SCMI clock and reset IDs are identical */ +}; + +struct r8a78000_mdlc_info { + u32 base; + const struct power_map_in *power_map; + const struct mod_map *mod_map; +}; + +struct fw_map { + u32 impl_ver; + const struct r8a78000_mdlc_info *info; +}; + +/** + * struct r8a78000_mdlc_priv - Module Controller Private Data + * + * @link: Link into list of MDLC instances + * @genpd_data: PM domain provider data + * @rcdev: Reset controller entity + * @dev: MDLC device + * @np: Device node in DT representing the MDLC + * @scmi_power_np: Device node in DT for the SCMI firmware power protocol + * @scmi_clk_np: Device node in DT for the SCMI firmware clock protocol + * @scmi_reset_np: Device node in DT for the SCMI firmware reset protocol + * @scmi_rcdev: SCMI reset controller entity + * @power_map: Mapping from hardware power domain IDs to SCMI power domains + * @mod_map: Mapping from hardware module IDs to SCMI clocks and resets + */ +struct r8a78000_mdlc_priv { + struct hlist_node link; + struct genpd_onecell_data genpd_data; + struct reset_controller_dev rcdev; + struct device *dev; + struct device_node *np; + struct device_node *scmi_power_np; + struct device_node *scmi_clk_np; + struct device_node *scmi_reset_np; + struct reset_controller_dev *scmi_rcdev; + const struct power_map *power_map; + const struct mod_map *mod_map; +}; + +static struct generic_pm_domain *r8a78000_genpd_always_on; +static HLIST_HEAD(r8a78000_mdlc_list); +static DEFINE_MUTEX(r8a78000_mdlc_lock); /* protects the two above */ + +static const struct power_map *power_map_find(const struct power_map *map, + u32 id) +{ + if (!map) + return NULL; + + for (; map->hw_id >=3D 0; map++) { + if (map->hw_id =3D=3D id) + return map; + } + + return NULL; +} + +static struct generic_pm_domain *r8a78000_genpd_xlate( + const struct of_phandle_args *spec, void *data) +{ + struct r8a78000_mdlc_priv *priv =3D container_of(data, + struct r8a78000_mdlc_priv, genpd_data); + struct generic_pm_domain *genpd; + struct device *dev =3D priv->dev; + const struct power_map *map; + u32 id; + + if (spec->args_count !=3D 2) + return ERR_PTR(-EINVAL); + + id =3D spec->args[0]; + + if (id >=3D R8A78000_MDLC_PD_AON) { + dev_dbg(dev, "Mapping HW power domain %u to always-on domain\n", + id); + return r8a78000_genpd_always_on; + } + + map =3D power_map_find(priv->power_map, id); + if (!map) { + dev_err(dev, "Unknown power domain %u\n", id); + return ERR_PTR(-ENOENT); + } + + dev_dbg(dev, "Mapping HW power domain %u to SCMI power domain %u\n", id, + map->fw_id); + + genpd =3D map->genpd; + + return genpd; +} + +#define rcdev_to_priv(_rcdev) \ + container_of(_rcdev, struct r8a78000_mdlc_priv, rcdev) + +static const struct mod_map *mod_map_find(const struct mod_map *map, u32 i= d) +{ + if (!map) + return NULL; + + for (; map->hw_id >=3D 0; map++) { + if (map->hw_id =3D=3D id) + return map; + } + + return NULL; +} + +static int r8a78000_mdlc_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *spec) +{ + struct r8a78000_mdlc_priv *priv =3D rcdev_to_priv(rcdev); + struct device *dev =3D priv->dev; + const struct mod_map *map; + u32 id; + + if (spec->args_count !=3D 1) + return -EINVAL; + + id =3D spec->args[0]; + + map =3D mod_map_find(priv->mod_map, id); + if (!map) { + dev_err(dev, "Unknown reset %u\n", id); + return -ENOENT; + } + + dev_dbg(dev, "Mapping HW reset %u to SCMI reset %u\n", id, map->fw_id); + + return map->fw_id; +} + +#define DEFINE_MDLC_RESET_WRAPPER(op) \ + static int r8a78000_mdlc_ ## op(struct reset_controller_dev *rcdev, \ + unsigned long id) \ + { \ + struct r8a78000_mdlc_priv *priv =3D rcdev_to_priv(rcdev); \ + int ret; \ + \ + if (!priv->scmi_rcdev->ops->op) \ + return -ENOTSUPP; \ + \ + ret =3D priv->scmi_rcdev->ops->op(priv->scmi_rcdev, id); \ + if (ret =3D=3D -EOPNOTSUPP) \ + dev_dbg(priv->dev, \ + "%s: Ignoring unsupported reset %lu\n", \ + __func__, id); \ + return ret =3D=3D -EOPNOTSUPP ? 0 : ret; \ + } + +DEFINE_MDLC_RESET_WRAPPER(reset) +DEFINE_MDLC_RESET_WRAPPER(assert) +DEFINE_MDLC_RESET_WRAPPER(deassert) +DEFINE_MDLC_RESET_WRAPPER(status) + +static const struct reset_control_ops r8a78000_mdlc_reset_ops =3D { + .reset =3D r8a78000_mdlc_reset, + .assert =3D r8a78000_mdlc_assert, + .deassert =3D r8a78000_mdlc_deassert, + .status =3D r8a78000_mdlc_status, +}; + +static struct device_node *scmi_find_proto(struct device_node *scmi, u32 p= roto) +{ + for_each_available_child_of_node_scoped(scmi, child) { + u32 reg; + + if (of_property_read_u32(child, "reg", ®)) + continue; + + if (reg =3D=3D proto) + return_ptr(child); + } + + return NULL; +} + +static int r8a78000_mdlc_attach_dev(struct generic_pm_domain *domain, + struct device *dev) +{ + struct of_phandle_args pd_spec, scmi_spec; + struct device_node *np =3D dev->of_node; + struct r8a78000_mdlc_priv *priv; + const struct mod_map *map; + unsigned int id; + struct clk *clk; + int ret; + + ret =3D of_parse_phandle_with_args(np, "power-domains", + "#power-domain-cells", 0, &pd_spec); + if (ret < 0) + return ret; + + if (pd_spec.args_count !=3D 2) { + of_node_put(pd_spec.np); + return -EINVAL; + } + + scoped_guard(mutex, &r8a78000_mdlc_lock) { + hlist_for_each_entry(priv, &r8a78000_mdlc_list, link) { + if (priv->np =3D=3D pd_spec.np) + break; + } + } + + if (!priv) { + dev_err(dev, "%s: MDLC %pOF not found\n", __func__, pd_spec.np); + of_node_put(pd_spec.np); + return -ENODEV; + } + + id =3D pd_spec.args[1]; + of_node_put(pd_spec.np); + + map =3D mod_map_find(priv->mod_map, id); + if (!map) { + dev_err(dev, "Unknown module %u\n", id); + return -ENOENT; + } + + dev_dbg(dev, "Mapping HW module %u to SCMI clock %u\n", id, map->fw_id); + + scmi_spec.np =3D priv->scmi_clk_np; + scmi_spec.args_count =3D 1; + scmi_spec.args[0] =3D map->fw_id; + + clk =3D of_clk_get_from_provider(&scmi_spec); + if (IS_ERR(clk)) { + dev_err(dev, "Cannot get SCMI clock %u: %pe\n", map->fw_id, + clk); + return PTR_ERR(clk); + } + + dev_dbg(dev, "SCMI clock %u is %pC\n", map->fw_id, clk); + + if (!clk) { + /* Ignore missing SCMI module clocks */ + return 0; + } + + ret =3D pm_clk_create(dev); + if (ret) + goto fail_put; + + ret =3D pm_clk_add_clk(dev, clk); + if (ret) + goto fail_destroy; + + return 0; + +fail_destroy: + pm_clk_destroy(dev); +fail_put: + clk_put(clk); + return ret; +} + +static void r8a78000_mdlc_detach_dev(struct generic_pm_domain *domain, + struct device *dev) +{ + if (!pm_clk_no_clocks(dev)) + pm_clk_destroy(dev); +} + +static const struct power_map *fill_power_map(struct r8a78000_mdlc_priv *p= riv, + const struct power_map_in *map_in) +{ + struct of_phandle_args scmi_spec; + struct generic_pm_domain *genpd; + struct device *dev =3D priv->dev; + struct power_map *map; + unsigned int i; + + if (!map_in) + return NULL; + + for (i =3D 0; map_in[i].hw_id >=3D 0; i++) { } + + map =3D devm_kcalloc(dev, i + 1, sizeof(*map), GFP_KERNEL); + if (!map) + return ERR_PTR(-ENOMEM); + + for (i =3D 0; ; i++) { + map[i].hw_id =3D map_in[i].hw_id; + if (map[i].hw_id < 0) + break; + + map[i].fw_id =3D map_in[i].fw_id; + + scmi_spec.np =3D priv->scmi_power_np; + scmi_spec.args_count =3D 1; + scmi_spec.args[0] =3D map[i].fw_id; + + genpd =3D genpd_get_from_provider(&scmi_spec); + if (IS_ERR(genpd)) + return dev_err_cast_probe(dev, genpd, + "Failed to get SCMI power domain %u\n", + map[i].fw_id); + + dev_dbg(dev, "SCMI power domain %u is %s\n", map[i].fw_id, + genpd->name); + + map[i].genpd =3D genpd; + + /* Hook up clock domain support */ + genpd->attach_dev =3D r8a78000_mdlc_attach_dev; + genpd->detach_dev =3D r8a78000_mdlc_detach_dev; + /* Setting flags this late has no impact, but does not hurt */ + genpd->flags |=3D GENPD_FLAG_PM_CLK; + genpd->dev_ops.stop =3D pm_clk_suspend; + genpd->dev_ops.start =3D pm_clk_resume; + } + + return map; +} + +static void r8a78000_mdlc_unlink(void *data) +{ + struct r8a78000_mdlc_priv *priv =3D data; + + scoped_guard(mutex, &r8a78000_mdlc_lock) { + hlist_del(&priv->link); + } +} + +static void r8a78000_genpd_del_provider(void *data) +{ + of_genpd_del_provider(data); +} + +static int r8a78000_genpd_always_on_singleton(struct device *dev) +{ + struct generic_pm_domain *genpd; + int ret; + + guard(mutex)(&r8a78000_mdlc_lock); + + if (r8a78000_genpd_always_on) + return 0; + + genpd =3D kzalloc_obj(*genpd); + if (!genpd) + return -ENOMEM; + + genpd->name =3D "always-on"; + genpd->attach_dev =3D r8a78000_mdlc_attach_dev; + genpd->detach_dev =3D r8a78000_mdlc_detach_dev; + genpd->flags |=3D GENPD_FLAG_PM_CLK; + + ret =3D pm_genpd_init(genpd, &pm_domain_always_on_gov, false); + if (ret) { + kfree(genpd); + return dev_err_probe(dev, ret, + "Failed to create always-on domain\n"); + } + + r8a78000_genpd_always_on =3D genpd; + return 0; +} + +static int r8a78000_mdlc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct device_node *scmi __free(device_node) =3D NULL; + const struct r8a78000_mdlc_info *info; + struct r8a78000_mdlc_priv *priv; + struct scmi_base_info version; + const struct fw_map *fw_map; + struct resource *res; + int ret; + + ret =3D r8a78000_genpd_always_on_singleton(dev); + if (ret) + return ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->np =3D np; + + scmi =3D of_parse_phandle(dev->of_node, "firmware", 0); + if (!scmi) { + dev_err(dev, "Cannot find SCMI firmware node\n"); + return -ENODEV; + } + + priv->scmi_power_np =3D scmi_find_proto(scmi, SCMI_PROTOCOL_POWER); + if (!priv->scmi_power_np) { + dev_err(dev, + "Cannot find SCMI power domain management protocol\n"); + return -ENODEV; + } + + priv->scmi_clk_np =3D scmi_find_proto(scmi, SCMI_PROTOCOL_CLOCK); + if (!priv->scmi_clk_np) { + dev_err(dev, "Cannot find SCMI clock management protocol\n"); + return -ENODEV; + } + + priv->scmi_reset_np =3D scmi_find_proto(scmi, SCMI_PROTOCOL_RESET); + if (!priv->scmi_reset_np) { + dev_err(dev, "Cannot find SCMI reset management protocol\n"); + return -ENODEV; + } + + ret =3D scmi_get_base_info(scmi, &version); + if (ret) { + return dev_err_probe(dev, -EPROBE_DEFER, + "SCMI not yet available\n"); + } + + if (strcmp(version.vendor_id, "Renesas") || + strcmp(version.sub_vendor_id, "None")) { + return dev_err_probe(dev, -ENODEV, + "Unsupported SCMI firmware %s/%s\n", + version.vendor_id, version.sub_vendor_id); + } + + priv->scmi_rcdev =3D reset_controller_get_provider(of_fwnode_handle(priv-= >scmi_reset_np)); + if (!priv->scmi_rcdev) + return dev_err_probe(dev, -EPROBE_DEFER, + "SCMI reset not yet available\n"); + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + for (fw_map =3D of_device_get_match_data(dev); fw_map->info; fw_map++) { + if (fw_map->impl_ver =3D=3D version.impl_ver) + break; + } + + if (!fw_map->info) { + return dev_err_probe(dev, -ENODEV, + "Unsupported SCMI version 0x%08x\n", + version.impl_ver); + } + + for (info =3D fw_map->info; info->base; info++) { + if (info->base =3D=3D res->start) + break; + } + + if (!info->base) { + dev_warn(dev, "Unsupported MDLC instance 0x%pa\n", &res->start); + return -ENODEV; + } + + /* + * We cannot do lazy look-up in r8a78000_genpd_xlate(), as that + * function is called with of_genpd_mutex already held. + */ + priv->power_map =3D fill_power_map(priv, info->power_map); + if (IS_ERR(priv->power_map)) + return PTR_ERR(priv->power_map); + + priv->mod_map =3D info->mod_map; + + scoped_guard(mutex, &r8a78000_mdlc_lock) { + hlist_add_head(&priv->link, &r8a78000_mdlc_list); + } + + ret =3D devm_add_action_or_reset(dev, r8a78000_mdlc_unlink, priv); + if (ret) + return dev_err_probe(dev, ret, "failed to add action\n"); + + // FIXME genpd_add_provider() would be sufficient, but is private + /* Note that no actual domains are registered, just need translation */ + priv->genpd_data.xlate =3D r8a78000_genpd_xlate; + ret =3D of_genpd_add_provider_onecell(np, &priv->genpd_data); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register genpd provider\n"); + + ret =3D devm_add_action_or_reset(dev, r8a78000_genpd_del_provider, np); + if (ret) + return dev_err_probe(dev, ret, + "failed to add unregister action\n"); + + priv->rcdev.ops =3D &r8a78000_mdlc_reset_ops; + priv->rcdev.of_node =3D np; + priv->rcdev.of_reset_n_cells =3D 1; + priv->rcdev.of_xlate =3D r8a78000_mdlc_reset_xlate; + + ret =3D devm_reset_controller_register(dev, &priv->rcdev); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register reset controller\n"); + + return 0; +} + +// FIXME We don't need all of them from the start; only add when used/test= ed +static const struct power_map_in r8a78000_mdlc_pere_power_fw_4_28_0[] =3D { + { 0, 12 }, /* PD_UFS0 */ + { 1, 13 }, /* PD_UFS1 */ + { -1 }, +}; + +static const struct mod_map r8a78000_mdlc_pere_mod_fw_4_28_0[] =3D { + { 0x30, 197 }, /* PERE_GPIODM0 */ + // No CLOCK_ATTRIBUTES { 0x31, 198 }, /* PERE_GPIODM1 */ + // No CLOCK_ATTRIBUTES { 0x32, 199 }, /* PERE_GPIODM2 */ + // No CLOCK_ATTRIBUTES { 0x33, 200 }, /* PERE_GPIODM3 */ + { 0x40, 201 }, /* RPC */ + { 0x60, 202 }, /* UFS0 */ + { 0x61, 203 }, /* UFS1 */ + { 0x70, 204 }, /* SDHI0 */ + { -1 }, +}; + +static const struct mod_map r8a78000_mdlc_perw_mod_fw_4_28_0[] =3D { + { 0x30, 205 }, /* PERW_GPIODM0 */ + // No CLOCK_ATTRIBUTES { 0x31, 206 }, /* PERW_GPIODM1 */ + // No CLOCK_ATTRIBUTES { 0x32, 207 }, /* PERW_GPIODM2 */ + // No CLOCK_ATTRIBUTES { 0x33, 208 }, /* PERW_GPIODM3 */ + { 0x40, 209 }, /* SCIF0 */ + { 0x41, 210 }, /* SCIF1 */ + { 0x42, 211 }, /* SCIF3 */ + { 0x43, 212 }, /* SCIF4 */ + { 0x44, 213 }, /* I2C1 */ + { 0x45, 214 }, /* I2C2 */ + { 0x46, 215 }, /* I2C3 */ + { 0x47, 216 }, /* I2C4 */ + { 0x48, 217 }, /* I2C5 */ + { 0x49, 218 }, /* I2C6 */ + { 0x4a, 219 }, /* I2C7 */ + { 0x4b, 220 }, /* I2C8 */ + { 0x4c, 221 }, /* I3C0 */ + { 0x4d, 222 }, /* I3C1 */ + { 0x4e, 223 }, /* I3C2 */ + { 0x4f, 224 }, /* MSI4 */ + { 0x50, 225 }, /* MSI5 */ + { 0x51, 226 }, /* MSI6 */ + { 0x52, 227 }, /* MSI7 */ + /* + * HSCIF0 is protected: + * - CLOCK_ATTRIBUTES is not supported, so clk is NULL + * - Reset operations fail with -EOPNOTSUPP + */ + { 0x54, 228 }, /* HSCIF0 */ + { 0x55, 229 }, /* HSCIF1 */ + { 0x56, 230 }, /* HSCIF2 */ + { 0x57, 231 }, /* HSCIF3 */ + { 0x58, 232 }, /* DRI00 */ + { 0x59, 233 }, /* DRI01 */ + { 0x5a, 234 }, /* DRI10 */ + { 0x5b, 235 }, /* DRI11 */ + { 0x5c, 236 }, /* DRI20 */ + { 0x5d, 237 }, /* DRI21 */ + { 0x5e, 238 }, /* DRI30 */ + { 0x5f, 239 }, /* DRI31 */ + { 0x60, 240 }, /* DRI40 */ + { 0x61, 241 }, /* DRI41 */ + { 0x62, 242 }, /* DRI50 */ + { 0x63, 243 }, /* DRI51 */ + { 0x64, 244 }, /* DRI60 */ + { 0x65, 245 }, /* DRI61 */ + { 0x66, 246 }, /* DRI70 */ + { 0x67, 247 }, /* DRI71 */ + { 0x70, 248 }, /* PWM0 */ + { 0x72, 249 }, /* TMU1 */ + { 0x73, 250 }, /* TMU2 */ + { 0x74, 251 }, /* TMU3 */ + { 0x75, 252 }, /* TMU4 */ + { 0x76, 253 }, /* TPU0 */ + { 0x90, 254 }, /* ADG0 */ + { 0x91, 255 }, /* ADG1 */ + { 0x92, 256 }, /* SSI0 */ + { 0x93, 257 }, /* SSI00 */ + { 0x94, 258 }, /* SSI01 */ + { 0x95, 259 }, /* SSI02 */ + { 0x96, 260 }, /* SSI03 */ + { 0x97, 261 }, /* SSI04 */ + { 0x98, 262 }, /* SSI05 */ + { 0x99, 263 }, /* SSI06 */ + { 0x9a, 264 }, /* SSI07 */ + { 0x9b, 265 }, /* SSI08 */ + { 0x9c, 266 }, /* SSI09 */ + { 0x9d, 267 }, /* SSI1 */ + { 0x9e, 268 }, /* SSI10 */ + { 0x9f, 269 }, /* SSI11 */ + { 0xa0, 270 }, /* SSI12 */ + { 0xa1, 271 }, /* SSI13 */ + { 0xa2, 272 }, /* SSI14 */ + { 0xa3, 273 }, /* SSI15 */ + { 0xa4, 274 }, /* SSI16 */ + { 0xa5, 275 }, /* SSI17 */ + { 0xa6, 276 }, /* SSI18 */ + { 0xa7, 277 }, /* SSI19 */ + { 0xa8, 278 }, /* SCU0 */ + { 0xa9, 279 }, /* SRC00 */ + { 0xaa, 280 }, /* SRC01 */ + { 0xab, 281 }, /* SRC02 */ + { 0xac, 282 }, /* SRC03 */ + { 0xad, 283 }, /* SRC04 */ + { 0xae, 284 }, /* SRC05 */ + { 0xaf, 285 }, /* SRC06 */ + { 0xb0, 286 }, /* SRC07 */ + { 0xb1, 287 }, /* SRC08 */ + { 0xb2, 288 }, /* SRC09 */ + { 0xb3, 289 }, /* SCU00 */ + { 0xb4, 290 }, /* SCU01 */ + { 0xb5, 291 }, /* DVC00 */ + { 0xb6, 292 }, /* DVC01 */ + { 0xb7, 293 }, /* SCU1 */ + { 0xb8, 294 }, /* SRC10 */ + { 0xb9, 295 }, /* SRC11 */ + { 0xba, 296 }, /* SRC12 */ + { 0xbb, 297 }, /* SRC13 */ + { 0xbc, 298 }, /* SRC14 */ + { 0xbd, 299 }, /* SRC15 */ + { 0xbe, 300 }, /* SRC16 */ + { 0xbf, 301 }, /* SRC17 */ + { 0xc0, 302 }, /* SRC18 */ + { 0xc1, 303 }, /* SRC19 */ + { 0xc2, 304 }, /* SCU10 */ + { 0xc3, 305 }, /* SCU11 */ + { 0xc4, 306 }, /* DVC10 */ + { 0xc5, 307 }, /* DVC11 */ + { 0xc6, 308 }, /* APD00 */ + { 0xc7, 309 }, /* APD01 */ + { 0xc8, 310 }, /* APD10 */ + { 0xc9, 311 }, /* APD11 */ + { 0xca, 312 }, /* APD02 */ + { 0xcb, 313 }, /* APD12 */ + { -1 }, +}; + +static const struct r8a78000_mdlc_info r8a78000_mdlc_fw_4_28_0[] =3D { + { + .base =3D 0xc3060000 /* mdlc_vipn */, + /* FIXME .power_map =3D r8a78000_mdlc_vipn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_vipn_mod_fw_4_28_0, */ + }, { + .base =3D 0xc3460000 /* mdlc_vips */, + /* FIXME .power_map =3D r8a78000_mdlc_vips_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_vips_mod_fw_4_28_0, */ + }, { + .base =3D 0xc5000000 /* mdlc_vio */, + /* FIXME .power_map =3D r8a78000_mdlc_vio_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_vio_mod_fw_4_28_0, */ + }, { + .base =3D 0xc08f0000 /* mdlc_pere */, + .power_map =3D r8a78000_mdlc_pere_power_fw_4_28_0, + .mod_map =3D r8a78000_mdlc_pere_mod_fw_4_28_0, + }, { + .base =3D 0xc05d0000 /* mdlc_perw */, + .mod_map =3D r8a78000_mdlc_perw_mod_fw_4_28_0, +// FIXME We don't need all of them from the start; only add when used/test= ed +#if 0 + }, { + .base =3D 0xe8000000 /* mdlc_ddr0 */, + }, { + .base =3D 0xe8080000 /* mdlc_ddr1 */, + }, { + .base =3D 0xe8100000 /* mdlc_ddr2 */, + }, { + .base =3D 0xe8180000 /* mdlc_ddr3 */, + }, { + .base =3D 0xe8200000 /* mdlc_ddr4 */, + }, { + .base =3D 0xe8280000 /* mdlc_ddr5 */, + }, { + .base =3D 0xe8300000 /* mdlc_ddr6 */, + }, { + .base =3D 0xe8380000 /* mdlc_ddr7 */, + }, { + .base =3D 0xc9c90000 /* mdlc_hscn */, + /* FIXME .power_map =3D r8a78000_mdlc_hscn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_hscn_mod_fw_4_28_0, */ + }, { + .base =3D 0x19440000 /* mdlc_rt */, + /* FIXME .power_map =3D r8a78000_mdlc_rt_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_rt_mod_fw_4_28_0, */ + }, { + .base =3D 0xc6480000 /* mdlc_top */, + /* FIXME .mod_map =3D r8a78000_mdlc_top_mod_fw_4_28_0, */ + }, { + .base =3D 0xde200000 /* mdlc_hscs */, + /* FIXME .power_map =3D r8a78000_mdlc_hscs_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_hscs_mod_fw_4_28_0, */ + }, { + .base =3D 0xc1990000 /* mdlc_imn */, + /* FIXME .power_map =3D r8a78000_mdlc_imn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_imn_mod_fw_4_28_0, */ + }, { + .base =3D 0xc1d90000 /* mdlc_ims */, + /* FIXME .power_map =3D r8a78000_mdlc_ims_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_ims_mod_fw_4_28_0, */ + }, { + .base =3D 0xcb510000 /* mdlc_gpc */, + /* FIXME .power_map =3D r8a78000_mdlc_gpc_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_gpc_mod_fw_4_28_0, */ + }, { + .base =3D 0xcbe90000 /* mdlc_dsp */, + /* FIXME .power_map =3D r8a78000_mdlc_dsp_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_dsp_mod_fw_4_28_0, */ + }, { + .base =3D 0xe9980000 /* mdlc_mm */, + /* FIXME .mod_map =3D r8a78000_mdlc_mm_mod_fw_4_28_0, */ + }, { + .base =3D 0xd2c30000 /* mdlc_npu0 */, + /* FIXME .power_map =3D r8a78000_mdlc_npu0_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_npu0_mod_fw_4_28_0, */ + }, { + .base =3D 0xd6c30000 /* mdlc_npu1 */, + /* FIXME .power_map =3D r8a78000_mdlc_npu1_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_npu1_mod_fw_4_28_0, */ + }, { + .base =3D 0xca410000 /* mdlc_cmnn */, + /* FIXME .power_map =3D r8a78000_mdlc_cmnn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_cmnn_mod_fw_4_28_0, */ + }, { + .base =3D 0xca510000 /* mdlc_cmns */, + /* FIXME .power_map =3D r8a78000_mdlc_cmns_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_cmns_mod_fw_4_28_0, */ + }, { + .base =3D 0xc1330000 /* mdlc_scp */, + /* FIXME .mod_map =3D r8a78000_mdlc_scp_mod_fw_4_28_0, */ + }, { + .base =3D 0xc1338000 /* mdlc_aon */, + /* FIXME .mod_map =3D r8a78000_mdlc_aon_mod_fw_4_28_0, */ +#endif + }, + { 0 } +}; + +static const struct mod_map r8a78000_mdlc_pere_mod_fw_4_31_0[] =3D { + { 0x30, 193 }, /* PERE_GPIODM0 */ + // No CLOCK_ATTRIBUTES { 0x31, 194 }, /* PERE_GPIODM1 */ + // No CLOCK_ATTRIBUTES { 0x32, 195 }, /* PERE_GPIODM2 */ + // No CLOCK_ATTRIBUTES { 0x33, 196 }, /* PERE_GPIODM3 */ + { 0x40, 197 }, /* RPC */ + { 0x60, 198 }, /* UFS0 */ + { 0x61, 199 }, /* UFS1 */ + { 0x70, 200 }, /* SDHI0 */ + { -1 }, +}; + +static const struct mod_map r8a78000_mdlc_perw_mod_fw_4_31_0[] =3D { + { 0x30, 201 }, /* PERW_GPIODM0 */ + // No CLOCK_ATTRIBUTES { 0x31, 202 }, /* PERW_GPIODM1 */ + // No CLOCK_ATTRIBUTES { 0x32, 203 }, /* PERW_GPIODM2 */ + // No CLOCK_ATTRIBUTES { 0x33, 204 }, /* PERW_GPIODM3 */ + { 0x40, 205 }, /* SCIF0 */ + { 0x41, 206 }, /* SCIF1 */ + { 0x42, 207 }, /* SCIF3 */ + { 0x43, 208 }, /* SCIF4 */ + { 0x44, 209 }, /* I2C1 */ + { 0x45, 210 }, /* I2C2 */ + { 0x46, 211 }, /* I2C3 */ + { 0x47, 212 }, /* I2C4 */ + { 0x48, 213 }, /* I2C5 */ + { 0x49, 214 }, /* I2C6 */ + { 0x4a, 215 }, /* I2C7 */ + { 0x4b, 216 }, /* I2C8 */ + { 0x4c, 217 }, /* I3C0 */ + { 0x4d, 218 }, /* I3C1 */ + { 0x4e, 219 }, /* I3C2 */ + { 0x4f, 220 }, /* MSI4 */ + { 0x50, 221 }, /* MSI5 */ + { 0x51, 222 }, /* MSI6 */ + { 0x52, 223 }, /* MSI7 */ + { 0x54, 224 }, /* HSCIF0 */ + { 0x55, 225 }, /* HSCIF1 */ + { 0x56, 226 }, /* HSCIF2 */ + { 0x57, 227 }, /* HSCIF3 */ + { 0x58, 228 }, /* DRI00 */ + { 0x59, 229 }, /* DRI01 */ + { 0x5a, 230 }, /* DRI10 */ + { 0x5b, 231 }, /* DRI11 */ + { 0x5c, 232 }, /* DRI20 */ + { 0x5d, 233 }, /* DRI21 */ + { 0x5e, 234 }, /* DRI30 */ + { 0x5f, 235 }, /* DRI31 */ + { 0x60, 236 }, /* DRI40 */ + { 0x61, 237 }, /* DRI41 */ + { 0x62, 238 }, /* DRI50 */ + { 0x63, 239 }, /* DRI51 */ + { 0x64, 240 }, /* DRI60 */ + { 0x65, 241 }, /* DRI61 */ + { 0x66, 242 }, /* DRI70 */ + { 0x67, 243 }, /* DRI71 */ + { 0x70, 244 }, /* PWM0 */ + { 0x72, 245 }, /* TMU1 */ + { 0x73, 246 }, /* TMU2 */ + { 0x74, 247 }, /* TMU3 */ + { 0x75, 248 }, /* TMU4 */ + { 0x76, 249 }, /* TPU0 */ + { 0x90, 250 }, /* ADG0 */ + { 0x91, 251 }, /* ADG1 */ + { 0x92, 252 }, /* SSI0 */ + { 0x93, 253 }, /* SSI00 */ + { 0x94, 254 }, /* SSI01 */ + { 0x95, 255 }, /* SSI02 */ + { 0x96, 256 }, /* SSI03 */ + { 0x97, 257 }, /* SSI04 */ + { 0x98, 258 }, /* SSI05 */ + { 0x99, 259 }, /* SSI06 */ + { 0x9a, 260 }, /* SSI07 */ + { 0x9b, 261 }, /* SSI08 */ + { 0x9c, 262 }, /* SSI09 */ + { 0x9d, 263 }, /* SSI1 */ + { 0x9e, 264 }, /* SSI10 */ + { 0x9f, 265 }, /* SSI11 */ + { 0xa0, 266 }, /* SSI12 */ + { 0xa1, 267 }, /* SSI13 */ + { 0xa2, 268 }, /* SSI14 */ + { 0xa3, 269 }, /* SSI15 */ + { 0xa4, 270 }, /* SSI16 */ + { 0xa5, 271 }, /* SSI17 */ + { 0xa6, 272 }, /* SSI18 */ + { 0xa7, 273 }, /* SSI19 */ + { 0xa8, 274 }, /* SCU0 */ + { 0xa9, 275 }, /* SRC00 */ + { 0xaa, 276 }, /* SRC01 */ + { 0xab, 277 }, /* SRC02 */ + { 0xac, 278 }, /* SRC03 */ + { 0xad, 279 }, /* SRC04 */ + { 0xae, 280 }, /* SRC05 */ + { 0xaf, 281 }, /* SRC06 */ + { 0xb0, 282 }, /* SRC07 */ + { 0xb1, 283 }, /* SRC08 */ + { 0xb2, 284 }, /* SRC09 */ + { 0xb3, 285 }, /* SCU00 */ + { 0xb4, 286 }, /* SCU01 */ + { 0xb5, 287 }, /* DVC00 */ + { 0xb6, 288 }, /* DVC01 */ + { 0xb7, 289 }, /* SCU1 */ + { 0xb8, 290 }, /* SRC10 */ + { 0xb9, 291 }, /* SRC11 */ + { 0xba, 292 }, /* SRC12 */ + { 0xbb, 293 }, /* SRC13 */ + { 0xbc, 294 }, /* SRC14 */ + { 0xbd, 295 }, /* SRC15 */ + { 0xbe, 296 }, /* SRC16 */ + { 0xbf, 297 }, /* SRC17 */ + { 0xc0, 298 }, /* SRC18 */ + { 0xc1, 299 }, /* SRC19 */ + { 0xc2, 300 }, /* SCU10 */ + { 0xc3, 301 }, /* SCU11 */ + { 0xc4, 302 }, /* DVC10 */ + { 0xc5, 303 }, /* DVC11 */ + { 0xc6, 304 }, /* APD00 */ + { 0xc7, 305 }, /* APD01 */ + { 0xc8, 306 }, /* APD10 */ + { 0xc9, 307 }, /* APD11 */ + { 0xca, 308 }, /* APD02 */ + { 0xcb, 309 }, /* APD12 */ + { -1 }, +}; + +static const struct r8a78000_mdlc_info r8a78000_mdlc_fw_4_31_0[] =3D { + { + .base =3D 0xc3060000 /* mdlc_vipn */, + /* FIXME .power_map =3D r8a78000_mdlc_vipn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_vipn_mod_fw_4_31_0, */ + }, { + .base =3D 0xc3460000 /* mdlc_vips */, + /* FIXME .power_map =3D r8a78000_mdlc_vips_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_vips_mod_fw_4_31_0, */ + }, { + .base =3D 0xc5000000 /* mdlc_vio */, + /* FIXME .power_map =3D r8a78000_mdlc_vio_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_vio_mod_fw_4_31_0, */ + }, { + .base =3D 0xc08f0000 /* mdlc_pere */, + .power_map =3D r8a78000_mdlc_pere_power_fw_4_28_0, + .mod_map =3D r8a78000_mdlc_pere_mod_fw_4_31_0, + }, { + .base =3D 0xc05d0000 /* mdlc_perw */, + .mod_map =3D r8a78000_mdlc_perw_mod_fw_4_31_0, +// FIXME We don't need all of them from the start; only add when used/test= ed +#if 0 + }, { + .base =3D 0xe8000000 /* mdlc_ddr0 */, + }, { + .base =3D 0xe8080000 /* mdlc_ddr1 */, + }, { + .base =3D 0xe8100000 /* mdlc_ddr2 */, + }, { + .base =3D 0xe8180000 /* mdlc_ddr3 */, + }, { + .base =3D 0xe8200000 /* mdlc_ddr4 */, + }, { + .base =3D 0xe8280000 /* mdlc_ddr5 */, + }, { + .base =3D 0xe8300000 /* mdlc_ddr6 */, + }, { + .base =3D 0xe8380000 /* mdlc_ddr7 */, + }, { + .base =3D 0xc9c90000 /* mdlc_hscn */, + /* FIXME .power_map =3D r8a78000_mdlc_hscn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_hscn_mod_fw_4_31_0, */ + }, { + .base =3D 0x19440000 /* mdlc_rt */, + /* FIXME .power_map =3D r8a78000_mdlc_rt_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_rt_mod_fw_4_31_0, */ + }, { + .base =3D 0xc6480000 /* mdlc_top */, + /* FIXME .mod_map =3D r8a78000_mdlc_top_mod_fw_4_31_0, */ + }, { + .base =3D 0xde200000 /* mdlc_hscs */, + /* FIXME .power_map =3D r8a78000_mdlc_hscs_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_hscs_mod_fw_4_31_0, */ + }, { + .base =3D 0xc1990000 /* mdlc_imn */, + /* FIXME .power_map =3D r8a78000_mdlc_imn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_imn_mod_fw_4_31_0, */ + }, { + .base =3D 0xc1d90000 /* mdlc_ims */, + /* FIXME .power_map =3D r8a78000_mdlc_ims_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_ims_mod_fw_4_31_0, */ + }, { + .base =3D 0xcb510000 /* mdlc_gpc */, + /* FIXME .power_map =3D r8a78000_mdlc_gpc_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_gpc_mod_fw_4_31_0, */ + }, { + .base =3D 0xcbe90000 /* mdlc_dsp */, + /* FIXME .power_map =3D r8a78000_mdlc_dsp_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_dsp_mod_fw_4_31_0, */ + }, { + .base =3D 0xe9980000 /* mdlc_mm */, + /* FIXME .mod_map =3D r8a78000_mdlc_mm_mod_fw_4_31_0, */ + }, { + .base =3D 0xd2c30000 /* mdlc_npu0 */, + /* FIXME .power_map =3D r8a78000_mdlc_npu0_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_npu0_mod_fw_4_31_0, */ + }, { + .base =3D 0xd6c30000 /* mdlc_npu1 */, + /* FIXME .power_map =3D r8a78000_mdlc_npu1_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_npu1_mod_fw_4_31_0, */ + }, { + .base =3D 0xca410000 /* mdlc_cmnn */, + /* FIXME .power_map =3D r8a78000_mdlc_cmnn_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_cmnn_mod_fw_4_31_0, */ + }, { + .base =3D 0xca510000 /* mdlc_cmns */, + /* FIXME .power_map =3D r8a78000_mdlc_cmns_power_fw_4_28_0, */ + /* FIXME .mod_map =3D r8a78000_mdlc_cmns_mod_fw_4_31_0, */ + }, { + .base =3D 0xc1330000 /* mdlc_scp */, + /* FIXME .mod_map =3D r8a78000_mdlc_scp_mod_fw_4_31_0, */ + }, { + .base =3D 0xc1338000 /* mdlc_aon */, + /* FIXME .mod_map =3D r8a78000_mdlc_aon_mod_fw_4_31_0, */ +#endif + }, + { 0 } +}; + +static const struct fw_map r8a78000_mdlc_fw_map[] =3D { + { 0x010a0000, r8a78000_mdlc_fw_4_28_0 }, /* SCP FW SDKv4.28.0 */ + { 0x010d0000, r8a78000_mdlc_fw_4_31_0 }, /* SCP FW SDKv4.31.0 */ + { 0x010e0000, r8a78000_mdlc_fw_4_31_0 }, /* SCP FW SDKv4.32.0 */ + { 0, NULL } +}; + +static const struct of_device_id r8a78000_mdlc_match[] =3D { + { + .compatible =3D "renesas,r8a78000-mdlc", + .data =3D &r8a78000_mdlc_fw_map, + }, + { /* sentinel */ } +}; + +static struct platform_driver r8a78000_mdlc_driver =3D { + .probe =3D r8a78000_mdlc_probe, + .driver =3D { + .name =3D "r8a78000-mdlc", + .of_match_table =3D r8a78000_mdlc_match, + .suppress_bind_attrs =3D true, + }, +}; + +builtin_platform_driver(r8a78000_mdlc_driver) + +MODULE_DESCRIPTION("R-Car X5H MDLC Driver"); diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 2ab150d04bb1f1ef..d4055250de72f1fe 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -358,6 +358,7 @@ config ARCH_R8A78000 default y if ARCH_RENESAS default ARCH_RENESAS select ARCH_RCAR_GEN5 + select MDLC_R8A78000 help This enables support for the Renesas R-Car X5H SoC. =20 --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B99A7260F; Tue, 21 Apr 2026 18:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795184; cv=none; b=gobZTFViIrPkN/Rr4lnnfJzjZQr6QQGhKCGx/CFrvCOHUyrUs4NpLP7b/N688CjGkiKylLSe9/Sxi1SAws9agwJy4pyad1VcoMV8YfewcYU/MiAPsHopv2zaPpL2wZImD7eYiRG/0CG5SsIvU2qdHW6bWBrnXhRDegbz3tzeLi8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795184; c=relaxed/simple; bh=ohh6rjckmdTtX2BmrPnpL5dknnlXTW3T12A14bkCGNo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y6sNfgqvLSVU9+bIRsc0jFQfyWo2kDO79XUFMEnGvSeO+Gso90wrMeNoLxx5L3PHqdVlwAs1KjVHBjWMKic+LgpR66YbNAmIsI8XCTPHM0e4i0hdDwvnf7d7hDbKcbLyqicSGEzeFaRTr2LCq49eMJ3zNdmXgbz51z7kS76gDmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B44BC2BCB7; Tue, 21 Apr 2026 18:12:59 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 13/14] arm64: dts: renesas: r8a78000: Add CPG/MDLC nodes Date: Tue, 21 Apr 2026 20:11:46 +0200 Message-ID: <586b1266f9a8e5aaccc010d4a3a02276ea44f3c8.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for the Clock Pulse Generator (CPG) and Module Control (MDLC) blocks on the R-Car X5H (R8A78000) SoC. Convert all (H)SCIF serial ports from dummy to CPG clocks, and link them to an MDLC for power domains and resets. Signed-off-by: Geert Uytterhoeven --- Add all MDLC nodes from the start, or only when used/tested? --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 300 ++++++++++++++++++++-- 1 file changed, 275 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dt= s/renesas/r8a78000.dtsi index 11922b1ac73b3af5..640b622435569461 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ =20 +#include +#include #include =20 / { @@ -636,23 +638,6 @@ L3_CA720_7: cache-controller-37 { }; }; =20 - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <266660000>; - }; - extal_clk: extal-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -813,8 +798,12 @@ scif0: serial@c0700000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc0700000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x40>; + resets =3D <&mdlc_perw 0x40>; status =3D "disabled"; }; =20 @@ -823,8 +812,12 @@ scif1: serial@c0704000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc0704000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x41>; + resets =3D <&mdlc_perw 0x41>; status =3D "disabled"; }; =20 @@ -833,8 +826,12 @@ scif3: serial@c0708000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc0708000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x42>; + resets =3D <&mdlc_perw 0x42>; status =3D "disabled"; }; =20 @@ -843,8 +840,12 @@ scif4: serial@c070c000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg =3D <0 0xc070c000 0 0x40>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x43>; + resets =3D <&mdlc_perw 0x43>; status =3D "disabled"; }; =20 @@ -853,8 +854,12 @@ hscif0: serial@c0710000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc0710000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x54>; + resets =3D <&mdlc_perw 0x54>; status =3D "disabled"; }; =20 @@ -863,8 +868,12 @@ hscif1: serial@c0714000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc0714000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x55>; + resets =3D <&mdlc_perw 0x55>; status =3D "disabled"; }; =20 @@ -873,8 +882,12 @@ hscif2: serial@c0718000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc0718000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x56>; + resets =3D <&mdlc_perw 0x56>; status =3D "disabled"; }; =20 @@ -883,8 +896,12 @@ hscif3: serial@c071c000 { "renesas,rcar-gen5-hscif", "renesas,hscif"; reg =3D <0 0xc071c000 0 0x60>; interrupts =3D ; - clocks =3D <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks =3D <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&mdlc_perw R8A78000_MDLC_PD_APL 0x57>; + resets =3D <&mdlc_perw 0x57>; status =3D "disabled"; }; =20 @@ -897,6 +914,239 @@ scp_sram: sram@c1000000 { =20 /* scp-sram node must be set per board file */ }; + + cpg: clock-controller@c1320000 { + compatible =3D "renesas,r8a78000-cpg"; + reg =3D <0 0xc1320000 0 0x10000>; + clocks =3D <&extal_clk>, <&extalr_clk>; + clock-names =3D "extal", "extalr"; + #clock-cells =3D <1>; + bootph-all; + }; + + mdlc_vipn: system-controller@c3060000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc3060000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_vips: system-controller@c3460000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc3460000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_vio: system-controller@c5000000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc5000000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_pere: system-controller@c08f0000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc08f0000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_perw: system-controller@c05d0000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc05d0000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr0: system-controller@e8000000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8000000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr1: system-controller@e8080000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8080000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr2: system-controller@e8100000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8100000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr3: system-controller@e8180000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8180000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr4: system-controller@e8200000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8200000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr5: system-controller@e8280000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8280000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr6: system-controller@e8300000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8300000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ddr7: system-controller@e8380000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe8380000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_hscn: system-controller@c9c90000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc9c90000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_rt: system-controller@19440000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0x19440000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_top: system-controller@c6480000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc6480000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_hscs: system-controller@de200000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xde200000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_imn: system-controller@c1990000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1990000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_ims: system-controller@c1d90000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1d90000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_gpc: system-controller@cb510000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xcb510000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_dsp: system-controller@cbe90000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xcbe90000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_mm: system-controller@e9980000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xe9980000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_npu0: system-controller@d2c30000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xd2c30000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_npu1: system-controller@d6c30000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xd6c30000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_cmnn: system-controller@ca410000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xca410000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_cmns: system-controller@ca510000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xca510000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_scp: system-controller@c1330000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1330000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; + + mdlc_aon: system-controller@c1338000 { + compatible =3D "renesas,r8a78000-mdlc"; + reg =3D <0 0xc1338000 0 0x1000>; + #power-domain-cells =3D <2>; + #reset-cells =3D <1>; + bootph-all; + }; }; =20 timer { --=20 2.43.0 From nobody Wed Jun 17 02:50:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B44D23DA5A5; Tue, 21 Apr 2026 18:13:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795189; cv=none; b=ALB8b2cJMY7FTh9tCoTi+Rqvfw3Qa1p8nSc+rpujQtK0FeOWp3nWbTkcoPLBs+MwiFIrI7i4Zz1BraCYlH+sjLxj6APnvXvoiQOL2gI+4ouxTN0KCZN7HT4Jgo5Y8M7eOSEjouXrs9FqdYWNhEoSLDeopX5j2rPbfJ2lgVPeMug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776795189; c=relaxed/simple; bh=5aEgK8XJ1yvOkRaOquOvl9TQhJ+t78QHDJ+2/j38IY4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eMzd77lxhr3Xxt+pGs03H++zUXqh9UW7aR75Dg3l24krJ51JLeBXYr1Rwluxzuj9yXCQFDJDX7dCpb+zB2wr19IFmfp3bYN0jBfWvwhT3uHZzhqIWf18EZs4Wbks75H/GtuY+2oleck56M1QVoj2vZAv1bFdhXvzCrr30jloReQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50330C2BCB4; Tue, 21 Apr 2026 18:13:04 +0000 (UTC) From: Geert Uytterhoeven To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Saravana Kannan , Michael Turquette , Stephen Boyd , Philipp Zabel , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Florian Fainelli , Wolfram Sang , Marek Vasut , Kuninori Morimoto Cc: arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 14/14] arm64: dts: renesas: ironhide: Add CPG/MDLC firmware properties Date: Tue, 21 Apr 2026 20:11:47 +0200 Message-ID: <258e1985bfa75ca0b3c98bd083628f9b6c7887fc.1776793163.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Link the various Clock Pulse Generator (CPG) and Module Controller (MDLC) device nodes to their SCMI provider. Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a78000-ironhide.dts | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64= /boot/dts/renesas/r8a78000-ironhide.dts index 2fb9557a7eb9dbb7..c6d1a9b5ba433c54 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts @@ -99,6 +99,10 @@ memory@1e00000000 { }; }; =20 +&cpg { + firmware =3D <&scmi>; +}; + &extal_clk { clock-frequency =3D <16666600>; }; @@ -112,6 +116,118 @@ &hscif0 { status =3D "okay"; }; =20 +&mdlc_aon { + firmware =3D <&scmi>; +}; + +&mdlc_cmnn { + firmware =3D <&scmi>; +}; + +&mdlc_cmns { + firmware =3D <&scmi>; +}; + +&mdlc_ddr0 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr1 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr2 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr3 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr4 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr5 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr6 { + firmware =3D <&scmi>; +}; + +&mdlc_ddr7 { + firmware =3D <&scmi>; +}; + +&mdlc_dsp { + firmware =3D <&scmi>; +}; + +&mdlc_gpc { + firmware =3D <&scmi>; +}; + +&mdlc_hscn { + firmware =3D <&scmi>; +}; + +&mdlc_hscs { + firmware =3D <&scmi>; +}; + +&mdlc_imn { + firmware =3D <&scmi>; +}; + +&mdlc_ims { + firmware =3D <&scmi>; +}; + +&mdlc_mm { + firmware =3D <&scmi>; +}; + +&mdlc_npu0 { + firmware =3D <&scmi>; +}; + +&mdlc_npu1 { + firmware =3D <&scmi>; +}; + +&mdlc_pere { + firmware =3D <&scmi>; +}; + +&mdlc_perw { + firmware =3D <&scmi>; +}; + +&mdlc_rt { + firmware =3D <&scmi>; +}; + +&mdlc_scp { + firmware =3D <&scmi>; +}; + +&mdlc_top { + firmware =3D <&scmi>; +}; + +&mdlc_vio { + firmware =3D <&scmi>; +}; + +&mdlc_vipn { + firmware =3D <&scmi>; +}; + +&mdlc_vips { + firmware =3D <&scmi>; +}; + &mfis_scp { status =3D "okay"; }; --=20 2.43.0