From nobody Sun Apr 12 22:00:07 2026 Received: from mail-244123.protonmail.ch (mail-244123.protonmail.ch [109.224.244.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87751312825 for ; Fri, 10 Apr 2026 09:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775814933; cv=none; b=eOSanyOMSroiTxEYUvOqYYK6zrIq/1NhsLMX+yqoCLCAiqQaNL/5pyEXxHhhCkjDVs0nAYPll2T1i/ULrIRslGHFu3BgBJZ2f6K3zbncxS4eB4CsoKXU1bJKodeZhc3Y5riSp9o8DBCdAVpdBNieRw7jQZ1CwrYkH16pJBskYl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775814933; c=relaxed/simple; bh=FzXBIw1vdsKfYogXbUn3HuPwaqm1ZjhIXwxLmyPxSHE=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eodp3obpkcdbJAG4c4Cra+RXGVq9t9GuZEuF7/2J1x39p7C4wITmtr1D0DvL5bF7HX8USC5/pmHvpA6S+q6TioBaiDrzl86IE9uKt7o1GjSXFWCuncwpPNcQkZKWYW4ydKxJEES/A9usQ8X996hMkZx9nvhvsOTChjCyVv1pqRI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=k5tYU5XI; arc=none smtp.client-ip=109.224.244.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="k5tYU5XI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775814929; x=1776074129; bh=P3Nnw9i6S+QzWm5UK1Oh5jO4xjBLfUIrVCJ6W6qb0cg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=k5tYU5XIUxSUYKuXpVOZHgaixMRlPRGZspZxHYmkRFF6/TY5dMiENCh+OfpBj9GZR xsn7TcYt5DVObEYpxdr4x1nEnbFk4mXJuuf9XGapVHCQSxaFiPctfIhSAkzPyXapQI 0g90XeLsHO3Kcw6SokTfHqK1u1ECw6xH0G5HjhGMZQ5dL9f5C7QY0ZMA4eYebScsdl M3kCz8N419nQ/N9m77ezHOb6lb+W7lpnX9WRKcLAT3v/Qcj/UjsE0XZRBGUJYXvbPT +pJyVS84V2jUMuD3+Dzbx7E1MxLnsqcCSN7GXy5qXfvjtAbQjODnPi8SV7GmmqTYqz 8lilxwEVU/NUg== Date: Fri, 10 Apr 2026 09:55:25 +0000 To: peterz@infradead.org, ryan.roberts@arm.com, ilpo.jarvinen@linux.intel.com, maciej.wieczor-retman@intel.com, jgross@suse.com, morbo@google.com, mingo@redhat.com, ljs@kernel.org, nathan@kernel.org, shuah@kernel.org, akpm@linux-foundation.org, james.morse@arm.com, oleg@redhat.com, houwenlong.hwl@antgroup.com, xin@zytor.com, justinstitt@google.com, seanjc@google.com, hpa@zytor.com, perry.yuan@amd.com, bp@alien8.de, dave.hansen@linux.intel.com, sohil.mehta@intel.com, tglx@kernel.org, nick.desaulniers+lkml@gmail.com From: Maciej Wieczor-Retman Cc: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, llvm@lists.linux.dev, x86@kernel.org, m.wieczorretman@pm.me Subject: [PATCH v6 1/3] x86/process: Shorten the LAM tag width Message-ID: <79720f2640839b15f22e3618136b084cb376456b.1775813245.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 9df94bdd32eb8008f8992a65852d1e219dfccc88 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman With the announcement of ChkTag, it's worth preparing a stable x86 linear address masking (lam) user interface. One important aspect of lam is the tag width, and aligning it with other industry solutions can provide a more popular, generalized interface that other technologies could utilize. ChkTag will use 4-bit tags and since that's the direction other memory tagging implementations seem to be taking too (for example Arm's MTE) it's reasonable to converge lam in linux to the same specification. Even though x86's LAM supports 6-bit tags it is beneficial to shorten lam to 4 bits as ChkTag will likely be the main user of the interface and such connection should simplify things in the future. Shrink the maximum acceptable tag width from 6 to 4. Define tag width and the untagging mask as constants with names matching the arch_prctl() LAM cases. This way it's easier to see where each value can be returned to userspace. Signed-off-by: Maciej Wieczor-Retman --- Changelog v6: - Rename the define constants so they match the arch_prctl() switch case na= mes and update the patch message. - Define LAM most/least significant bits so they fit better into GENMASK(). - Remove 'default' from the patch subject. Changelog v4: - Ditch the default wording in the patch message. - Add the imperative last line as Dave suggested. Changelog v3: - Remove the variability of the lam width after the debugfs part was removed from the patchset. arch/x86/kernel/process_64.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 08e72f429870..d6f8e71156cd 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -797,7 +797,10 @@ static long prctl_map_vdso(const struct vdso_image *im= age, unsigned long addr) =20 #ifdef CONFIG_ADDRESS_MASKING =20 -#define LAM_U57_BITS 6 +#define LAM_TAG_BITS 4 +#define LAM_LS_BIT 57 +#define LAM_MS_BIT (LAM_LS_BIT + LAM_TAG_BITS - 1) /* 60 */ +#define LAM_UNTAG_MASK ~GENMASK(LAM_MS_BIT, LAM_LS_BIT) =20 static void enable_lam_func(void *__mm) { @@ -814,7 +817,7 @@ static void enable_lam_func(void *__mm) static void mm_enable_lam(struct mm_struct *mm) { mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; - mm->context.untag_mask =3D ~GENMASK(62, 57); + mm->context.untag_mask =3D LAM_UNTAG_MASK; =20 /* * Even though the process must still be single-threaded at this @@ -850,7 +853,7 @@ static int prctl_enable_tagged_addr(struct mm_struct *m= m, unsigned long nr_bits) return -EBUSY; } =20 - if (!nr_bits || nr_bits > LAM_U57_BITS) { + if (!nr_bits || nr_bits > LAM_TAG_BITS) { mmap_write_unlock(mm); return -EINVAL; } @@ -965,7 +968,7 @@ long do_arch_prctl_64(struct task_struct *task, int opt= ion, unsigned long arg2) if (!cpu_feature_enabled(X86_FEATURE_LAM)) return put_user(0, (unsigned long __user *)arg2); else - return put_user(LAM_U57_BITS, (unsigned long __user *)arg2); + return put_user(LAM_TAG_BITS, (unsigned long __user *)arg2); #endif case ARCH_SHSTK_ENABLE: case ARCH_SHSTK_DISABLE: --=20 2.53.0 From nobody Sun Apr 12 22:00:07 2026 Received: from mail-106120.protonmail.ch (mail-106120.protonmail.ch [79.135.106.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CE453783CC for ; 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charset="utf-8" From: Maciej Wieczor-Retman For simplicity only the LAM_U57 mode is implemented in the kernel. No matter whether the enabled paging mode is 5-level or 4-level the masked tag bits are the same as on a 5-level system. Remove two mentions of LAM_U48 which implied that it could be enabled. Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Sohil Mehta --- Changelog v6: - Add Sohil's Reviewed-by. arch/x86/include/asm/mmu.h | 2 +- arch/x86/include/asm/tlbflush.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 0fe9c569d171..9dcfce439c19 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -49,7 +49,7 @@ typedef struct { unsigned long flags; =20 #ifdef CONFIG_ADDRESS_MASKING - /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ + /* Active LAM mode: X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; =20 /* Significant bits of the virtual address. Excludes tag bits. */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 5a3cdc439e38..94c5ca1febaf 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -110,7 +110,7 @@ struct tlb_state { /* * Active LAM mode. * - * X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM + * X86_CR3_LAM_U57 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM * disabled. */ u8 lam; --=20 2.53.0 From nobody Sun Apr 12 22:00:07 2026 Received: from mail-24418.protonmail.ch (mail-24418.protonmail.ch [109.224.244.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA610312825 for ; Fri, 10 Apr 2026 09:55:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775814956; cv=none; b=sWL5jQx4JrNKvwMAtiCCQpDKywRZa6YdJvgZHJkpfpD0u/yMEf9sWBkbpjh+mz4gekfj+kxiwLYCqV4GVDYUiB5+BV3+4+9t7+u/lR7c1FbbPxcRynB08/fpIioZwZgVHkOsLPjgw/K2bwmkUJM2fed8aoEkY3DxKJitM+IJ0nM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775814956; c=relaxed/simple; bh=EhZxedE48iyEtofQO3IsZdajA3ZW+sdCe0Tmu4JXA8A=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LD032jCad7qAv5D70KCpe3tE3bSqpX3/KCsSa7qdqOySZ3iQqV/Mwtt55qKAb6zw4OBhYtmS4nuqEplK6sc0cys4iW8AJkolq+7ri6/XnbAy+n3tViXasnpEIVizvic+E1T9gIYcw9GGRRLJZU78YZLwFwzbyP0ygZ3qCdIbZSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=S4V5MyFG; arc=none smtp.client-ip=109.224.244.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="S4V5MyFG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775814952; x=1776074152; bh=4lwqm41kb3Xq61Z1+ag7RwAcMowrPSu9Ny1DsvAYvcs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=S4V5MyFGu3qubujb6NYq44G7KfXOkW5i4aNAHvabxKaVGNGfaj+4jcpzkHeahcXb3 /akM9qNJFerJymohInmpbBwsS2qr4zN0cr0jt59YEFLMO0lYXm8baUUQHKl5PbuykJ GGvKVinvVyNyMOt1NHobRTO/ekKdsZqErBXBD/9Ylt+f7ecHscsqJZAdE5VyPGZU57 lXKOAuRdkAAA3DfBowTEte4lEolYXKUo0pVpwNeq7GTd6FvR3Egt+55ZHdY7wDgX+W 4hZ8XmHsTdg0hyv9Yk/QeqfUpb2bkc/y8d80CFl8So6gXdbwn00G4udJRUvqLjZekZ 24YxbfBs77q8g== Date: Fri, 10 Apr 2026 09:55:48 +0000 To: peterz@infradead.org, ryan.roberts@arm.com, ilpo.jarvinen@linux.intel.com, maciej.wieczor-retman@intel.com, jgross@suse.com, morbo@google.com, mingo@redhat.com, ljs@kernel.org, nathan@kernel.org, shuah@kernel.org, akpm@linux-foundation.org, james.morse@arm.com, oleg@redhat.com, houwenlong.hwl@antgroup.com, xin@zytor.com, justinstitt@google.com, seanjc@google.com, hpa@zytor.com, perry.yuan@amd.com, bp@alien8.de, dave.hansen@linux.intel.com, sohil.mehta@intel.com, tglx@kernel.org, nick.desaulniers+lkml@gmail.com From: Maciej Wieczor-Retman Cc: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, llvm@lists.linux.dev, x86@kernel.org, m.wieczorretman@pm.me Subject: [PATCH v6 3/3] selftests/lam: Update LAM tag width and cleanup names Message-ID: <20687a8abed771847a4056e64aedbc073076d477.1775813245.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: ec2a6d2f0cd9e70992ae524544427f5ae548dd11 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman After the tag width in LAM (Linear Address Masking) is set to 4 bits, the value isn't strictly related to the CPU features like LAM_U57 or LAM_U48. To emphasise this, remove mentions of _U57 from the selftest and update the tag width. Define GENMASK() so the selftest defines can match the kernel ones. That way it's easier to find or synchronize the two sets of values. Signed-off-by: Maciej Wieczor-Retman --- Changelog v6: - Update the patch subject that was not accurate after debugfs part got removed. - Fix one comment I missed. - Define GENMASK() and change defined constants so they match the ones in the kernel (from patch 1/3). Changelog v4: - Remove the 'default' wording. Changelog v3: - Redo the patch after the removal of the debugfs part. tools/testing/selftests/x86/lam.c | 94 ++++++++++++++++--------------- 1 file changed, 49 insertions(+), 45 deletions(-) diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c index 1919fa6daec0..f14600e74d8c 100644 --- a/tools/testing/selftests/x86/lam.c +++ b/tools/testing/selftests/x86/lam.c @@ -24,11 +24,15 @@ # error This test is 64-bit only #endif =20 +#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (__BITS_PER_LONG - 1 - (= h)))) + /* LAM modes, these definitions were copied from kernel code */ #define LAM_NONE 0 -#define LAM_U57_BITS 6 +#define LAM_TAG_BITS 4 +#define LAM_LS_BIT 57 +#define LAM_MS_BIT (LAM_LS_BIT + LAM_TAG_BITS - 1) /* 60 */ +#define LAM_UNTAG_MASK ~GENMASK(LAM_MS_BIT, LAM_LS_BIT) =20 -#define LAM_U57_MASK (0x3fULL << 57) /* arch prctl for LAM */ #define ARCH_GET_UNTAG_MASK 0x4001 #define ARCH_ENABLE_TAGGED_ADDR 0x4002 @@ -51,8 +55,8 @@ #define GET_USER_KERNEL 3 =20 #define TEST_MASK 0x7f -#define L5_SIGN_EXT_MASK (0xFFUL << 56) -#define L4_SIGN_EXT_MASK (0x1FFFFUL << 47) +#define L5_SIGN_EXT_MASK GENMASK(63, 56) +#define L4_SIGN_EXT_MASK GENMASK(63, 47) =20 #define LOW_ADDR (0x1UL << 30) #define HIGH_ADDR (0x3UL << 48) @@ -175,7 +179,7 @@ static int set_lam(unsigned long lam) int ret =3D 0; uint64_t ptr =3D 0; =20 - if (lam !=3D LAM_U57_BITS && lam !=3D LAM_NONE) + if (lam !=3D LAM_TAG_BITS && lam !=3D LAM_NONE) return -1; =20 /* Skip check return */ @@ -185,8 +189,8 @@ static int set_lam(unsigned long lam) syscall(SYS_arch_prctl, ARCH_GET_UNTAG_MASK, &ptr); =20 /* Check mask returned is expected */ - if (lam =3D=3D LAM_U57_BITS) - ret =3D (ptr !=3D ~(LAM_U57_MASK)); + if (lam =3D=3D LAM_TAG_BITS) + ret =3D (ptr !=3D LAM_UNTAG_MASK); else if (lam =3D=3D LAM_NONE) ret =3D (ptr !=3D -1ULL); =20 @@ -204,8 +208,8 @@ static unsigned long get_default_tag_bits(void) perror("Fork failed."); } else if (pid =3D=3D 0) { /* Set LAM mode in child process */ - if (set_lam(LAM_U57_BITS) =3D=3D 0) - lam =3D LAM_U57_BITS; + if (set_lam(LAM_TAG_BITS) =3D=3D 0) + lam =3D LAM_TAG_BITS; else lam =3D LAM_NONE; exit(lam); @@ -230,8 +234,8 @@ static int get_lam(void) return -1; =20 /* Check mask returned is expected */ - if (ptr =3D=3D ~(LAM_U57_MASK)) - ret =3D LAM_U57_BITS; + if (ptr =3D=3D LAM_UNTAG_MASK) + ret =3D LAM_TAG_BITS; else if (ptr =3D=3D -1ULL) ret =3D LAM_NONE; =20 @@ -247,10 +251,10 @@ static uint64_t set_metadata(uint64_t src, unsigned l= ong lam) srand(time(NULL)); =20 switch (lam) { - case LAM_U57_BITS: /* Set metadata in bits 62:57 */ + case LAM_TAG_BITS: /* Set metadata in bits 60:57 */ /* Get a random non-zero value as metadata */ - metadata =3D (rand() % ((1UL << LAM_U57_BITS) - 1) + 1) << 57; - metadata |=3D (src & ~(LAM_U57_MASK)); + metadata =3D (rand() % ((1UL << LAM_TAG_BITS) - 1) + 1) << 57; + metadata |=3D (src & LAM_UNTAG_MASK); break; default: metadata =3D src; @@ -291,7 +295,7 @@ int handle_max_bits(struct testcases *test) unsigned long bits =3D 0; =20 if (exp_bits !=3D LAM_NONE) - exp_bits =3D LAM_U57_BITS; + exp_bits =3D LAM_TAG_BITS; =20 /* Get LAM max tag bits */ if (syscall(SYS_arch_prctl, ARCH_GET_MAX_TAG_BITS, &bits) =3D=3D -1) @@ -719,8 +723,8 @@ int do_uring(unsigned long lam) uint64_t addr =3D ((uint64_t)fi->iovecs[i].iov_base); =20 switch (lam) { - case LAM_U57_BITS: /* Clear bits 62:57 */ - addr =3D (addr & ~(LAM_U57_MASK)); + case LAM_TAG_BITS: /* Clear bits 60:57 */ + addr =3D (addr & LAM_UNTAG_MASK); break; } free((void *)addr); @@ -937,14 +941,14 @@ static void run_test(struct testcases *test, int coun= t) static struct testcases uring_cases[] =3D { { .later =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_uring, - .msg =3D "URING: LAM_U57. Dereferencing pointer with metadata\n", + .msg =3D "URING: LAM. Dereferencing pointer with metadata\n", }, { .later =3D 1, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_uring, .msg =3D "URING:[Negative] Disable LAM. Dereferencing pointer with metad= ata.\n", }, @@ -953,14 +957,14 @@ static struct testcases uring_cases[] =3D { static struct testcases malloc_cases[] =3D { { .later =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_malloc, - .msg =3D "MALLOC: LAM_U57. Dereferencing pointer with metadata\n", + .msg =3D "MALLOC: LAM. Dereferencing pointer with metadata\n", }, { .later =3D 1, .expected =3D 2, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_malloc, .msg =3D "MALLOC:[Negative] Disable LAM. Dereferencing pointer with meta= data.\n", }, @@ -976,41 +980,41 @@ static struct testcases bits_cases[] =3D { static struct testcases syscall_cases[] =3D { { .later =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_syscall, - .msg =3D "SYSCALL: LAM_U57. syscall with metadata\n", + .msg =3D "SYSCALL: LAM. syscall with metadata\n", }, { .later =3D 1, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_syscall, .msg =3D "SYSCALL:[Negative] Disable LAM. Dereferencing pointer with met= adata.\n", }, { .later =3D GET_USER_USER, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER: get_user() and pass a properly tagged user pointer.\= n", }, { .later =3D GET_USER_KERNEL_TOP, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER:[Negative] get_user() with a kernel pointer and the t= op bit cleared.\n", }, { .later =3D GET_USER_KERNEL_BOT, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER:[Negative] get_user() with a kernel pointer and the b= ottom sign-extension bit cleared.\n", }, { .later =3D GET_USER_KERNEL, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER:[Negative] get_user() and pass a kernel pointer.\n", }, @@ -1020,60 +1024,60 @@ static struct testcases mmap_cases[] =3D { { .later =3D 1, .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .addr =3D HIGH_ADDR, .test_func =3D handle_mmap, - .msg =3D "MMAP: First mmap high address, then set LAM_U57.\n", + .msg =3D "MMAP: First mmap high address, then set LAM.\n", }, { .later =3D 0, .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .addr =3D HIGH_ADDR, .test_func =3D handle_mmap, - .msg =3D "MMAP: First LAM_U57, then High address.\n", + .msg =3D "MMAP: First LAM, then High address.\n", }, { .later =3D 0, .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .addr =3D LOW_ADDR, .test_func =3D handle_mmap, - .msg =3D "MMAP: First LAM_U57, then Low address.\n", + .msg =3D "MMAP: First LAM, then Low address.\n", }, }; =20 static struct testcases inheritance_cases[] =3D { { .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_inheritance, - .msg =3D "FORK: LAM_U57, child process should get LAM mode same as paren= t\n", + .msg =3D "FORK: LAM, child process should get LAM mode same as parent\n", }, { .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_thread, - .msg =3D "THREAD: LAM_U57, child thread should get LAM mode same as pare= nt\n", + .msg =3D "THREAD: LAM, child thread should get LAM mode same as parent\n= ", }, { .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_thread_enable, .msg =3D "THREAD: [NEGATIVE] Enable LAM in child.\n", }, { .expected =3D 1, .later =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_thread, .msg =3D "THREAD: [NEGATIVE] Enable LAM in parent after thread created.\= n", }, { .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_TAG_BITS, .test_func =3D handle_execve, - .msg =3D "EXECVE: LAM_U57, child process should get disabled LAM mode\n", + .msg =3D "EXECVE: LAM, child process should get disabled LAM mode\n", }, }; =20 @@ -1224,7 +1228,7 @@ int handle_pasid(struct testcases *test) if (tmp & 0x1) { /* run set lam mode*/ if ((runed & 0x1) =3D=3D 0) { - err =3D set_lam(LAM_U57_BITS); + err =3D set_lam(LAM_TAG_BITS); runed =3D runed | 0x1; } else err =3D 1; --=20 2.53.0