From nobody Wed Apr 8 03:08:37 2026 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C5233A0B05; Tue, 7 Apr 2026 17:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775583939; cv=none; b=VRn3S25ygjz/5ievo7Tu404N90v6qKqaBwatOHYYEaxexkj8r1cff4z7j+yJBEbQDmxPjiCKUx6aAA7mqiLNKvUuSUmAcLpLL0CLswrBo+H69uHJy1zylHk+PAdGrzn9XAy4xNqem5M5YCWwygeeJSrn2GMB2SkSPQ5oDqFfDXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775583939; c=relaxed/simple; bh=QCvNrVBR+UQpZWHcJILEpoR99lJLLIBXUMiv9hufMAc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kPxUYJwfaT+qacexLwAGzmxhymoQ8NA357YRBBeo/4ohLA0/XBYU31pCmm3c1zZf17HfJXhZ60xPismw+9/zdoLyZHHawa2P0Z9RQwZ85rUe49sb0Pm6XTRcY8U0hKNSvjPIoVKisD9oY3f4YnplWG3mo/Ux8gDTfe+7Rqs9NXU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=qRc/istY; arc=none smtp.client-ip=185.70.43.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="qRc/istY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775583924; x=1775843124; bh=Jue6vVhHghVxlyod3DDyXibcUYZsmo8usQOXh8QIwdM=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=qRc/istYVPGaNJqfY76Rl82eXyWWqTy5JWG5C8lxC58jn4j3kfBKiu605rODy2mD2 hCDCwFYgiaTseeuEom/YtmPzaGqubKRFMXqsjYg2JDyjz+/iIg6PNgK1zcqSk3ck4Q bOpGTCuZumHXX54mhNQB+VdrqUmryPrxJ8c2G/peKUuITs/Irr4Ct/W39zhpHOCU8z OjhwjkzDUCEGPx9YqSx+SkeaKwP7DPBwxwbzpM7FuIoGJwRsgP1po0gO/k8qmOyEDW gVBlorFQisBYDgC7bsgVa2Czs0CEyqft0AlxqYBICRk/HxHuYOL+SprxjCTpWzFt2e En4PautBUXYag== Date: Tue, 07 Apr 2026 17:45:20 +0000 To: houwenlong.hwl@antgroup.com, dave.hansen@linux.intel.com, ryan.roberts@arm.com, nick.desaulniers+lkml@gmail.com, bp@alien8.de, will@kernel.org, maciej.wieczor-retman@intel.com, david@kernel.org, nathan@kernel.org, justinstitt@google.com, seanjc@google.com, perry.yuan@amd.com, oleg@redhat.com, tglx@kernel.org, hpa@zytor.com, james.morse@arm.com, mingo@redhat.com, akpm@linux-foundation.org, jgross@suse.com, peterz@infradead.org, morbo@google.com, ilpo.jarvinen@linux.intel.com, xin@zytor.com, shuah@kernel.org From: Maciej Wieczor-Retman Cc: x86@kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, m.wieczorretman@pm.me Subject: [PATCH v5 1/3] x86/process: Shorten the default LAM tag width Message-ID: In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 708afe33024b2f3955356fd5ac5e9c619a50ed3f Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman With the announcement of ChkTag, it's worth preparing a stable x86 linear address masking (lam) user interface. One important aspect of lam is the tag width, and aligning it with other industry solutions can provide a more popular, generalized interface that other technologies could utilize. ChkTag will use 4-bit tags and since that's the direction other memory tagging implementations seem to be taking too (for example Arm's MTE) it's reasonable to converge lam in linux to the same specification. Even though x86's LAM supports 6-bit tags it is beneficial to shorten lam to 4 bits as ChkTag will likely be the main user of the interface and such connection should simplify things in the future. Shrink the maximum acceptable tag width from 6 to 4. Signed-off-by: Maciej Wieczor-Retman --- Changelog v4: - Ditch the default wording in the patch message. - Add the imperative last line as Dave suggested. Changelog v3: - Remove the variability of the lam width after the debugfs part was removed from the patchset. arch/x86/kernel/process_64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 08e72f429870..1a0e96835bbc 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -797,7 +797,7 @@ static long prctl_map_vdso(const struct vdso_image *ima= ge, unsigned long addr) =20 #ifdef CONFIG_ADDRESS_MASKING =20 -#define LAM_U57_BITS 6 +#define LAM_DEFAULT_BITS 4 =20 static void enable_lam_func(void *__mm) { @@ -814,7 +814,7 @@ static void enable_lam_func(void *__mm) static void mm_enable_lam(struct mm_struct *mm) { mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; - mm->context.untag_mask =3D ~GENMASK(62, 57); + mm->context.untag_mask =3D ~GENMASK(57 + LAM_DEFAULT_BITS - 1, 57); =20 /* * Even though the process must still be single-threaded at this @@ -850,7 +850,7 @@ static int prctl_enable_tagged_addr(struct mm_struct *m= m, unsigned long nr_bits) return -EBUSY; } =20 - if (!nr_bits || nr_bits > LAM_U57_BITS) { + if (!nr_bits || nr_bits > LAM_DEFAULT_BITS) { mmap_write_unlock(mm); return -EINVAL; } @@ -965,7 +965,7 @@ long do_arch_prctl_64(struct task_struct *task, int opt= ion, unsigned long arg2) if (!cpu_feature_enabled(X86_FEATURE_LAM)) return put_user(0, (unsigned long __user *)arg2); else - return put_user(LAM_U57_BITS, (unsigned long __user *)arg2); + return put_user(LAM_DEFAULT_BITS, (unsigned long __user *)arg2); #endif case ARCH_SHSTK_ENABLE: case ARCH_SHSTK_DISABLE: --=20 2.53.0 From nobody Wed Apr 8 03:08:37 2026 Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 506273D34A0; Tue, 7 Apr 2026 17:45:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.30 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" From: Maciej Wieczor-Retman For simplicity only the LAM_U57 mode is implemented in the kernel. No matter whether the enabled paging mode is 5-level or 4-level the masked tag bits are the same as on a 5-level system. Remove two mentions of LAM_U48 which implied that it could be enabled. Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Sohil Mehta --- arch/x86/include/asm/mmu.h | 2 +- arch/x86/include/asm/tlbflush.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 0fe9c569d171..9dcfce439c19 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -49,7 +49,7 @@ typedef struct { unsigned long flags; =20 #ifdef CONFIG_ADDRESS_MASKING - /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ + /* Active LAM mode: X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; =20 /* Significant bits of the virtual address. Excludes tag bits. */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 5a3cdc439e38..94c5ca1febaf 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -110,7 +110,7 @@ struct tlb_state { /* * Active LAM mode. * - * X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM + * X86_CR3_LAM_U57 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM * disabled. */ u8 lam; --=20 2.53.0 From nobody Wed Apr 8 03:08:37 2026 Received: from mail-106119.protonmail.ch (mail-106119.protonmail.ch [79.135.106.119]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 178CF3D3336 for ; Tue, 7 Apr 2026 17:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.119 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775583947; cv=none; b=ZEm9PzbZi5Ul64Q2fkBdPO390xeWnxSvn+juvNnwRKmZufHrflEhKOY2VOBKmxsZ9tBRreFBLDEv09gDa+Or6xrfGdgHkHb7H3YMAp//XezX5Zm8nk2KnqGmkX+TuBiujo9DMKLXut24QcgdUh0k2HLGD5Ggi+HKpFMb4E4w8PU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775583947; c=relaxed/simple; bh=ndlEYMHwNVLY0ZDNRaBYVoKCtbHQwKNvD5Yoahc+3h4=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ExSYR6nmAjBXM4F2qJrhmUWwHxgo5sfWD+NFcMdS1fnaENthN0mfvU6kuRLsHBZfiVL9MkL9afCJsaT+NRK8EJjvMMb39Ph6i/x2dKkszfizwT3SHXQo3X1J/GrwD3xmYFbn/Y4j73OgQGLrj2ZXTnUhy7zz8JLP+8wzbtHnDzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=TaXEE9NZ; arc=none smtp.client-ip=79.135.106.119 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="TaXEE9NZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775583939; x=1775843139; bh=frxC/97h47KcnStF4BkXv4YUpUyn1kKMQMG6V/5CXyQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=TaXEE9NZ9Jt1SG2T1C0MJa7wMScoNm6qjAZK2EJmKVOyyqEK3ncD14bNRq6pDyisb tCLDNxXRUsqkra45o1if3sFtRrKZ9riOmn90XTWUhILFGgl5JSmVcklTDgJ+LviZrg 7RIv8Cp0qlkhWyC4Uq1AImf5cANfVazGvNex+NmKrYFwAANVbxgweX6dHK+yp9RO5y mgxHKdylMj9B4bxM+saHlgzS7A5+amSgcrqUjSXzBV1chqqAdioKRg7bleIt74ewhI VQAJjSz+lAKZAywx3HXF81fVDVkbKGc+XhqygTn9eIPQlqlorplLtTD+syXAENlXyT DanortkwHVzFQ== Date: Tue, 07 Apr 2026 17:45:34 +0000 To: houwenlong.hwl@antgroup.com, dave.hansen@linux.intel.com, ryan.roberts@arm.com, nick.desaulniers+lkml@gmail.com, bp@alien8.de, will@kernel.org, maciej.wieczor-retman@intel.com, david@kernel.org, nathan@kernel.org, justinstitt@google.com, seanjc@google.com, perry.yuan@amd.com, oleg@redhat.com, tglx@kernel.org, hpa@zytor.com, james.morse@arm.com, mingo@redhat.com, akpm@linux-foundation.org, jgross@suse.com, peterz@infradead.org, morbo@google.com, ilpo.jarvinen@linux.intel.com, xin@zytor.com, shuah@kernel.org From: Maciej Wieczor-Retman Cc: x86@kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, m.wieczorretman@pm.me Subject: [PATCH v5 3/3] selftests/lam: Add test cases for different LAM tag widths Message-ID: <91141bc8dc7241b0c77208c743a7e051c782ccef.1775581451.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: a66203fa7a0ce54fab6bb2c5d556c4fd9e12a09b Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman After the tag width in LAM (Linear Address Masking) is set to 4 bits, the value isn't strictly related to the CPU features like LAM_U57 or LAM_U48. To emphasise this, remove mentions of _U57 from the selftest and update the bit width. Signed-off-by: Maciej Wieczor-Retman --- Changelog v4: - Remove the 'default' wording. Changelog v3: - Redo the patch after the removal of the debugfs part. tools/testing/selftests/x86/lam.c | 86 +++++++++++++++---------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c index 1919fa6daec0..d27f947ea694 100644 --- a/tools/testing/selftests/x86/lam.c +++ b/tools/testing/selftests/x86/lam.c @@ -26,9 +26,9 @@ =20 /* LAM modes, these definitions were copied from kernel code */ #define LAM_NONE 0 -#define LAM_U57_BITS 6 +#define LAM_BITS 4 =20 -#define LAM_U57_MASK (0x3fULL << 57) +#define LAM_MASK (0xfULL << 57) /* arch prctl for LAM */ #define ARCH_GET_UNTAG_MASK 0x4001 #define ARCH_ENABLE_TAGGED_ADDR 0x4002 @@ -175,7 +175,7 @@ static int set_lam(unsigned long lam) int ret =3D 0; uint64_t ptr =3D 0; =20 - if (lam !=3D LAM_U57_BITS && lam !=3D LAM_NONE) + if (lam !=3D LAM_BITS && lam !=3D LAM_NONE) return -1; =20 /* Skip check return */ @@ -185,8 +185,8 @@ static int set_lam(unsigned long lam) syscall(SYS_arch_prctl, ARCH_GET_UNTAG_MASK, &ptr); =20 /* Check mask returned is expected */ - if (lam =3D=3D LAM_U57_BITS) - ret =3D (ptr !=3D ~(LAM_U57_MASK)); + if (lam =3D=3D LAM_BITS) + ret =3D (ptr !=3D ~(LAM_MASK)); else if (lam =3D=3D LAM_NONE) ret =3D (ptr !=3D -1ULL); =20 @@ -204,8 +204,8 @@ static unsigned long get_default_tag_bits(void) perror("Fork failed."); } else if (pid =3D=3D 0) { /* Set LAM mode in child process */ - if (set_lam(LAM_U57_BITS) =3D=3D 0) - lam =3D LAM_U57_BITS; + if (set_lam(LAM_BITS) =3D=3D 0) + lam =3D LAM_BITS; else lam =3D LAM_NONE; exit(lam); @@ -230,8 +230,8 @@ static int get_lam(void) return -1; =20 /* Check mask returned is expected */ - if (ptr =3D=3D ~(LAM_U57_MASK)) - ret =3D LAM_U57_BITS; + if (ptr =3D=3D ~(LAM_MASK)) + ret =3D LAM_BITS; else if (ptr =3D=3D -1ULL) ret =3D LAM_NONE; =20 @@ -247,10 +247,10 @@ static uint64_t set_metadata(uint64_t src, unsigned l= ong lam) srand(time(NULL)); =20 switch (lam) { - case LAM_U57_BITS: /* Set metadata in bits 62:57 */ + case LAM_BITS: /* Set metadata in bits 62:57 */ /* Get a random non-zero value as metadata */ - metadata =3D (rand() % ((1UL << LAM_U57_BITS) - 1) + 1) << 57; - metadata |=3D (src & ~(LAM_U57_MASK)); + metadata =3D (rand() % ((1UL << LAM_BITS) - 1) + 1) << 57; + metadata |=3D (src & ~(LAM_MASK)); break; default: metadata =3D src; @@ -291,7 +291,7 @@ int handle_max_bits(struct testcases *test) unsigned long bits =3D 0; =20 if (exp_bits !=3D LAM_NONE) - exp_bits =3D LAM_U57_BITS; + exp_bits =3D LAM_BITS; =20 /* Get LAM max tag bits */ if (syscall(SYS_arch_prctl, ARCH_GET_MAX_TAG_BITS, &bits) =3D=3D -1) @@ -719,8 +719,8 @@ int do_uring(unsigned long lam) uint64_t addr =3D ((uint64_t)fi->iovecs[i].iov_base); =20 switch (lam) { - case LAM_U57_BITS: /* Clear bits 62:57 */ - addr =3D (addr & ~(LAM_U57_MASK)); + case LAM_BITS: /* Clear bits 60:57 */ + addr =3D (addr & ~(LAM_MASK)); break; } free((void *)addr); @@ -937,14 +937,14 @@ static void run_test(struct testcases *test, int coun= t) static struct testcases uring_cases[] =3D { { .later =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_uring, - .msg =3D "URING: LAM_U57. Dereferencing pointer with metadata\n", + .msg =3D "URING: LAM. Dereferencing pointer with metadata\n", }, { .later =3D 1, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_uring, .msg =3D "URING:[Negative] Disable LAM. Dereferencing pointer with metad= ata.\n", }, @@ -953,14 +953,14 @@ static struct testcases uring_cases[] =3D { static struct testcases malloc_cases[] =3D { { .later =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_malloc, - .msg =3D "MALLOC: LAM_U57. Dereferencing pointer with metadata\n", + .msg =3D "MALLOC: LAM. Dereferencing pointer with metadata\n", }, { .later =3D 1, .expected =3D 2, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_malloc, .msg =3D "MALLOC:[Negative] Disable LAM. Dereferencing pointer with meta= data.\n", }, @@ -976,41 +976,41 @@ static struct testcases bits_cases[] =3D { static struct testcases syscall_cases[] =3D { { .later =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_syscall, - .msg =3D "SYSCALL: LAM_U57. syscall with metadata\n", + .msg =3D "SYSCALL: LAM. syscall with metadata\n", }, { .later =3D 1, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_syscall, .msg =3D "SYSCALL:[Negative] Disable LAM. Dereferencing pointer with met= adata.\n", }, { .later =3D GET_USER_USER, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER: get_user() and pass a properly tagged user pointer.\= n", }, { .later =3D GET_USER_KERNEL_TOP, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER:[Negative] get_user() with a kernel pointer and the t= op bit cleared.\n", }, { .later =3D GET_USER_KERNEL_BOT, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER:[Negative] get_user() with a kernel pointer and the b= ottom sign-extension bit cleared.\n", }, { .later =3D GET_USER_KERNEL, .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D get_user_syscall, .msg =3D "GET_USER:[Negative] get_user() and pass a kernel pointer.\n", }, @@ -1020,60 +1020,60 @@ static struct testcases mmap_cases[] =3D { { .later =3D 1, .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .addr =3D HIGH_ADDR, .test_func =3D handle_mmap, - .msg =3D "MMAP: First mmap high address, then set LAM_U57.\n", + .msg =3D "MMAP: First mmap high address, then set LAM.\n", }, { .later =3D 0, .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .addr =3D HIGH_ADDR, .test_func =3D handle_mmap, - .msg =3D "MMAP: First LAM_U57, then High address.\n", + .msg =3D "MMAP: First LAM, then High address.\n", }, { .later =3D 0, .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .addr =3D LOW_ADDR, .test_func =3D handle_mmap, - .msg =3D "MMAP: First LAM_U57, then Low address.\n", + .msg =3D "MMAP: First LAM, then Low address.\n", }, }; =20 static struct testcases inheritance_cases[] =3D { { .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_inheritance, - .msg =3D "FORK: LAM_U57, child process should get LAM mode same as paren= t\n", + .msg =3D "FORK: LAM, child process should get LAM mode same as parent\n", }, { .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_thread, - .msg =3D "THREAD: LAM_U57, child thread should get LAM mode same as pare= nt\n", + .msg =3D "THREAD: LAM, child thread should get LAM mode same as parent\n= ", }, { .expected =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_thread_enable, .msg =3D "THREAD: [NEGATIVE] Enable LAM in child.\n", }, { .expected =3D 1, .later =3D 1, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_thread, .msg =3D "THREAD: [NEGATIVE] Enable LAM in parent after thread created.\= n", }, { .expected =3D 0, - .lam =3D LAM_U57_BITS, + .lam =3D LAM_BITS, .test_func =3D handle_execve, - .msg =3D "EXECVE: LAM_U57, child process should get disabled LAM mode\n", + .msg =3D "EXECVE: LAM, child process should get disabled LAM mode\n", }, }; =20 @@ -1224,7 +1224,7 @@ int handle_pasid(struct testcases *test) if (tmp & 0x1) { /* run set lam mode*/ if ((runed & 0x1) =3D=3D 0) { - err =3D set_lam(LAM_U57_BITS); + err =3D set_lam(LAM_BITS); runed =3D runed | 0x1; } else err =3D 1; --=20 2.53.0