From nobody Sun Apr 5 18:16:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AC273803FC for ; Wed, 1 Apr 2026 04:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019487; cv=none; b=bKoPE19WzTONSuyi+tbKfZ9DV3TXAGG7zcXRA8O30UeoMcekWlWZMAfF10d5Y38juVAG9yc1JJXT4fnzLMtlaTMv6lWITzpqevbAtHa6ywSuI/dzBV0lKMWfLLpD9ZVskFcULXYcEXhMPDLSBz6iyvTSoWFmzzNBso84ALJLxG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019487; c=relaxed/simple; bh=cLKp5iF31o6Ro9r4J6GrrD52iJ3EzOROMB6g+YbPXrw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dH+eJGYhiSrj/nOVMaoi+Y46r38IBWtD9ceq/5+pRzYdkdUZ5rT8C72E6i9wwVg/qLX0JevinMqWbtPBhUghZi6ntciKZtOVHHrKwawu/OksRNQkt2a4iSY4vtvXiTO6byb23DuZ6XYB0MO/5aBPOx7A3WAKwLddLkE4nEP4S3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RXEFrrVw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RXEFrrVw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E5A1C116C6; Wed, 1 Apr 2026 04:58:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019486; bh=cLKp5iF31o6Ro9r4J6GrrD52iJ3EzOROMB6g+YbPXrw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RXEFrrVwUpbOhHnrdZL16AYo6yF5Yw5vlMFFo0+NF8rGtkyiqh5X50CI6CPL2SoOv NIKfHyjL19zDnA2bLFECDnTMG4EswSr3zj3QS96DFJagYYw6iRgQJZwwRrP0fVsXse ys4B69cwfyNREQd2a5S8ZMLl/4gOv1YYOyZpplQgqyBw9B4Zl59aDsk/qpXwp2xdZd axaXUBrH8p7E0rBjsghvO5W5espo+05EL5uBs0aypGSgoVBf6rd4cDMOaDSiY4TFNt DZo5ejI1EzTnO/XcuE4jokB/Q6vGnAcFliNjm0FIqdpWXdh4u13zL1EPfhVXrwos4c LVKsjDcS8SGSQ== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 1/5] x86/apic: Drop AMD Extended Interrupt LVT macros Date: Wed, 1 Apr 2026 10:26:32 +0530 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD defines Extended Interrupt Local Vector Table (EILVT) registers to allow for additional interrupt sources. While the APIC registers for those are unique to AMD, the format of those registers follows the standard LVT registers. Drop EILVT-specific macros in favor of the standard APIC LVT macros. No functional change. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 5 ----- arch/x86/events/amd/ibs.c | 6 +++--- arch/x86/kernel/apic/apic.c | 12 ++++++------ arch/x86/kernel/cpu/mce/amd.c | 6 +++--- 4 files changed, 12 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index be39a543fbe5..f6d821656b02 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -142,11 +142,6 @@ #define APIC_EILVT_NR_AMD_10H 4 #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) -#define APIC_EILVT_MSG_FIX 0x0 -#define APIC_EILVT_MSG_SMI 0x2 -#define APIC_EILVT_MSG_NMI 0x4 -#define APIC_EILVT_MSG_EXT 0x7 -#define APIC_EILVT_MASKED (1 << 16) =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index eeb607b84dda..e0bd5051db2a 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1748,7 +1748,7 @@ EXPORT_SYMBOL(get_ibs_caps); =20 static inline int get_eilvt(int offset) { - return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1); + return !setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 1); } =20 static inline int put_eilvt(int offset) @@ -1897,7 +1897,7 @@ static void setup_APIC_ibs(void) if (offset < 0) goto failed; =20 - if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0)) + if (!setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 0)) return; failed: pr_warn("perf: IBS APIC setup failed on cpu #%d\n", @@ -1910,7 +1910,7 @@ static void clear_APIC_ibs(void) =20 offset =3D get_ibs_lvt_offset(); if (offset >=3D 0) - setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1); + setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_FIXED, 1); } =20 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 0c8970c4c3e3..639904911444 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -332,7 +332,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * Since the offsets must be consistent for all cores, we keep track * of the LVT offsets in software and reserve the offset for the same * vector also to be used on other cores. An offset is freed by - * setting the entry to APIC_EILVT_MASKED. + * setting the entry to APIC_LVT_MASKED. * * If the BIOS is right, there should be no conflicts. Otherwise a * "[Firmware Bug]: ..." error message is generated. However, if @@ -344,9 +344,9 @@ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { - return (old & APIC_EILVT_MASKED) - || (new =3D=3D APIC_EILVT_MASKED) - || ((new & ~APIC_EILVT_MASKED) =3D=3D old); + return (old & APIC_LVT_MASKED) + || (new =3D=3D APIC_LVT_MASKED) + || ((new & ~APIC_LVT_MASKED) =3D=3D old); } =20 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) @@ -358,13 +358,13 @@ static unsigned int reserve_eilvt_offset(int offset, = unsigned int new) =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); do { - vector =3D rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ + vector =3D rsvd & ~APIC_LVT_MASKED; /* 0: unassigned */ if (vector && !eilvt_entry_is_changeable(vector, new)) /* may not change if vectors are different */ return rsvd; } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); =20 - rsvd =3D new & ~APIC_EILVT_MASKED; + rsvd =3D new & ~APIC_LVT_MASKED; if (rsvd && rsvd !=3D vector) pr_info("LVT offset %d assigned for vector 0x%02x\n", offset, rsvd); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 146f4207a863..c82266cbd9f6 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -523,7 +523,7 @@ static void mce_threshold_block_init(struct threshold_b= lock *b, int offset) static int setup_APIC_mce_threshold(int reserved, int new) { if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, - APIC_EILVT_MSG_FIX, 0)) + APIC_DELIVERY_MODE_FIXED, 0)) return new; =20 return reserved; @@ -706,11 +706,11 @@ static void smca_enable_interrupt_vectors(void) return; =20 offset =3D (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; - if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, = 0)) + if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_F= IXED, 0)) data->thr_intr_en =3D 1; =20 offset =3D (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; - if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, = 0)) + if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_F= IXED, 0)) data->dfr_intr_en =3D 1; } =20 --=20 2.53.0 From nobody Sun Apr 5 18:16:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD07E351C3C for ; Wed, 1 Apr 2026 04:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019462; cv=none; b=aZLrOC/Z9BF7gQjiIhQYhumJrlkqJRzl84RCu589zpFb3HfMxlDe4zie2FvMN2pmZI3CFWEaqQFsknJ3CoT5XlK5unatrdzY2hMil+XDRO4osX0G+A8wtQh6FIHb+4kO9d4lSWHTa7As6H9qjmZWdxuPlBNgg+nHsQfF26Tx31g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019462; c=relaxed/simple; bh=TptvZ2qALp92JUus6oNn6a5GGBUiaDJx532BkTtSV24=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bFZsYO2O04rvMd+k9RLyTJ/83KkmE4sp4YIWzjoEedtxP2FXLYNVWZtun1gtRqDP3sWlVw11tEoGvh41pQjkjDtBEe0O5skxngP1TzZ60GbEMAB+nhjVoL/JwCI0tB+fyxu+O+Eta5ji8cwUQAXwQhHx1pzar1Q6ZvCzLCoigek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VuzdVLGk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VuzdVLGk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 105C0C4CEF7; Wed, 1 Apr 2026 04:57:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019462; bh=TptvZ2qALp92JUus6oNn6a5GGBUiaDJx532BkTtSV24=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VuzdVLGkAGEZIMO/g7rLy2AMpbrTIq1+b3mwKNP5bKT8T75N/eYJxUqF+D6jxEwri XztvparPyd0u7mowje+QQ+0pVOzByEXFftOU+YKiXUQR21F44rb1TjZNpn0WTaIK6S uxMMrkmTYT42j/KBAHmxRc6sV5VOz3Ne9rN4wUdR491dQ60Z6ViP7lDEDKAw99JFQh HjIuSuIKAsLdms31WTbofcCwsPvwFcNDl3m6R/UR+CAk1zO9Wc8qW3NX2GrUKyC8tI Zoi+ahCkOh7bLs0f2k6h4/Mo/Zy/uFt5PiEIidqRNXQSt85SrCJe/l171FGABPyD4Y hQpNlaJ/w2sgQ== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 2/5] x86/apic: Drop unused AMD EILVT macros Date: Wed, 1 Apr 2026 10:26:33 +0530 Message-ID: <8f2cb354f418dbd4bd6abce542a53bcee247688b.1775019269.git.naveen@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC_EILVT_NR_AMD_K8 and APIC_EILVT_LVTOFF are both unused. Drop them. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index f6d821656b02..bc125c4429dc 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -138,10 +138,8 @@ #define APIC_SEOI 0x420 #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) -#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ #define APIC_EILVT_NR_AMD_10H 4 #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H -#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 --=20 2.53.0 From nobody Sun Apr 5 18:16:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA91137FF5D for ; Wed, 1 Apr 2026 04:57:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019471; cv=none; b=oRIyNpWL+I8zv3XbnFlJGEK/UfajI5vd1wcCCvv8A6WakwYkNZQ2fGkkMKDWA5oePdj0xhSBsqkBKR2GaWPCDlGpwoRPx+ja99GDBDZZqPfv/edAUmvd4Hsbz1eruaxC2gfPuOzy04tX0ZFO9EbBftEyCE/Vd70IMaYpzXWDzH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019471; c=relaxed/simple; bh=YsqalQAe/OCRyIHlLpgRRfoU/NRoj+H/1pjvmU21LAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FQ3FQfle+Mdnm1/YGk4L0S5pabyVXMLEFeiP4YRM4uU9/RPJrSDnziPw0ezWxkFtNJuK9qDVRyZMuTJ40gz++yXtCNn9DUaERqQmEcP2RABjjuq5QHHkXbQrZwbN+uad8OegPosR3n/XZkjF6grLuKYaEU1uFE2TDkkxvQ2jRMk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TL0rP4AL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TL0rP4AL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE19CC4CEF7; Wed, 1 Apr 2026 04:57:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019471; bh=YsqalQAe/OCRyIHlLpgRRfoU/NRoj+H/1pjvmU21LAE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TL0rP4ALr0t+OfYFClnEht4ZjeaXZXNBzlJIwBgAU/PSpfFRO0CGI1RjrcFmLvVC6 Dm7mF5C3CSBY7Boq+qre0EE5C3+gyrhkQ+EUHc53kroSDZcsxep6e3X/Msyuhbqd9w jxmWUS3IAkcdL6IAPQ2mB74zwktl/7o88s6RbQLRMLZQ0J3VA4LVtGAp7JlVtpqPtk a0Hd+9gci0ZSpNiNHTcV9XHRnprgpXTdcFw/lOVoHzLxM042VwDGY8qbUqbh0lABrs fVQrhnfxM9RCuk0ndOKJfYm5bVsKq2Wzo6q5mxf1QxeupBcsJ6uamcXBtHcnLvUSUa 0s8KQhwSwbX9A== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 3/5] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Wed, 1 Apr 2026 10:26:34 +0530 Message-ID: <2086bdb889d265e5da5b48b61580fe4b7db340ee.1775019269.git.naveen@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e0bd5051db2a..61d14cbdda49 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1838,13 +1838,13 @@ static void force_ibs_eilvt_setup(void) =20 preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset =3D 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset =3D 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); =20 - if (offset =3D=3D APIC_EILVT_NR_MAX) { + if (offset =3D=3D APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } --=20 2.53.0 From nobody Sun Apr 5 18:16:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D869264A9D for ; Wed, 1 Apr 2026 04:57:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019476; cv=none; b=NIkD5SaAbWLWCN3eWZfuMjwpGemahQvUMZsKSbo5O3cWclcaReMOeHCmmgtjVTI5kntRiQolCCFJ5dPTIYSIlxH30uUf4P1h+TdjsJBEaLdB3FRzNts0ss1+CW58rcM43lK0JS3g4LYvPJtpoTckf8vbWvt/mzy2DrlPhaZgO/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019476; c=relaxed/simple; bh=z0tEmdEQL9m8O9ApEa/2VPWIexXaGwZs/d5SKbhL/jg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aeuaoyXkNMWi6XamF8iAm8Cbr7rPek24EVeTsTKjZ7WceHQX94lLnX71JryGckVBi/FeBFpQlQSvCy27VntMghHxxWbvzoeFMiotP3U/XpD8goZZOXvevzpnpItuagECgHN4OBa2+Q8nv2Ur/INIOs7KwBWgda0JbuYU5ieg2MM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NuMZcBJ+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NuMZcBJ+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B52EC116C6; Wed, 1 Apr 2026 04:57:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019476; bh=z0tEmdEQL9m8O9ApEa/2VPWIexXaGwZs/d5SKbhL/jg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NuMZcBJ+CkCp1Doa/fj2fUfYQYMtx5Y7ZUutMMXnFnz6yip/RdlHhZCml2wXmaOPK 87Ptovrva7T+/dY9oxLyyYXHUMTfwMdZq4bw+uSHDViT3lz9eS+wk74FGEcpGAPQmW rSI+xfR/RDGEZcQz8bkwM0n+KSoGspDHCiIwv2u8dNqu+SkP2+Cpgy/LQ8jiXA3FBb ZtXNWbbi0L6useKulw0ZjAdoWee94VpLbDHKYUDUNXjku4zZ/2siDf8Aqi61ekZrea 6tRn6nZwyV+t4s1PRRWbepzpyi+ZAyO8RdJITY164Q3Wdhzyj3kNwR2tAFOYrtRazd nMP/+TBt4VUYQ== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 4/5] x86/apic: Introduce a variable to track the number of EILVT registers Date: Wed, 1 Apr 2026 10:26:35 +0530 Message-ID: <6184174999bdd316b421aa2fd346276011b6900b.1775019269.git.naveen@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable to track the EILVT register count. The number of EILVT registers is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Export the new variable for KVM since it needs this for supporting extended APIC register space on AMD. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- http://lore.kernel.org/r/20260204074452.55453-3-manali.shukla@amd.com as=20 a related series adding support for KVM and needing access to the EILVT=20 register count. - Naveen arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 14 ++++++++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..8b03c7a14706 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -74,6 +74,8 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; =20 +extern unsigned int apic_eilvt_count; + /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 639904911444..748e09c5b322 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,6 +341,8 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) */ =20 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +unsigned int apic_eilvt_count __ro_after_init; +EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { @@ -409,6 +411,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type= , u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); =20 +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic_eilvt_count =3D APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic_eilvt_count) + apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -1644,6 +1655,9 @@ static void setup_local_APIC(void) if (!cpu) cmci_recheck(); #endif + + if (!apic_eilvt_count) + init_eilvt(); } =20 static void end_local_APIC_setup(void) --=20 2.53.0 From nobody Sun Apr 5 18:16:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66EE237FF66 for ; Wed, 1 Apr 2026 04:58:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019482; cv=none; b=fuR42H2Z+NBUBUttBPVD33OBTQ9EGcsRKajbQ5pBNy8Pj6PwLgp2nqJ9+tGriMNQgAqfV1T4GVS74jg/zeSmMQGSGOiVZad5nlwG6ZoEFlt4ihChhoIbzAHFz2cS95JCUKfu0zoHNgFjqqkIhA308tv+WRKhwJQw+nTApqJrdbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019482; c=relaxed/simple; bh=mhMkiLJ2AM2h6N0ira9zkE5d1/7knLpaBSGY4Xr35UQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I4TBD07s/MT3LSTmVk17JAsGNvcp1/pCZMTAmRbHEcWt9fNoBrkzVSBastJ/ezntKgLfg5Rg88HtOkIqrmdusqD7e2cDt4+TakNEuDLTPa5PKMhsLgvlTf1d6GnFe9jALCYXDnAKUo6AykkMtKzr+Ja13MO0DrK+4o6vLW0V1xo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D5QPvPFv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D5QPvPFv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FA5AC2BCB3; Wed, 1 Apr 2026 04:58:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019482; bh=mhMkiLJ2AM2h6N0ira9zkE5d1/7knLpaBSGY4Xr35UQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D5QPvPFvT8TRArCvjic2+k11ExiHEtnCSh4rRS+m22isQT7hqMf9UCEE2mJFJGo/8 Zxnv63Z4Fsgweuk+/uOYBlM+423U1vby1kqbpeA7AZKMjFnZSvEaNwuqmb63PNnlkk Wioteh3jXkjHW6nqkbTIgouAcg8gFhKZU5bSO/DLiqjtFRhIzQgNOd/lXcsrM8Bbat g8EkRASvnBZ2m2FFssIeV0gUSprtqdnWokFI/xLZzOesfZoRGldRdrVps04phLmylf W8sutFsqYS/zYJz0DDpUj4YoLZfnYfY1k9pINfu63UmZZkkVvjvM5VMM4FLJ+rYf3C pZ/uKM93pN60g== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 5/5] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Date: Wed, 1 Apr 2026 10:26:36 +0530 Message-ID: <2fd862367e1552615c823a6cda274b05bc04cc38.1775019269.git.naveen@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to using apic_eilvt_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. But do so during init instead of in reserve_eilvt_offset() since the latter is called with preemption disabled. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 748e09c5b322..c4dfd7e93fe4 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -340,7 +340,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * necessarily a BIOS bug. */ =20 -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; unsigned int apic_eilvt_count __ro_after_init; EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); =20 @@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, un= signed int new) { unsigned int rsvd, vector; =20 - if (offset >=3D APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >=3D apic_eilvt_count) return ~0; =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); @@ -418,6 +418,9 @@ static __init void init_eilvt(void) =20 if (!apic_eilvt_count) apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; + + if (!eilvt_offsets) + eilvt_offsets =3D kzalloc_objs(atomic_t, apic_eilvt_count); } =20 /* --=20 2.53.0