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charset="utf-8" The Data Ready/FIFO interrupt has a special behavior that inverts the IRQ polarity when devices with FIFO support enter FIFO mode, while using normal polarity for data ready. Document the interrupts property to clarify this special behavior for users. Acked-by: Krzysztof Kozlowski Signed-off-by: Jonathan Santos --- Changes in v3: * None. Changes in v2: * New patch. --- Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4130.yaml index d00690a8d3fb..fcc00e5cfd54 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml @@ -32,6 +32,10 @@ properties: =20 interrupts: maxItems: 1 + description: | + Data Ready / FIFO interrupt. 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charset="utf-8" Extend driver support for AD4129-4/8, AD4130-4, and AD4131-4/8 ADC variants. Acked-by: Krzysztof Kozlowski Signed-off-by: Jonathan Santos --- Changes in v3: * None. Changes in v2: * None. --- .../devicetree/bindings/iio/adc/adi,ad4130.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4130.yaml index fcc00e5cfd54..f4cad68fa04d 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml @@ -5,19 +5,30 @@ $id: http://devicetree.org/schemas/iio/adc/adi,ad4130.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Analog Devices AD4130 ADC device driver +title: Analog Devices AD4130 family ADC device driver =20 maintainers: - Cosmin Tanislav =20 description: | - Bindings for the Analog Devices AD4130 ADC. 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Wed, 1 Apr 2026 07:58:25 -0400 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , , Andy Shevchenko Subject: [PATCH v3 3/5] iio: adc: ad4130: Add SPI device ID table Date: Wed, 1 Apr 2026 08:58:22 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=VqQuwu2n c=1 sm=1 tr=0 ts=69cd086f cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=QyXUC8HyAAAA:8 a=gAnH3GRIAAAA:8 a=ijA5dNRdcb88KqkhJh4A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDExMCBTYWx0ZWRfX7XYy3q+W4hJJ tNqmOcoM5w9NXJ+LvInWVtLzM+xphkzmXFKeUo6pqMsfbeTU4YXF8zB4ZJ299KHokvco5H9ppbU YBNaPj5jgEeYlCza0gd7E48307XL4vQyyOPnwUgrP5OHYpJy5F+JzrBDfCC8o1LuMG0LVecXBf5 X3UT06oPZo09Jvyb/2cJ+wDXH1JToT55JykRLvdSX4uqtUOEqjQDzvUKtRAX9d9mdGjve1QA1lb D7xa6jg30uAk3X4CYPRBrvNBHmK4yKVFhwb8iX3SU38x51DrmCLJ7vB6loqPc6Tv3r0P0cVD1cZ kxVFFLaZxTcFPZvJV+n/5EETQ2l0Q+2Orpv7g7hdnU4n0/GbBSAgqySOCC4JUMcG6t4BTA3l8QV GuXwBvg6WqySf8Qf5cR1xLCmS+2iKO6T69HWRiwJunoxsC9B7sdTJ94VnGfgHptieqZCnwSL9H/ lnBS2xffZJDCdDx68Qw== X-Proofpoint-GUID: JflbSGemF37IRuJD4jSAO_9w-0-mXrwf X-Proofpoint-ORIG-GUID: JflbSGemF37IRuJD4jSAO_9w-0-mXrwf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_03,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010110 Content-Type: text/plain; charset="utf-8" Add SPI device ID table to enable non-device tree based device binding. The id_table provides a fallback matching mechanism when of_match_table cannot be used, which is required for proper SPI driver registration. Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Santos --- Changes in v3: * Removed ', 0' in the ad4130_id_table. Changes in v2: * New patch. --- drivers/iio/adc/ad4130.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iio/adc/ad4130.c b/drivers/iio/adc/ad4130.c index 5567ae5dee88..d7aaf57ab87a 100644 --- a/drivers/iio/adc/ad4130.c +++ b/drivers/iio/adc/ad4130.c @@ -2109,12 +2109,19 @@ static const struct of_device_id ad4130_of_match[] = =3D { }; MODULE_DEVICE_TABLE(of, ad4130_of_match); =20 +static const struct spi_device_id ad4130_id_table[] =3D { + { "ad4130" }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad4130_id_table); + static struct spi_driver ad4130_driver =3D { .driver =3D { .name =3D AD4130_NAME, .of_match_table =3D ad4130_of_match, }, .probe =3D ad4130_probe, + .id_table =3D ad4130_id_table, }; module_spi_driver(ad4130_driver); =20 --=20 2.34.1 From nobody Wed Apr 1 20:42:56 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4624301493; 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Wed, 1 Apr 2026 07:58:39 -0400 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , , Andy Shevchenko Subject: [PATCH v3 4/5] iio: adc: ad4130: introduce chip info for future multidevice support Date: Wed, 1 Apr 2026 08:58:34 -0300 Message-ID: <24c34bf6bfe61a0cb1dfc1438a87329356dbeaba.1774996100.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDExMCBTYWx0ZWRfX/67mBFFobdti du3Lji7uG9eQVMoyoV5Vro1UWSrsUR4jqqbiOtwFxHxyPaJR5aKsINjryQvBILzpD1Dt4/RZsPS TzwaM84DfoUhNcqYVBeRnKOONIwVhqIUMoFQD7dtBToG5tDM8RePH4cuzzWbU9nGXgRfVzhAjmx PVO4vyHAz88vBBh9/rQM3Ukh2puWyZYobihZV+xrCEeg60L315cfFjN8mguDJUhOsoAEZGInCoM 6zBIZ8j/sMz7Wm/Wi4prs4BkrXJTqGzqJ33FlC8RtynWEzYaalgJpqnkyct3iLaVhpbvE0YqQ3D Go5mc6Lc3YSYUhNXvyXrtMTLghmKE43kHLfoIuQczyjV0iMl+2oLBMOCY+rQq0mVmdS699/op0N tT3BGYCG3/aWhmfC6R22S/S26ROgU2NPrgkGm6FCokTepqcsLdFsvxcfBA2YcPf2x3/TGF736Xm nNhIymAB9FhApadDHbA== X-Proofpoint-ORIG-GUID: UYUGKOE-jKLEGWpfSby25qjLgoe9zqZA X-Authority-Analysis: v=2.4 cv=cqiWUl4i c=1 sm=1 tr=0 ts=69cd087b cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=QyXUC8HyAAAA:8 a=gAnH3GRIAAAA:8 a=iK7pNCdl7K3njzu4ZfAA:9 X-Proofpoint-GUID: UYUGKOE-jKLEGWpfSby25qjLgoe9zqZA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_03,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010110 Content-Type: text/plain; charset="utf-8" Introduce a chip_info structure to abstract device-specific parameters and prepare the driver for supporting multiple AD4130 family variants. Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Santos --- Changes in v3: * None. Changes in v2: * spi_device_id table moved into a precursor patch. * OF device id table using the original indentation. --- drivers/iio/adc/ad4130.c | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad4130.c b/drivers/iio/adc/ad4130.c index d7aaf57ab87a..b064744e8da8 100644 --- a/drivers/iio/adc/ad4130.c +++ b/drivers/iio/adc/ad4130.c @@ -224,6 +224,14 @@ enum ad4130_pin_function { AD4130_PIN_FN_VBIAS =3D BIT(3), }; =20 +struct ad4130_chip_info { + const char *name; + unsigned int max_analog_pins; + const struct iio_info *info; + const unsigned int *reg_size; + const unsigned int reg_size_length; +}; + /* * If you make adaptations in this struct, you most likely also have to ad= apt * ad4130_setup_info_eq(), too. @@ -268,6 +276,7 @@ struct ad4130_state { struct regmap *regmap; struct spi_device *spi; struct clk *mclk; + const struct ad4130_chip_info *chip_info; struct regulator_bulk_data regulators[4]; u32 irq_trigger; u32 inv_irq_trigger; @@ -394,10 +403,10 @@ static const char * const ad4130_filter_types_str[] = =3D { static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, unsigned int *size) { - if (reg >=3D ARRAY_SIZE(ad4130_reg_size)) + if (reg >=3D st->chip_info->reg_size_length) return -EINVAL; =20 - *size =3D ad4130_reg_size[reg]; + *size =3D st->chip_info->reg_size[reg]; =20 return 0; } @@ -1291,6 +1300,14 @@ static const struct iio_info ad4130_info =3D { .debugfs_reg_access =3D ad4130_reg_access, }; =20 +static const struct ad4130_chip_info ad4130_8_chip_info =3D { + .name =3D "ad4130-8", + .max_analog_pins =3D 16, + .info =3D &ad4130_info, + .reg_size =3D ad4130_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4130_reg_size), +}; + static int ad4130_buffer_postenable(struct iio_dev *indio_dev) { struct ad4130_state *st =3D iio_priv(indio_dev); @@ -1504,7 +1521,7 @@ static int ad4130_validate_diff_channel(struct ad4130= _state *st, u32 pin) return dev_err_probe(dev, -EINVAL, "Invalid differential channel %u\n", pin); =20 - if (pin >=3D AD4130_MAX_ANALOG_PINS) + if (pin >=3D st->chip_info->max_analog_pins) return 0; =20 if (st->pins_fn[pin] =3D=3D AD4130_PIN_FN_SPECIAL) @@ -1536,7 +1553,7 @@ static int ad4130_validate_excitation_pin(struct ad41= 30_state *st, u32 pin) { struct device *dev =3D &st->spi->dev; =20 - if (pin >=3D AD4130_MAX_ANALOG_PINS) + if (pin >=3D st->chip_info->max_analog_pins) return dev_err_probe(dev, -EINVAL, "Invalid excitation pin %u\n", pin); =20 @@ -1554,7 +1571,7 @@ static int ad4130_validate_vbias_pin(struct ad4130_st= ate *st, u32 pin) { struct device *dev =3D &st->spi->dev; =20 - if (pin >=3D AD4130_MAX_ANALOG_PINS) + if (pin >=3D st->chip_info->max_analog_pins) return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n", pin); =20 @@ -1730,7 +1747,7 @@ static int ad4310_parse_fw(struct iio_dev *indio_dev) =20 ret =3D device_property_count_u32(dev, "adi,vbias-pins"); if (ret > 0) { - if (ret > AD4130_MAX_ANALOG_PINS) + if (ret > st->chip_info->max_analog_pins) return dev_err_probe(dev, -EINVAL, "Too many vbias pins %u\n", ret); =20 @@ -1994,6 +2011,8 @@ static int ad4130_probe(struct spi_device *spi) =20 st =3D iio_priv(indio_dev); =20 + st->chip_info =3D device_get_match_data(dev); + memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); init_completion(&st->completion); mutex_init(&st->lock); @@ -2011,9 +2030,9 @@ static int ad4130_probe(struct spi_device *spi) spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, ARRAY_SIZE(st->fifo_xfer)); =20 - indio_dev->name =3D AD4130_NAME; + indio_dev->name =3D st->chip_info->name; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->info =3D &ad4130_info; + indio_dev->info =3D st->chip_info->info; =20 st->regmap =3D devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); if (IS_ERR(st->regmap)) @@ -2056,7 +2075,7 @@ static int ad4130_probe(struct spi_device *spi) ad4130_fill_scale_tbls(st); =20 st->gc.owner =3D THIS_MODULE; - st->gc.label =3D AD4130_NAME; + st->gc.label =3D st->chip_info->name; st->gc.base =3D -1; st->gc.ngpio =3D AD4130_MAX_GPIOS; st->gc.parent =3D dev; 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charset="utf-8" Add support for AD4129-4/8, AD4130-4, and AD4131-4/8 variants. The AD4129 series supports the same FIFO interface as the AD4130 but with reduced resolution (16-bit). The AD4131 series lacks FIFO support, so triggered buffer functionality is introduced. The 4-channel variants feature fewer analog inputs, GPIOs, and sparse pin mappings for VBIAS, analog inputs, and excitation currents. The driver now handles these differences with chip-specific configurations, including pin mappings and GPIO counts. Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Santos --- Changes in v3: * Since we have either FIFO or triggered buffer configured, create a union struct with the FIFO buffers and the triggered buffer scan channel declaration to save memory. Since they already are in a DMA safe and aligned space, use IIO_DECLARE_BUFFER_WITH_TS() instead of IIO_DECLARE_DMA_BUFFER_WITH_TS() * restructured ad4130_4_pin_map constant definition to be more consistent with other pin map definitions. * Some lines in the ad4130_trigger_handler() were ending in comma instead of a semicolon. Replaced the commas with semicolons for those cases. * Inverted logic for wait_for_completion_timeout() check in ad4130_trigger_handler(). It was warning on success. Changes in v2: * ad4130_8_pin_map comment description modified to be clearer. * Refactored variable assignments on ad4130_trigger_handler(). * Refactored ad4130_buffer_predisable() function. * Replaced scan data struct (for triggered buffer mode) with=20 IIO_DECLARE_DMA_BUFFER_WITH_TS(), as suggested by David. * Renamed err_unlock label to err_out. --- drivers/iio/adc/ad4130.c | 446 ++++++++++++++++++++++++++++++++------- 1 file changed, 373 insertions(+), 73 deletions(-) diff --git a/drivers/iio/adc/ad4130.c b/drivers/iio/adc/ad4130.c index b064744e8da8..7f39f3484062 100644 --- a/drivers/iio/adc/ad4130.c +++ b/drivers/iio/adc/ad4130.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,7 @@ #include #include #include +#include #include =20 #include @@ -30,6 +32,9 @@ #include #include #include +#include +#include +#include =20 #define AD4130_NAME "ad4130" =20 @@ -40,6 +45,7 @@ #define AD4130_ADC_CONTROL_REG 0x01 #define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14) #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13) +#define AD4130_ADC_CONTROL_CONT_READ_MASK BIT(11) #define AD4130_INT_REF_2_5V 2500000 #define AD4130_INT_REF_1_25V 1250000 #define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9) @@ -54,7 +60,9 @@ #define AD4130_IO_CONTROL_REG 0x03 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8) #define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4) +#define AD4130_4_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 6) #define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0) +#define AD4130_4_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 2) =20 #define AD4130_VBIAS_REG 0x04 =20 @@ -125,6 +133,28 @@ =20 #define AD4130_INVALID_SLOT -1 =20 +static const unsigned int ad4129_reg_size[] =3D { + [AD4130_STATUS_REG] =3D 1, + [AD4130_ADC_CONTROL_REG] =3D 2, + [AD4130_DATA_REG] =3D 2, + [AD4130_IO_CONTROL_REG] =3D 2, + [AD4130_VBIAS_REG] =3D 2, + [AD4130_ID_REG] =3D 1, + [AD4130_ERROR_REG] =3D 2, + [AD4130_ERROR_EN_REG] =3D 2, + [AD4130_MCLK_COUNT_REG] =3D 1, + [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1= )] =3D 3, + [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 3, + [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] =3D 2, + [AD4130_MISC_REG] =3D 2, + [AD4130_FIFO_CONTROL_REG] =3D 3, + [AD4130_FIFO_STATUS_REG] =3D 1, + [AD4130_FIFO_THRESHOLD_REG] =3D 3, + [AD4130_FIFO_DATA_REG] =3D 2, +}; + static const unsigned int ad4130_reg_size[] =3D { [AD4130_STATUS_REG] =3D 1, [AD4130_ADC_CONTROL_REG] =3D 2, @@ -147,6 +177,24 @@ static const unsigned int ad4130_reg_size[] =3D { [AD4130_FIFO_DATA_REG] =3D 3, }; =20 +static const unsigned int ad4131_reg_size[] =3D { + [AD4130_STATUS_REG] =3D 1, + [AD4130_ADC_CONTROL_REG] =3D 2, + [AD4130_DATA_REG] =3D 2, + [AD4130_IO_CONTROL_REG] =3D 2, + [AD4130_VBIAS_REG] =3D 2, + [AD4130_ID_REG] =3D 1, + [AD4130_ERROR_REG] =3D 2, + [AD4130_ERROR_EN_REG] =3D 2, + [AD4130_MCLK_COUNT_REG] =3D 1, + [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1= )] =3D 3, + [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 3, + [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] =3D 2, + [AD4130_MISC_REG] =3D 2, +}; + enum ad4130_int_ref_val { AD4130_INT_REF_VAL_2_5V, AD4130_INT_REF_VAL_1_25V, @@ -224,12 +272,26 @@ enum ad4130_pin_function { AD4130_PIN_FN_VBIAS =3D BIT(3), }; =20 +/* Pin mapping for AIN0..AIN7, VBIAS_0..VBIAS_7 */ +static const u8 ad4130_4_pin_map[] =3D { + 0x00, 0x01, 0x04, 0x05, 0x0A, 0x0B, 0x0E, 0x0F, /* 0 - 7 */ +}; + +/* Pin mapping for AIN0..AIN15, VBIAS_0..VBIAS_15 */ +static const u8 ad4130_8_pin_map[] =3D { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 0 - 7 */ + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, /* 8 - 15 */ +}; + struct ad4130_chip_info { const char *name; unsigned int max_analog_pins; + unsigned int num_gpios; const struct iio_info *info; const unsigned int *reg_size; const unsigned int reg_size_length; + const u8 *pin_map; + bool has_fifo; }; =20 /* @@ -303,6 +365,7 @@ struct ad4130_state { u32 mclk_sel; bool int_ref_en; bool bipolar; + bool buffer_wait_for_irq; =20 unsigned int num_enabled_channels; unsigned int effective_watermark; @@ -310,6 +373,7 @@ struct ad4130_state { =20 struct spi_message fifo_msg; struct spi_transfer fifo_xfer[2]; + struct iio_trigger *trig; =20 /* * DMA (thus cache coherency maintenance) requires any transfer @@ -321,9 +385,13 @@ struct ad4130_state { u8 reg_write_tx_buf[4]; u8 reg_read_tx_buf[1]; u8 reg_read_rx_buf[3]; - u8 fifo_tx_buf[2]; - u8 fifo_rx_buf[AD4130_FIFO_SIZE * - AD4130_FIFO_MAX_SAMPLE_SIZE]; + union { + struct { + u8 fifo_tx_buf[2]; + u8 fifo_rx_buf[AD4130_FIFO_SIZE * AD4130_FIFO_MAX_SAMPLE_SIZE]; + }; + IIO_DECLARE_BUFFER_WITH_TS(u32, scan_channels, AD4130_MAX_CHANNELS); + }; }; =20 static const char * const ad4130_int_pin_names[] =3D { @@ -514,7 +582,8 @@ static int ad4130_gpio_init_valid_mask(struct gpio_chip= *gc, =20 /* * Output-only GPIO functionality is available on pins AIN2 through - * AIN5. If these pins are used for anything else, do not expose them. + * AIN5 for some parts and AIN2 through AIN3 for others. If these pins + * are used for anything else, do not expose them. */ for (i =3D 0; i < ngpios; i++) { unsigned int pin =3D i + AD4130_AIN2_P1; @@ -535,8 +604,14 @@ static int ad4130_gpio_set(struct gpio_chip *gc, unsig= ned int offset, int value) { struct ad4130_state *st =3D gpiochip_get_data(gc); - unsigned int mask =3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK, - BIT(offset)); + unsigned int mask; + + if (st->chip_info->num_gpios =3D=3D AD4130_MAX_GPIOS) + mask =3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK, + BIT(offset)); + else + mask =3D FIELD_PREP(AD4130_4_IO_CONTROL_GPIO_DATA_MASK, + BIT(offset)); =20 return regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, value ? mask : 0); @@ -597,10 +672,43 @@ static irqreturn_t ad4130_irq_handler(int irq, void *= private) struct iio_dev *indio_dev =3D private; struct ad4130_state *st =3D iio_priv(indio_dev); =20 - if (iio_buffer_enabled(indio_dev)) - ad4130_push_fifo_data(indio_dev); - else + if (iio_buffer_enabled(indio_dev)) { + if (st->chip_info->has_fifo) + ad4130_push_fifo_data(indio_dev); + else if (st->buffer_wait_for_irq) + complete(&st->completion); + else + iio_trigger_poll(st->trig); + } else { complete(&st->completion); + } + + return IRQ_HANDLED; +} + +static irqreturn_t ad4130_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4130_state *st =3D iio_priv(indio_dev); + unsigned int data_reg_size =3D ad4130_data_reg_size(st); + struct spi_transfer xfer =3D { }; + unsigned int num_en_chn; + int ret; + + num_en_chn =3D bitmap_weight(indio_dev->active_scan_mask, + iio_get_masklength(indio_dev)); + xfer.rx_buf =3D st->scan_channels; + xfer.len =3D data_reg_size * num_en_chn; + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret < 0) + goto err_out; + + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_channels, + iio_get_time_ns(indio_dev)); + +err_out: + iio_trigger_notify_done(indio_dev->trig); =20 return IRQ_HANDLED; } @@ -1300,12 +1408,77 @@ static const struct iio_info ad4130_info =3D { .debugfs_reg_access =3D ad4130_reg_access, }; =20 +static const struct iio_info ad4131_info =3D { + .read_raw =3D ad4130_read_raw, + .read_avail =3D ad4130_read_avail, + .write_raw_get_fmt =3D ad4130_write_raw_get_fmt, + .write_raw =3D ad4130_write_raw, + .update_scan_mode =3D ad4130_update_scan_mode, + .debugfs_reg_access =3D ad4130_reg_access, +}; + +static const struct ad4130_chip_info ad4129_4_chip_info =3D { + .name =3D "ad4129-4", + .max_analog_pins =3D 8, + .num_gpios =3D 2, + .info =3D &ad4130_info, + .reg_size =3D ad4129_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4129_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_4_pin_map, +}; + +static const struct ad4130_chip_info ad4129_8_chip_info =3D { + .name =3D "ad4129-8", + .max_analog_pins =3D 16, + .num_gpios =3D 4, + .info =3D &ad4130_info, + .reg_size =3D ad4129_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4129_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_8_pin_map, +}; + +static const struct ad4130_chip_info ad4130_4_chip_info =3D { + .name =3D "ad4130-4", + .max_analog_pins =3D 16, + .num_gpios =3D 2, + .info =3D &ad4130_info, + .reg_size =3D ad4130_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4130_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_4_pin_map, +}; + static const struct ad4130_chip_info ad4130_8_chip_info =3D { .name =3D "ad4130-8", .max_analog_pins =3D 16, + .num_gpios =3D 4, .info =3D &ad4130_info, .reg_size =3D ad4130_reg_size, .reg_size_length =3D ARRAY_SIZE(ad4130_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_8_pin_map, +}; + +static const struct ad4130_chip_info ad4131_4_chip_info =3D { + .name =3D "ad4131-4", + .max_analog_pins =3D 8, + .num_gpios =3D 2, + .info =3D &ad4131_info, + .reg_size =3D ad4131_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4131_reg_size), + .pin_map =3D ad4130_4_pin_map, +}; + +static const struct ad4130_chip_info ad4131_8_chip_info =3D { + .name =3D "ad4131-8", + .max_analog_pins =3D 16, + .num_gpios =3D 4, + .info =3D &ad4131_info, + .reg_size =3D ad4131_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4131_reg_size), + .pin_map =3D ad4130_8_pin_map, }; =20 static int ad4130_buffer_postenable(struct iio_dev *indio_dev) @@ -1315,44 +1488,89 @@ static int ad4130_buffer_postenable(struct iio_dev = *indio_dev) =20 guard(mutex)(&st->lock); =20 - ret =3D ad4130_set_watermark_interrupt_en(st, true); - if (ret) - return ret; + if (st->chip_info->has_fifo) { + ret =3D ad4130_set_watermark_interrupt_en(st, true); + if (ret) + return ret; =20 - ret =3D irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); - if (ret) - return ret; + ret =3D irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); + if (ret) + return ret; + + ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); + if (ret) + return ret; + } =20 - ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); + ret =3D ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); if (ret) return ret; =20 - return ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); + /* + * When using triggered buffer, Entering continuous read mode must + * be the last command sent. No configuration changes are allowed until + * exiting this mode. + */ + if (!st->chip_info->has_fifo) { + ret =3D regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, + AD4130_ADC_CONTROL_CONT_READ_MASK, + FIELD_PREP(AD4130_ADC_CONTROL_CONT_READ_MASK, 1)); + if (ret) + return ret; + } + + return 0; } =20 static int ad4130_buffer_predisable(struct iio_dev *indio_dev) { struct ad4130_state *st =3D iio_priv(indio_dev); unsigned int i; + u32 temp; int ret; =20 guard(mutex)(&st->lock); =20 + if (!st->chip_info->has_fifo) { + temp =3D 0x42; + reinit_completion(&st->completion); + + /* + * In continuous read mode, when all samples are read, the data + * ready signal returns high until the next conversion result is + * ready. To exit this mode, the command must be sent when data + * ready is low. In order to ensure that condition, wait for the + * next interrupt (when the new conversion is finished), allowing + * data ready to return low before sending the exit command. + */ + st->buffer_wait_for_irq =3D true; + if (!wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000)= )) + dev_warn(&st->spi->dev, "Conversion timed out\n"); + st->buffer_wait_for_irq =3D false; + + /* Perform a read data command to exit continuous read mode (0x42) */ + ret =3D spi_write(st->spi, &temp, 1); + if (ret) + return ret; + } + ret =3D ad4130_set_mode(st, AD4130_MODE_IDLE); if (ret) return ret; =20 - ret =3D irq_set_irq_type(st->spi->irq, st->irq_trigger); - if (ret) - return ret; + if (st->chip_info->has_fifo) { + ret =3D irq_set_irq_type(st->spi->irq, st->irq_trigger); + if (ret) + return ret; =20 - ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); - if (ret) - return ret; + ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); + if (ret) + return ret; =20 - ret =3D ad4130_set_watermark_interrupt_en(st, false); - if (ret) - return ret; + ret =3D ad4130_set_watermark_interrupt_en(st, false); + if (ret) + return ret; + } =20 /* * update_scan_mode() is not called in the disable path, disable all @@ -1427,6 +1645,34 @@ static const struct iio_dev_attr *ad4130_fifo_attrib= utes[] =3D { NULL }; =20 +static const struct iio_trigger_ops ad4130_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + +static int ad4130_triggered_buffer_setup(struct iio_dev *indio_dev) +{ + struct ad4130_state *st =3D iio_priv(indio_dev); + int ret; + + st->trig =3D devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", + indio_dev->name, iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + + st->trig->ops =3D &ad4130_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret =3D devm_iio_trigger_register(indio_dev->dev.parent, st->trig); + if (ret) + return ret; + + indio_dev->trig =3D iio_trigger_get(st->trig); + + return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, + &iio_pollfunc_store_time, + &ad4130_trigger_handler, + &ad4130_buffer_ops); +} + static int _ad4130_find_table_index(const unsigned int *tbl, size_t len, unsigned int val) { @@ -1513,6 +1759,17 @@ static int ad4130_parse_fw_setup(struct ad4130_state= *st, return 0; } =20 +static unsigned int ad4130_translate_pin(struct ad4130_state *st, + unsigned int logical_pin) +{ + /* For analog input pins, use the chip-specific pin mapping */ + if (logical_pin < st->chip_info->max_analog_pins) + return st->chip_info->pin_map[logical_pin]; + + /* For internal channels, pass through unchanged */ + return logical_pin; +} + static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) { struct device *dev =3D &st->spi->dev; @@ -1931,9 +2188,14 @@ static int ad4130_setup(struct iio_dev *indio_dev) * function of P2 takes priority over the GPIO out function. */ val =3D 0; - for (i =3D 0; i < AD4130_MAX_GPIOS; i++) - if (st->pins_fn[i + AD4130_AIN2_P1] =3D=3D AD4130_PIN_FN_NONE) - val |=3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); + for (i =3D 0; i < st->chip_info->num_gpios; i++) { + if (st->pins_fn[i + AD4130_AIN2_P1] =3D=3D AD4130_PIN_FN_NONE) { + if (st->chip_info->num_gpios =3D=3D 2) + val |=3D FIELD_PREP(AD4130_4_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); + else + val |=3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); + } + } =20 val |=3D FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); =20 @@ -1943,21 +2205,23 @@ static int ad4130_setup(struct iio_dev *indio_dev) =20 val =3D 0; for (i =3D 0; i < st->num_vbias_pins; i++) - val |=3D BIT(st->vbias_pins[i]); + val |=3D BIT(ad4130_translate_pin(st, st->vbias_pins[i])); =20 ret =3D regmap_write(st->regmap, AD4130_VBIAS_REG, val); if (ret) return ret; =20 - ret =3D regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, - AD4130_FIFO_CONTROL_HEADER_MASK); - if (ret) - return ret; + if (st->chip_info->has_fifo) { + ret =3D regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, + AD4130_FIFO_CONTROL_HEADER_MASK); + if (ret) + return ret; =20 - /* FIFO watermark interrupt starts out as enabled, disable it. */ - ret =3D ad4130_set_watermark_interrupt_en(st, false); - if (ret) - return ret; + /* FIFO watermark interrupt starts out as enabled, disable it. */ + ret =3D ad4130_set_watermark_interrupt_en(st, false); + if (ret) + return ret; + } =20 /* Setup channels. */ for (i =3D 0; i < indio_dev->num_channels; i++) { @@ -1965,10 +2229,14 @@ static int ad4130_setup(struct iio_dev *indio_dev) struct iio_chan_spec *chan =3D &st->chans[i]; unsigned int val; =20 - val =3D FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) | - FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) | - FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) | - FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1); + val =3D FIELD_PREP(AD4130_CHANNEL_AINP_MASK, + ad4130_translate_pin(st, chan->channel)) | + FIELD_PREP(AD4130_CHANNEL_AINM_MASK, + ad4130_translate_pin(st, chan->channel2)) | + FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, + ad4130_translate_pin(st, chan_info->iout0)) | + FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, + ad4130_translate_pin(st, chan_info->iout1)); =20 ret =3D regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); if (ret) @@ -2018,17 +2286,19 @@ static int ad4130_probe(struct spi_device *spi) mutex_init(&st->lock); st->spi =3D spi; =20 - /* - * Xfer: [ XFR1 ] [ XFR2 ] - * Master: 0x7D N ...................... - * Slave: ...... DATA1 DATA2 ... DATAN - */ - st->fifo_tx_buf[0] =3D AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; - st->fifo_xfer[0].tx_buf =3D st->fifo_tx_buf; - st->fifo_xfer[0].len =3D sizeof(st->fifo_tx_buf); - st->fifo_xfer[1].rx_buf =3D st->fifo_rx_buf; - spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, - ARRAY_SIZE(st->fifo_xfer)); + if (st->chip_info->has_fifo) { + /* + * Xfer: [ XFR1 ] [ XFR2 ] + * Master: 0x7D N ...................... + * Slave: ...... DATA1 DATA2 ... DATAN + */ + st->fifo_tx_buf[0] =3D AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; + st->fifo_xfer[0].tx_buf =3D st->fifo_tx_buf; + st->fifo_xfer[0].len =3D sizeof(st->fifo_tx_buf); + st->fifo_xfer[1].rx_buf =3D st->fifo_rx_buf; + spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, + ARRAY_SIZE(st->fifo_xfer)); + } =20 indio_dev->name =3D st->chip_info->name; indio_dev->modes =3D INDIO_DIRECT_MODE; @@ -2077,7 +2347,7 @@ static int ad4130_probe(struct spi_device *spi) st->gc.owner =3D THIS_MODULE; st->gc.label =3D st->chip_info->name; st->gc.base =3D -1; - st->gc.ngpio =3D AD4130_MAX_GPIOS; + st->gc.ngpio =3D st->chip_info->num_gpios; st->gc.parent =3D dev; st->gc.can_sleep =3D true; st->gc.init_valid_mask =3D ad4130_gpio_init_valid_mask; @@ -2088,9 +2358,12 @@ static int ad4130_probe(struct spi_device *spi) if (ret) return ret; =20 - ret =3D devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, - &ad4130_buffer_ops, - ad4130_fifo_attributes); + if (st->chip_info->has_fifo) + ret =3D devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, + &ad4130_buffer_ops, + ad4130_fifo_attributes); + else + ret =3D ad4130_triggered_buffer_setup(indio_dev); if (ret) return ret; =20 @@ -2100,37 +2373,64 @@ static int ad4130_probe(struct spi_device *spi) if (ret) return dev_err_probe(dev, ret, "Failed to request irq\n"); =20 - /* - * When the chip enters FIFO mode, IRQ polarity is inverted. - * When the chip exits FIFO mode, IRQ polarity returns to normal. - * See datasheet pages: 65, FIFO Watermark Interrupt section, - * and 71, Bit Descriptions for STATUS Register, RDYB. - * Cache the normal and inverted IRQ triggers to set them when - * entering and exiting FIFO mode. - */ - st->irq_trigger =3D irq_get_trigger_type(spi->irq); - if (st->irq_trigger & IRQF_TRIGGER_RISING) - st->inv_irq_trigger =3D IRQF_TRIGGER_FALLING; - else if (st->irq_trigger & IRQF_TRIGGER_FALLING) - st->inv_irq_trigger =3D IRQF_TRIGGER_RISING; - else - return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", - st->irq_trigger); + if (st->chip_info->has_fifo) { + /* + * When the chip enters FIFO mode, IRQ polarity is inverted. + * When the chip exits FIFO mode, IRQ polarity returns to normal. + * See datasheet pages: 65, FIFO Watermark Interrupt section, + * and 71, Bit Descriptions for STATUS Register, RDYB. + * Cache the normal and inverted IRQ triggers to set them when + * entering and exiting FIFO mode. + */ + st->irq_trigger =3D irq_get_trigger_type(spi->irq); + if (st->irq_trigger & IRQF_TRIGGER_RISING) + st->inv_irq_trigger =3D IRQF_TRIGGER_FALLING; + else if (st->irq_trigger & IRQF_TRIGGER_FALLING) + st->inv_irq_trigger =3D IRQF_TRIGGER_RISING; + else + return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", + st->irq_trigger); + } =20 return devm_iio_device_register(dev, indio_dev); } =20 static const struct of_device_id ad4130_of_match[] =3D { + { + .compatible =3D "adi,ad4129-4", + .data =3D &ad4129_4_chip_info + }, + { + .compatible =3D "adi,ad4129-8", + .data =3D &ad4129_8_chip_info + }, + { + .compatible =3D "adi,ad4130-4", + .data =3D &ad4130_4_chip_info + }, { .compatible =3D "adi,ad4130", .data =3D &ad4130_8_chip_info }, + { + .compatible =3D "adi,ad4131-4", + .data =3D &ad4131_4_chip_info + }, + { + .compatible =3D "adi,ad4131-8", + .data =3D &ad4131_8_chip_info + }, { } }; MODULE_DEVICE_TABLE(of, ad4130_of_match); =20 static const struct spi_device_id ad4130_id_table[] =3D { + { "ad4129-4", (kernel_ulong_t)&ad4129_4_chip_info }, + { "ad4129-8", (kernel_ulong_t)&ad4129_8_chip_info }, + { "ad4130-4", (kernel_ulong_t)&ad4130_4_chip_info }, { "ad4130", (kernel_ulong_t)&ad4130_8_chip_info }, + { "ad4131-4", (kernel_ulong_t)&ad4131_4_chip_info }, + { "ad4131-8", (kernel_ulong_t)&ad4131_8_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4130_id_table); --=20 2.34.1