From nobody Thu Apr 2 16:58:52 2026 Received: from out198-43.us.a.mail.aliyun.com (out198-43.us.a.mail.aliyun.com [47.90.198.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130743D3487 for ; Fri, 27 Mar 2026 08:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774598900; cv=none; b=Nt+aYFmIkY0UQPp97VcTHWKgIBZ0bCPz93GsuUN7+LMlA0nf45u6rq4HMOa2HncBO3QifSfAyMne1X9ZK/Ig55NEnQ2gR0JMM3l7bbcVd6ndbMpzjoZBJEBma68y6shC6zvZwx2YXkH2rDU9vZ8MxqZNJnR/FDVgbc3H3R2TcuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774598900; c=relaxed/simple; bh=WoeG3l1mHc9f4LWhnNTOR3i5tWatcLIAz9VUayUc4zQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Fl72teU0c0moa/PQPHKu6brcxhAfau5OZq2LE0vvXnWJDXGkzvXJewTZvGx0KImc0S9yIjPu/QML0v5RIBueu+b8t7GDEsVwE89jSG3pVotL+zKUehV8c5ltVWGFKke2D78GvzC6nxThSf/weqObllF3me9D4l58Jcwfpt+blTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1280032|-1;CH=blue;DM=|OVERLOAD|false|;DS=CONTINUE|ham_alarm|0.00862387-8.83284e-05-0.991288;FP=14403770588962881983|4|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037032089;MF=fuhao@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.h.BSWZF_1774598870; Received: from higon..(mailfrom:fuhao@open-hieco.net fp:SMTPD_---.h.BSWZF_1774598870 cluster:ay29) by smtp.aliyun-inc.com; Fri, 27 Mar 2026 16:07:56 +0800 From: Fu Hao To: puwen@hygon.cn, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com Cc: linux-kernel@vger.kernel.org, Fu Hao Subject: [PATCH 1/8] x86/cpu/hygon: Adjust the die_id and logical_die_id for Hygon model 4h~8h Date: Fri, 27 Mar 2026 16:07:31 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The die id should be get from the NodeId field of CPUID leaf 0x8000001e ecx for Hygon model 4h~8h processors. Signed-off-by: Fu Hao --- arch/x86/kernel/cpu/hygon.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 7f95a74e4..f39d32a68 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -168,6 +168,19 @@ static void early_init_hygon(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_VMMCALL); } =20 +/* + * Adjust the die_id and logical_die_id for Hygon model 4h~8h. + */ +static void cpu_topology_fixup_hygon(struct cpuinfo_x86 *c) +{ + if (c->x86_model >=3D 0x4 && c->x86_model <=3D 0x8) { + c->topo.die_id =3D cpuid_ecx(0x8000001e) & 0xff; + c->topo.logical_die_id =3D (c->topo.die_id >> 4) * + topology_amd_nodes_per_pkg() + + (c->topo.die_id & 0xf); + } +} + static void init_hygon(struct cpuinfo_x86 *c) { u64 vm_cr; @@ -191,6 +204,8 @@ static void init_hygon(struct cpuinfo_x86 *c) =20 init_hygon_cacheinfo(c); =20 + cpu_topology_fixup_hygon(c); + if (cpu_has(c, X86_FEATURE_SVM)) { rdmsrq(MSR_VM_CR, vm_cr); if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { --=20 2.34.1 From nobody Thu Apr 2 16:58:52 2026 Received: from out28-107.mail.aliyun.com (out28-107.mail.aliyun.com [115.124.28.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC4763A5E77 for ; Fri, 27 Mar 2026 08:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774598931; cv=none; b=IFSPc0xNc5lja/obSnF0rWeyW6hjlOdR6Al/FMvg1TopU8CLW4R+8pqJyhrWP8ILhG1PI/Hp8Vy0IUmQYux/ReBJgU1Jk1waqd4V0grTf3GrvVHZ7BIuGWvnzCoxS/D3C6t4OwKqLuVBMnMwD3wiaOVTpoibU9hTTwYwFoZlZEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774598931; c=relaxed/simple; bh=oibeUgxHcNCRV8WSG7Akkc5rxD45S1mXhPzoWTwmtys=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fouDLP/edkWG5RQbWi975KmWHNeF42hsE+llo6eMFDE4E9BQg6efp06maPB/oAkTvayoHkOEWc+Ma5VLrHOie+QzEjm+gkK0xlvDfRWTe0ckAaKaczouygvbPFMLzbMo1Sy0WRw2IBfJOuszGj6w4y48vu2suL7crxaBY1VsK5w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.09426788|-1;CH=blue;DM=|OVERLOAD|false|;DS=CONTINUE|ham_system_inform|0.0559394-0.000520006-0.943541;FP=5616368311665788086|4|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037006180;MF=fuhao@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.h.JPrSH_1774598908; Received: from higon..(mailfrom:fuhao@open-hieco.net fp:SMTPD_---.h.JPrSH_1774598908 cluster:ay29) by smtp.aliyun-inc.com; Fri, 27 Mar 2026 16:08:34 +0800 From: Fu Hao To: tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com Cc: linux-kernel@vger.kernel.org, Fu Hao Subject: [PATCH 2/8] x86/cpu: Get LLC ID for Hygon family 18h model 4h Date: Fri, 27 Mar 2026 16:08:25 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to calculate LLC ID from the number of threads sharing the cache for Hygon family 18h model 4h processor. Signed-off-by: Fu Hao --- arch/x86/kernel/cpu/cacheinfo.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 51a95b078..98862afc4 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -341,11 +341,23 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *= c) if (!cpuid_amd_hygon_has_l3_cache()) return; =20 - /* - * Hygons are similar to AMD Family 17h up to 1F models: LLC is - * at the core complex level. Core complex ID is ApicId[3]. - */ - c->topo.llc_id =3D c->topo.apicid >> 3; + if (c->x86_model >=3D 0x4) { + /* + * From model 4h: LLC ID is calculated from the number + * of threads sharing the L3 cache. + */ + u32 llc_index =3D find_num_cache_leaves(c) - 1; + struct _cpuid4_info id4 =3D {}; + + if (!amd_fill_cpuid4_info(llc_index, &id4)) + c->topo.llc_id =3D get_cache_id(c->topo.apicid, &id4); + } else { + /* + * The others are similar to AMD Family 17h up to 1F models: LLC is + * at the core complex level. Core complex ID is ApicId[3]. + */ + c->topo.llc_id =3D c->topo.apicid >> 3; + } } =20 void init_amd_cacheinfo(struct cpuinfo_x86 *c) --=20 2.34.1 From nobody Thu Apr 2 16:58:52 2026 Received: from out198-41.us.a.mail.aliyun.com (out198-41.us.a.mail.aliyun.com [47.90.198.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D86A3CD8A4 for ; Fri, 27 Mar 2026 08:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599290; cv=none; b=pEI+Fw00H6FPJrd9RbPKqHy3B4pRM9pSjbWbteSRd1g7T3efnYqFJpQeLpqF7FjFfu/t7qvMnL7IbOe1/pcZzTjQQ+BTHw6+enIXKzNANoJ7YU1+hYjdtM82FeVqczBq93sNDAEUpYFD+y8aX28UMSO+0H0mr31tFRmA/dPCXKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599290; c=relaxed/simple; bh=4y50c30r3UyxOZkO8Zd+adYqYovVf8QS0bgi7O6npSs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SijvbshCGBtIxn/iZsfPvHgoF8z+6omkL/JsTuU9M/YZmwvuKxhpMAu3zYbPK+h8/7o89xwm+gH+smYUMLsFg+6Od/8Oiobb/NfLIowRld4bog17rR6CLaQd3dw0JlpdfL2UGeI1vUU7LgiZJTOqESaMmRd7VkaEnmfZkzWsXmA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1895277|-1;CH=blue;DM=|OVERLOAD|false|;DS=CONTINUE|ham_system_inform|0.00462074-0.000241749-0.995138;FP=12090291488864961999|4|1|1|0|-1|-1|-1;HT=maildocker-contentspam033068005250;MF=fuhao@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.h.G3Gej_1774598949; Received: from higon..(mailfrom:fuhao@open-hieco.net fp:SMTPD_---.h.G3Gej_1774598949 cluster:ay29) by smtp.aliyun-inc.com; Fri, 27 Mar 2026 16:09:14 +0800 From: Fu Hao To: puwen@hygon.cn, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com Cc: linux-kernel@vger.kernel.org, Fu Hao Subject: [PATCH 3/8] x86/cpu/hygon: Remove Spectral Chicken for Hygon processors Date: Fri, 27 Mar 2026 16:09:05 +0800 Message-Id: <433c4c2c9f6bea00d69e71d95c2b65deb9a22e41.1774595153.git.fuhao@open-hieco.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The chicken bit is not need to be set for Hygon processors, so remove it. Fixes: d7caac991fee ("x86/cpu/amd: Add Spectral Chicken") Signed-off-by: Fu Hao --- arch/x86/kernel/cpu/hygon.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index f39d32a68..72110eb73 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -189,12 +189,6 @@ static void init_hygon(struct cpuinfo_x86 *c) =20 set_cpu_cap(c, X86_FEATURE_REP_GOOD); =20 - /* - * XXX someone from Hygon needs to confirm this DTRT - * - init_spectral_chicken(c); - */ - set_cpu_cap(c, X86_FEATURE_ZEN); set_cpu_cap(c, X86_FEATURE_CPB); =20 --=20 2.34.1 From nobody Thu Apr 2 16:58:52 2026 Received: from out28-133.mail.aliyun.com (out28-133.mail.aliyun.com [115.124.28.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A07AA3CD8A4; Fri, 27 Mar 2026 08:09:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.133 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599000; cv=none; b=aq4gcyrsQ9QmFh5l34hmIHOefO7SyCGyBbVQ+IQ2DU8jfx5OMC3iKzcp56Mq0xWYTiI8Hur8n5pGlFl32GLCGF9OV7VljnuKvk7e7B8+38MXy57FcEWwKWFodjgSsbKTdZCwWWFHDMYlTwwMmuAB0zYfn/aiBLbdV0MGfJ2Nanc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599000; c=relaxed/simple; bh=jekUoRM6xAl2PNYqAev73aVpcZjT/bi7bFrfh8DgPEI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PIRkDyShtq3HOBB5KdjGmUjMcvfjAJV7YQaCQJXZMfxdjN4KW8pCohHP6cG4nNRFo0lvTFXotTkANLzOyeQFXpv1sbtXsQ4cd0cf5h4MXn9/abxMdDl1VW7vrZDR2fKE8bKvqW+UqdrLxHgP2mFoBK/1MzKtUm3BJvZkjdP301w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.133 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436463|-1;CH=blue;DM=|OVERLOAD|false|;DS=CONTINUE|ham_alarm|0.00828711-0.000511096-0.991202;FP=5927386199564553616|3|1|1|0|-1|-1|-1;HT=maildocker-contentspam033045220102;MF=fuhao@open-hieco.net;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.h.LaOdR_1774598985; Received: from higon..(mailfrom:fuhao@open-hieco.net fp:SMTPD_---.h.LaOdR_1774598985 cluster:ay29) by smtp.aliyun-inc.com; Fri, 27 Mar 2026 16:09:51 +0800 From: Fu Hao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, tglx@kernel.org, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, hpa@zytor.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Fu Hao Subject: [PATCH 4/8] perf/x86/uncore: Add L3 PMU support for Hygon family 18h model 6h Date: Fri, 27 Mar 2026 16:09:38 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adjust the L3 PMU slicemask and threadmask for Hygon family 18h model 6h processor. Signed-off-by: Fu Hao --- arch/x86/events/amd/uncore.c | 48 ++++++++++++++++++++++++++++++- arch/x86/include/asm/perf_event.h | 8 ++++++ 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index dd956cfca..e71d9e784 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -308,6 +308,14 @@ amd_f17h_uncore_is_visible(struct kobject *kobj, struc= t attribute *attr, int i) attr->mode : 0; } =20 +static umode_t +hygon_f18h_m6h_uncore_is_visible(struct kobject *kobj, struct attribute *a= ttr, int i) +{ + return boot_cpu_data.x86 =3D=3D 0x18 && + boot_cpu_data.x86_model >=3D 0x6 && boot_cpu_data.x86_model <=3D 0= xf ? + attr->mode : 0; +} + static umode_t amd_f19h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, i= nt i) { @@ -359,6 +367,8 @@ DEFINE_UNCORE_FORMAT_ATTR(enallslices, enallslices, "co= nfig:46"); /* F19h L3 DEFINE_UNCORE_FORMAT_ATTR(enallcores, enallcores, "config:47"); /* F19= h L3 */ DEFINE_UNCORE_FORMAT_ATTR(sliceid, sliceid, "config:48-50"); /* F19h L3= */ DEFINE_UNCORE_FORMAT_ATTR(rdwrmask, rdwrmask, "config:8-9"); /* PerfMo= nV2 UMC */ +DEFINE_UNCORE_FORMAT_ATTR(slicemask4, slicemask, "config:28-31"); /* F1= 8h L3 */ +DEFINE_UNCORE_FORMAT_ATTR(threadmask32, threadmask, "config:32-63"); /*= F18h L3 */ =20 /* Common DF and NB attributes */ static struct attribute *amd_uncore_df_format_attr[] =3D { @@ -388,6 +398,12 @@ static struct attribute *amd_f17h_uncore_l3_format_att= r[] =3D { NULL, }; =20 +/* F18h M06h unique L3 attributes */ +static struct attribute *hygon_f18h_m6h_uncore_l3_format_attr[] =3D { + &format_attr_slicemask4.attr, /* slicemask */ + NULL, +}; + /* F19h unique L3 attributes */ static struct attribute *amd_f19h_uncore_l3_format_attr[] =3D { &format_attr_coreid.attr, /* coreid */ @@ -413,6 +429,12 @@ static struct attribute_group amd_f17h_uncore_l3_forma= t_group =3D { .is_visible =3D amd_f17h_uncore_is_visible, }; =20 +static struct attribute_group hygon_f18h_m6h_uncore_l3_format_group =3D { + .name =3D "format", + .attrs =3D hygon_f18h_m6h_uncore_l3_format_attr, + .is_visible =3D hygon_f18h_m6h_uncore_is_visible, +}; + static struct attribute_group amd_f19h_uncore_l3_format_group =3D { .name =3D "format", .attrs =3D amd_f19h_uncore_l3_format_attr, @@ -442,6 +464,11 @@ static const struct attribute_group *amd_uncore_l3_att= r_update[] =3D { NULL, }; =20 +static const struct attribute_group *hygon_uncore_l3_attr_update[] =3D { + &hygon_f18h_m6h_uncore_l3_format_group, + NULL, +}; + static const struct attribute_group *amd_uncore_umc_attr_groups[] =3D { &amd_uncore_attr_group, &amd_uncore_umc_format_group, @@ -820,6 +847,12 @@ static int amd_uncore_l3_event_init(struct perf_event = *event) mask =3D AMD64_L3_F19H_THREAD_MASK | AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES; =20 + if (boot_cpu_data.x86 =3D=3D 0x18 && + boot_cpu_data.x86_model >=3D 0x6 && + boot_cpu_data.x86_model <=3D 0xf) + mask =3D ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) | + ((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK); + hwc->config |=3D mask; =20 return 0; @@ -877,7 +910,8 @@ int amd_uncore_l3_ctx_init(struct amd_uncore *uncore, u= nsigned int cpu) pmu->rdpmc_base =3D RDPMC_BASE_LLC; pmu->group =3D amd_uncore_ctx_gid(uncore, cpu); =20 - if (boot_cpu_data.x86 >=3D 0x17) { + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && + boot_cpu_data.x86 >=3D 0x17) { *l3_attr++ =3D &format_attr_event8.attr; *l3_attr++ =3D &format_attr_umask8.attr; *l3_attr++ =3D boot_cpu_data.x86 >=3D 0x19 ? @@ -904,6 +938,18 @@ int amd_uncore_l3_ctx_init(struct amd_uncore *uncore, = unsigned int cpu) .module =3D THIS_MODULE, }; =20 + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON && + boot_cpu_data.x86 =3D=3D 0x18) { + *l3_attr++ =3D &format_attr_event8.attr; + *l3_attr++ =3D &format_attr_umask8.attr; + if (boot_cpu_data.x86_model >=3D 0x6 && boot_cpu_data.x86_model <=3D 0xf= ) { + *l3_attr++ =3D &format_attr_threadmask32.attr; + pmu->pmu.attr_update =3D hygon_uncore_l3_attr_update; + } else { + *l3_attr++ =3D &format_attr_threadmask8.attr; + } + } + if (perf_pmu_register(&pmu->pmu, pmu->pmu.name, -1)) { free_percpu(pmu->ctx); pmu->ctx =3D NULL; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index ff5acb8b1..404752601 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -89,6 +89,14 @@ #define AMD64_L3_COREID_MASK \ (0x7ULL << AMD64_L3_COREID_SHIFT) =20 +#define HYGON_L3_SLICE_SHIFT 28 +#define HYGON_L3_SLICE_MASK \ + (0xFULL << HYGON_L3_SLICE_SHIFT) + +#define HYGON_L3_THREAD_SHIFT 32 +#define HYGON_L3_THREAD_MASK \ + (0xFFFFFFFFULL << HYGON_L3_THREAD_SHIFT) + #define X86_RAW_EVENT_MASK \ (ARCH_PERFMON_EVENTSEL_EVENT | \ ARCH_PERFMON_EVENTSEL_UMASK | \ --=20 2.34.1 From nobody Thu Apr 2 16:58:52 2026 Received: from out28-106.mail.aliyun.com (out28-106.mail.aliyun.com [115.124.28.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA3953C2798 for ; Fri, 27 Mar 2026 08:10:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599027; cv=none; b=fw4ZuLH9egnbwgzK7at79My1dr5Wi7aEs58GZYgJwdFgSmqTkerXxwvhKt2kOxX3bnYNv86KEJfIjruLRTDhh32+pdwZRr1JL5T+C4QyGhRvEj6J7sDzDPdZKd3HnJ4wMM9a35h6yOqz6WvpcdqCtDquq9A0T8m3rl8rOZax2CU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599027; c=relaxed/simple; bh=Sb3qrMkICVL2Yuh5+GEgMaKTrVJ6Z6EYyoo5cAcIiyw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ambk/18N3sX76COuTe6bXDhl0rCR4DrmBCsp2ZRmfmhuoqdMlJ7z7Woh08kjF0ZKLHtrYJ918dRLo608LLSpUamHAQJoSUEP38CsLpWzERvvuj6lIOGeHdftKUtl5bWpeOJfJVPJ/XM9WS+1Ri/kyypoA1NaoMjQT/XvommDNFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=blue;DM=|OVERLOAD|false|;DS=CONTINUE|ham_alarm|0.00359679-0.00150827-0.994895;FP=13686271970075284603|4|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037022039;MF=fuhao@open-hieco.net;NM=1;PH=DS;RN=8;RT=8;SR=0;TI=SMTPD_---.h.LaP6h_1774599011; Received: from higon..(mailfrom:fuhao@open-hieco.net fp:SMTPD_---.h.LaP6h_1774599011 cluster:ay29) by smtp.aliyun-inc.com; Fri, 27 Mar 2026 16:10:18 +0800 From: Fu Hao To: tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com Cc: linux-kernel@vger.kernel.org, Fu Hao Subject: [PATCH 5/8] x86/microcode/hygon: Add microcode loading support for Hygon processors Date: Fri, 27 Mar 2026 16:10:09 +0800 Message-Id: <944d5379c699bbb0ef5122d5860ad1ca01188885.1774595153.git.fuhao@open-hieco.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for loading Hygon microcode, which is compatible with AMD one. Signed-off-by: Fu Hao --- arch/x86/Kconfig | 2 +- arch/x86/kernel/cpu/microcode/amd.c | 63 ++++++++++++++++++------ arch/x86/kernel/cpu/microcode/core.c | 11 +++++ arch/x86/kernel/cpu/microcode/internal.h | 12 +++++ 4 files changed, 73 insertions(+), 15 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e2df1b147..b94f3dbf1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1330,7 +1330,7 @@ config X86_REBOOTFIXUPS =20 config MICROCODE def_bool y - depends on CPU_SUP_AMD || CPU_SUP_INTEL + depends on CPU_SUP_AMD || CPU_SUP_INTEL || CPU_SUP_HYGON select CRYPTO_LIB_SHA256 if CPU_SUP_AMD =20 config MICROCODE_INITRD32 diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index e53388128..0f2d4829c 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -347,7 +347,8 @@ static u16 find_equiv_id(struct equiv_cpu_table *et, u3= 2 sig) unsigned int i; =20 /* Zen and newer do not need an equivalence table. */ - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) return 0; =20 if (!et || !et->num_entries) @@ -397,7 +398,8 @@ static bool verify_equivalence_table(const u8 *buf, siz= e_t buf_size) return false; =20 /* Zen and newer do not need an equivalence table. */ - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) return true; =20 cont_type =3D hdr[1]; @@ -577,7 +579,8 @@ static int verify_patch(const u8 *buf, size_t buf_size,= u32 *patch_size) static bool mc_patch_matches(struct microcode_amd *mc, u16 eq_id) { /* Zen and newer do not need an equivalence table. */ - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) return ucode_rev_to_cpuid(mc->hdr.patch_id).full =3D=3D bsp_cpuid_1_eax; else return eq_id =3D=3D mc->hdr.processor_rev_id; @@ -701,7 +704,9 @@ static bool __apply_microcode_amd(struct microcode_amd = *mc, u32 *cur_rev, =20 native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr); =20 - if (x86_family(bsp_cpuid_1_eax) =3D=3D 0x17) { + if ((x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) =3D=3D 0x17) || + x86_cpuid_vendor() =3D=3D X86_VENDOR_HYGON) { unsigned long p_addr_end =3D p_addr + psize - 1; =20 invlpg(p_addr); @@ -730,16 +735,19 @@ static bool __apply_microcode_amd(struct microcode_am= d *mc, u32 *cur_rev, =20 static bool get_builtin_microcode(struct cpio_data *cp) { - char fw_name[36] =3D "amd-ucode/microcode_amd.bin"; + char fw_name[40] =3D "amd-ucode/microcode_amd.bin"; u8 family =3D x86_family(bsp_cpuid_1_eax); struct firmware fw; =20 if (IS_ENABLED(CONFIG_X86_32)) return false; =20 - if (family >=3D 0x15) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && family >=3D 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%02hhxh.bin", family); + else if (x86_cpuid_vendor() =3D=3D X86_VENDOR_HYGON) + snprintf(fw_name, sizeof(fw_name), + "hygon-ucode/microcode_hygon_fam%.2xh.bin", family); =20 if (firmware_request_builtin(&fw, fw_name)) { cp->size =3D fw.size; @@ -824,7 +832,8 @@ static inline bool patch_cpus_equivalent(struct ucode_p= atch *p, bool ignore_stepping) { /* Zen and newer hardcode the f/m/s in the patch ID */ - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) { + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) { union cpuid_1_eax p_cid =3D ucode_rev_to_cpuid(p->patch_id); union cpuid_1_eax n_cid =3D ucode_rev_to_cpuid(n->patch_id); =20 @@ -860,7 +869,8 @@ static struct ucode_patch *cache_find_patch(struct ucod= e_cpu_info *uci, u16 equi static inline int patch_newer(struct ucode_patch *p, struct ucode_patch *n) { /* Zen and newer hardcode the f/m/s in the patch ID */ - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) { + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) { union zen_patch_rev zp, zn; =20 zp.ucode_rev =3D p->patch_id; @@ -920,7 +930,9 @@ static struct ucode_patch *find_patch(unsigned int cpu) =20 uci->cpu_sig.rev =3D get_patch_level(); =20 - if (x86_family(bsp_cpuid_1_eax) < 0x17) { + if ((x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) < 0x17) || + x86_cpuid_vendor() =3D=3D X86_VENDOR_HYGON) { equiv_id =3D find_equiv_id(&equiv_table, uci->cpu_sig.sig); if (!equiv_id) return NULL; @@ -1035,7 +1047,8 @@ static size_t install_equiv_cpu_table(const u8 *buf, = size_t buf_size) equiv_tbl_len =3D hdr[2]; =20 /* Zen and newer do not need an equivalence table. */ - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) goto out; =20 equiv_table.entry =3D vmalloc(equiv_tbl_len); @@ -1054,7 +1067,8 @@ static size_t install_equiv_cpu_table(const u8 *buf, = size_t buf_size) =20 static void free_equiv_cpu_table(void) { - if (x86_family(bsp_cpuid_1_eax) >=3D 0x17) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && + x86_family(bsp_cpuid_1_eax) >=3D 0x17) return; =20 vfree(equiv_table.entry); @@ -1200,7 +1214,9 @@ static int __init save_microcode_in_initrd(void) enum ucode_state ret; struct cpio_data cp; =20 - if (microcode_loader_disabled() || c->x86_vendor !=3D X86_VENDOR_AMD || c= ->x86 < 0x10) + if (microcode_loader_disabled() || + ((c->x86_vendor !=3D X86_VENDOR_AMD || c->x86 < 0x10) && + (c->x86_vendor !=3D X86_VENDOR_HYGON))) return 0; =20 cpuid_1_eax =3D native_cpuid_eax(1); @@ -1238,7 +1254,7 @@ early_initcall(save_microcode_in_initrd); */ static enum ucode_state request_microcode_amd(int cpu, struct device *devi= ce) { - char fw_name[36] =3D "amd-ucode/microcode_amd.bin"; + char fw_name[40] =3D "amd-ucode/microcode_amd.bin"; struct cpuinfo_x86 *c =3D &cpu_data(cpu); enum ucode_state ret =3D UCODE_NFOUND; const struct firmware *fw; @@ -1246,8 +1262,11 @@ static enum ucode_state request_microcode_amd(int cp= u, struct device *device) if (force_minrev) return UCODE_NFOUND; =20 - if (c->x86 >=3D 0x15) + if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD && c->x86 >=3D 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin= ", c->x86); + else if (x86_cpuid_vendor() =3D=3D X86_VENDOR_HYGON) + snprintf(fw_name, sizeof(fw_name), + "hygon-ucode/microcode_hygon_fam%.2xh.bin", c->x86); =20 if (request_firmware_direct(&fw, (const char *)fw_name, device)) { ucode_dbg("failed to load file %s\n", fw_name); @@ -1297,8 +1316,24 @@ struct microcode_ops * __init init_amd_microcode(voi= d) pr_warn("AMD CPU family 0x%x not supported\n", c->x86); return NULL; } + + return µcode_amd_ops; +} + +#ifdef CONFIG_CPU_SUP_HYGON +struct microcode_ops * __init init_hygon_microcode(void) +{ + struct cpuinfo_x86 *c =3D &boot_cpu_data; + + if (c->x86_vendor !=3D X86_VENDOR_HYGON) + return NULL; + + strscpy((char *)ucode_path, "kernel/x86/microcode/HygonGenuine.bin", + sizeof(ucode_path)); + return µcode_amd_ops; } +#endif =20 void __exit exit_amd_microcode(void) { diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 651202e6f..813c5c157 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -195,6 +195,9 @@ void __init load_ucode_bsp(void) return; intel =3D false; break; + case X86_VENDOR_HYGON: + intel =3D false; + break; =20 default: return; @@ -229,6 +232,9 @@ void load_ucode_ap(void) if (x86_family(cpuid_1_eax) >=3D 0x10) load_ucode_amd_ap(cpuid_1_eax); break; + case X86_VENDOR_HYGON: + load_ucode_amd_ap(cpuid_1_eax); + break; default: break; } @@ -288,6 +294,9 @@ static void reload_early_microcode(unsigned int cpu) if (family >=3D 0x10) reload_ucode_amd(cpu); break; + case X86_VENDOR_HYGON: + reload_ucode_amd(cpu); + break; default: break; } @@ -895,6 +904,8 @@ static int __init microcode_init(void) microcode_ops =3D init_intel_microcode(); else if (c->x86_vendor =3D=3D X86_VENDOR_AMD) microcode_ops =3D init_amd_microcode(); + else if (c->x86_vendor =3D=3D X86_VENDOR_HYGON) + microcode_ops =3D init_hygon_microcode(); else pr_err("no support for this CPU vendor\n"); =20 diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 3b93c0676..75591afae 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -61,6 +61,9 @@ struct cpio_data find_microcode_in_initrd(const char *pat= h); #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') +#define CPUID_HYGON1 QCHAR('H', 'y', 'g', 'o') +#define CPUID_HYGON2 QCHAR('n', 'G', 'e', 'n') +#define CPUID_HYGON3 QCHAR('u', 'i', 'n', 'e') =20 #define CPUID_IS(a, b, c, ebx, ecx, edx) \ (!(((ebx) ^ (a)) | ((edx) ^ (b)) | ((ecx) ^ (c)))) @@ -87,6 +90,9 @@ static inline int x86_cpuid_vendor(void) if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) return X86_VENDOR_AMD; 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charset="utf-8" Add the new PCI ID 0x1d94 0x14a9 for Hygon family 18h model 5h HDA controller. Signed-off-by: Fu Hao --- include/linux/pci_ids.h | 1 + sound/hda/controllers/intel.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 406abf629..19d968017 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2613,6 +2613,7 @@ #define PCI_VENDOR_ID_ROCKCHIP 0x1d87 =20 #define PCI_VENDOR_ID_HYGON 0x1d94 +#define PCI_DEVICE_ID_HYGON_18H_M05H_HDA 0x14a9 =20 #define PCI_VENDOR_ID_META 0x1d9b =20 diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c index 3f434994c..eb5d48d90 100644 --- a/sound/hda/controllers/intel.c +++ b/sound/hda/controllers/intel.c @@ -241,6 +241,7 @@ enum { AZX_DRIVER_ZHAOXIN, AZX_DRIVER_ZHAOXINHDMI, AZX_DRIVER_LOONGSON, + AZX_DRIVER_HYGON, AZX_DRIVER_GENERIC, AZX_NUM_DRIVERS, /* keep this as last entry */ }; @@ -357,6 +358,7 @@ static const char * const driver_short_names[] =3D { [AZX_DRIVER_ZHAOXIN] =3D "HDA Zhaoxin", [AZX_DRIVER_ZHAOXINHDMI] =3D "HDA Zhaoxin HDMI", [AZX_DRIVER_LOONGSON] =3D "HDA Loongson", + [AZX_DRIVER_HYGON] =3D "HDA Hygon", [AZX_DRIVER_GENERIC] =3D "HD-Audio Generic", }; =20 @@ -2818,6 +2820,9 @@ static const struct pci_device_id azx_ids[] =3D { .driver_data =3D AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), .driver_data =3D AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, + /* Hygon HDAudio */ + { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_HDA), + .driver_data =3D AZX_DRIVER_HYGON | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_N= O_MSI }, { 0, } }; MODULE_DEVICE_TABLE(pci, azx_ids); --=20 2.34.1 From nobody Thu Apr 2 16:58:52 2026 Received: from out28-136.mail.aliyun.com (out28-136.mail.aliyun.com [115.124.28.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13A5F3D5651; Fri, 27 Mar 2026 08:16:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599411; cv=none; b=IoGPF3udhblmX0d07mhxTkrTnh101poJIAFA5sOA+Wy8waVwbn2OhWJuKIKMKfcPgMlMY71TcAUuyTZai6kOi+lp8YjrLg0wB2GOvK+jbQsDEf8e7jrAkWq74y7jttDPDTj2H2zf+mjVpN/5Kn3YTja8h1Hfu1TtRZ/P8AWtYhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774599411; c=relaxed/simple; bh=/nxndo//ast7P75ncXLL86cDTV+NCxVD2lEMWPd79lw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H+JEa3oYjvOPuG7jspQ9PVgDdiS+rZeeYXFA1p1F3nyeLZdPBqlgqqITlVYdHszdovvDEVBueXZxLJAxl/6LX83VAHKJM8xWXRR+ICOFTxRyvLAE6fBq/rfgVAoaflfhvkfJ9Zsx1rJPwssr0Lg63MXaStoDSLsh4htndBOeznA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=blue;DM=|OVERLOAD|false|;DS=CONTINUE|ham_system_inform|0.00344733-0.00060156-0.995951;FP=13132325447127404178|3|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037025160;MF=fuhao@open-hieco.net;NM=1;PH=DS;RN=5;RT=5;SR=0;TI=SMTPD_---.h.Byuum_1774599079; Received: from higon..(mailfrom:fuhao@open-hieco.net fp:SMTPD_---.h.Byuum_1774599079 cluster:ay29) by smtp.aliyun-inc.com; Fri, 27 Mar 2026 16:11:25 +0800 From: Fu Hao To: perex@perex.cz, tiwai@suse.com Cc: linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Fu Hao Subject: [PATCH 7/8] ALSA: hda: Fix single byte writing issue for Hygon family 18h model 5h Date: Fri, 27 Mar 2026 16:11:13 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Hygon family 18h model 5h controller, some registers such as GCTL, SD_CTL and SD_CTL_3B should be accessed in dword, or the writing will fail. Signed-off-by: Fu Hao --- include/sound/hdaudio.h | 1 + sound/hda/controllers/intel.c | 4 ++++ sound/hda/core/controller.c | 10 +++++++-- sound/hda/core/stream.c | 42 ++++++++++++++++++++++++++--------- 4 files changed, 45 insertions(+), 12 deletions(-) diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index f11bfc6b9..57a144fec 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -352,6 +352,7 @@ struct hdac_bus { bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */ bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword = */ bool use_pio_for_commands:1; /* Use PIO instead of CORB for commands */ + bool hygon_dword_access:1; =20 int poll_count; =20 diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c index eb5d48d90..6b27248dc 100644 --- a/sound/hda/controllers/intel.c +++ b/sound/hda/controllers/intel.c @@ -1885,6 +1885,10 @@ static int azx_first_init(struct azx *chip) if (chip->driver_type =3D=3D AZX_DRIVER_ZHAOXINHDMI) bus->polling_mode =3D 1; =20 + if (chip->driver_type =3D=3D AZX_DRIVER_HYGON && + chip->pci->device =3D=3D PCI_DEVICE_ID_HYGON_18H_M05H_HDA) + bus->hygon_dword_access =3D 1; + bus->remap_addr =3D pcim_iomap_region(pci, 0, "ICH HD audio"); if (IS_ERR(bus->remap_addr)) return PTR_ERR(bus->remap_addr); diff --git a/sound/hda/core/controller.c b/sound/hda/core/controller.c index 69e11d62b..bfe817045 100644 --- a/sound/hda/core/controller.c +++ b/sound/hda/core/controller.c @@ -511,7 +511,10 @@ void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) { unsigned long timeout; =20 - snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); + if (bus->hygon_dword_access) + snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); + else + snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); =20 timeout =3D jiffies + msecs_to_jiffies(100); while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) @@ -576,7 +579,10 @@ static void azx_int_disable(struct hdac_bus *bus) =20 /* disable interrupts in stream descriptor */ list_for_each_entry(azx_dev, &bus->stream_list, list) - snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); + if (bus->hygon_dword_access) + snd_hdac_stream_updatel(azx_dev, SD_CTL, SD_INT_MASK, 0); + else + snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); =20 /* disable SIE for all streams & disable controller CIE and GIE */ snd_hdac_chip_writel(bus, INTCTL, 0); diff --git a/sound/hda/core/stream.c b/sound/hda/core/stream.c index b471a038b..ccc0003a8 100644 --- a/sound/hda/core/stream.c +++ b/sound/hda/core/stream.c @@ -146,11 +146,15 @@ void snd_hdac_stream_start(struct hdac_stream *azx_de= v) stripe_ctl =3D snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); else stripe_ctl =3D 0; - snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, - stripe_ctl); + if (bus->hygon_dword_access) + snd_hdac_stream_updatel(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, + stripe_ctl); + else + snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, + stripe_ctl); } /* set DMA start and interrupt mask */ - if (bus->access_sdnctl_in_dword) + if (bus->access_sdnctl_in_dword || bus->hygon_dword_access) snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_CTL_DMA_START | SD_INT_MASK); else @@ -166,11 +170,22 @@ EXPORT_SYMBOL_GPL(snd_hdac_stream_start); */ static void snd_hdac_stream_clear(struct hdac_stream *azx_dev) { - snd_hdac_stream_updateb(azx_dev, SD_CTL, - SD_CTL_DMA_START | SD_INT_MASK, 0); - snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ - if (azx_dev->stripe) - snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); + struct hdac_bus *bus =3D azx_dev->bus; + + if (bus->hygon_dword_access) { + snd_hdac_stream_updatel(azx_dev, SD_CTL, + SD_CTL_DMA_START | SD_INT_MASK, 0); + snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ + if (azx_dev->stripe) + snd_hdac_stream_updatel(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); + } else { + snd_hdac_stream_updateb(azx_dev, SD_CTL, + SD_CTL_DMA_START | SD_INT_MASK, 0); + snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ + if (azx_dev->stripe) + snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); + } + azx_dev->running =3D false; } =20 @@ -225,12 +240,16 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_de= v) { unsigned char val; int dma_run_state; + struct hdac_bus *bus =3D azx_dev->bus; =20 snd_hdac_stream_clear(azx_dev); =20 dma_run_state =3D snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_STA= RT; =20 - snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); + if (bus->hygon_dword_access) + snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); + else + snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); =20 /* wait for hardware to report that the stream entered reset */ snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RES= ET), 3, 300); @@ -238,7 +257,10 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) if (azx_dev->bus->dma_stop_delay && dma_run_state) udelay(azx_dev->bus->dma_stop_delay); =20 - snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); + if (bus->hygon_dword_access) + snd_hdac_stream_updatel(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); + else + snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); =20 /* wait for hardware to report that the stream is out of reset */ snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RE= SET), 3, 300); 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charset="utf-8" The SB IOAPIC is on the device 0xb from Hygon family 18h model 4h. Signed-off-by: Fu Hao --- drivers/iommu/amd/init.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index f3fd7f39e..568851cc2 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -3096,6 +3096,9 @@ static void __init free_iommu_resources(void) /* SB IOAPIC is always on this device in AMD systems */ #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) =20 +/* SB IOAPIC for Hygon family 18h model 4h is on the device 0xb */ +#define IOAPIC_SB_DEVID_FAM18H_M4H ((0x00 << 8) | PCI_DEVFN(0xb, 0)) + static bool __init check_ioapic_information(void) { const char *fw_bug =3D FW_BUG; @@ -3121,7 +3124,12 @@ static bool __init check_ioapic_information(void) pr_err("%s: IOAPIC[%d] not in IVRS table\n", fw_bug, id); ret =3D false; - } else if (devid =3D=3D IOAPIC_SB_DEVID) { + } else if (devid =3D=3D IOAPIC_SB_DEVID || + (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON && + boot_cpu_data.x86 =3D=3D 0x18 && + boot_cpu_data.x86_model >=3D 0x4 && + boot_cpu_data.x86_model <=3D 0xf && + devid =3D=3D IOAPIC_SB_DEVID_FAM18H_M4H)) { has_sb_ioapic =3D true; ret =3D true; } --=20 2.34.1