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Tue, 17 Mar 2026 07:40:23 -0700 (PDT) Date: Tue, 17 Mar 2026 17:40:20 +0300 From: Dan Carpenter To: Linus Walleij , AKASHI Takahiro Cc: Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , arm-scmi@vger.kernel.org, Vincent Guittot , Khaled Ali Ahmed , Michal Simek Subject: [PATCH v4 1/7] pinctrl: introduce pinctrl_gpio_get_config() Message-ID: <22af6c960a7d20eb09e57e91821abe7ffbc52b9c.1773757772.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AKASHI Takahiro This is a counterpart of pinctrl_gpio_set_config(), which will be used to implement the ->get() interface in a GPIO driver for SCMI. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko --- v4: Fix kernel-doc (Andy) drivers/pinctrl/core.c | 31 +++++++++++++++++++++++++++++++ include/linux/pinctrl/consumer.h | 9 +++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 2edc9bdad183..c471f3fbd035 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -30,6 +30,7 @@ #include #include #include +#include #include =20 #include "core.h" @@ -938,6 +939,36 @@ int pinctrl_gpio_set_config(struct gpio_chip *gc, unsi= gned int offset, } EXPORT_SYMBOL_GPL(pinctrl_gpio_set_config); =20 +/** + * pinctrl_gpio_get_config() - Get the config for a given GPIO pin + * @gc: GPIO chip structure from the GPIO subsystem + * @offset: hardware offset of the GPIO relative to the controller + * @config: the configuration to query. On success it holds the result + * Return: 0 on success, negative errno otherwise + */ +int pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, uns= igned long *config) +{ + struct pinctrl_gpio_range *range; + struct pinctrl_dev *pctldev; + int ret, pin; + + ret =3D pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range); + if (ret) + return ret; + + mutex_lock(&pctldev->mutex); + pin =3D gpio_to_pin(range, gc, offset); + ret =3D pin_config_get_for_pin(pctldev, pin, config); + mutex_unlock(&pctldev->mutex); + + if (ret) + return ret; + + *config =3D pinconf_to_config_argument(*config); + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_gpio_get_config); + static struct pinctrl_state *find_state(struct pinctrl *p, const char *name) { diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consu= mer.h index 63ce16191eb9..11b8f0b8da0c 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -35,6 +35,8 @@ int pinctrl_gpio_direction_output(struct gpio_chip *gc, unsigned int offset); int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config); +int pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config); =20 struct pinctrl * __must_check pinctrl_get(struct device *dev); void pinctrl_put(struct pinctrl *p); @@ -101,6 +103,13 @@ pinctrl_gpio_direction_output(struct gpio_chip *gc, un= signed int offset) return 0; } =20 +static inline int +pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config) +{ + return 0; +} + static inline int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config) --=20 2.51.0 From nobody Mon Apr 6 23:25:00 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46F9D3E715F for ; Tue, 17 Mar 2026 14:40:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 17 Mar 2026 07:40:30 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b976cf380f2sm755154766b.53.2026.03.17.07.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 07:40:30 -0700 (PDT) Date: Tue, 17 Mar 2026 17:40:27 +0300 From: Dan Carpenter To: Sudeep Holla , AKASHI Takahiro Cc: Cristian Marussi , Linus Walleij , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Bartosz Golaszewski , Vincent Guittot , Khaled Ali Ahmed , Michal Simek Subject: [PATCH v4 2/7] pinctrl: scmi: Add SCMI_PIN_INPUT_VALUE Message-ID: <940ff48bd53e35e19a4cda081170d9198c20675e.1773757772.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PIN_CONFIG_LEVEL parameter represents the value of the pin, whether reading or writing to the pin. In SCMI, the parameter is represented by two different values SCMI_PIN_OUTPUT_VALUE for writing to a pin and SCMI_PIN_INPUT_VALUE for reading. The current code translates PIN_CONFIG_LEVEL as SCMI_PIN_OUTPUT_VALUE (writing). Add a function to translate it to either INPUT or OUTPUT depending on whether it is called from a _get or _set() operation. Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij Acked-by: Sudeep Holla --- drivers/pinctrl/pinctrl-scmi.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index f4f296e07be5..5d347e6b2e4c 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -251,9 +251,6 @@ static int pinctrl_scmi_map_pinconf_type(enum pin_confi= g_param param, case PIN_CONFIG_MODE_LOW_POWER: *type =3D SCMI_PIN_LOW_POWER_MODE; break; - case PIN_CONFIG_LEVEL: - *type =3D SCMI_PIN_OUTPUT_VALUE; - break; case PIN_CONFIG_OUTPUT_ENABLE: *type =3D SCMI_PIN_OUTPUT_MODE; break; @@ -276,6 +273,28 @@ static int pinctrl_scmi_map_pinconf_type(enum pin_conf= ig_param param, return 0; } =20 +static int pinctrl_scmi_map_pinconf_type_get(enum pin_config_param param, + enum scmi_pinctrl_conf_type *type) +{ + if (param =3D=3D PIN_CONFIG_LEVEL) { + *type =3D SCMI_PIN_INPUT_VALUE; + return 0; + } + + return pinctrl_scmi_map_pinconf_type(param, type); +} + +static int pinctrl_scmi_map_pinconf_type_set(enum pin_config_param param, + enum scmi_pinctrl_conf_type *type) +{ + if (param =3D=3D PIN_CONFIG_LEVEL) { + *type =3D SCMI_PIN_OUTPUT_VALUE; + return 0; + } + + return pinctrl_scmi_map_pinconf_type(param, type); +} + static int pinctrl_scmi_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { @@ -290,7 +309,7 @@ static int pinctrl_scmi_pinconf_get(struct pinctrl_dev = *pctldev, =20 config_type =3D pinconf_to_config_param(*config); =20 - ret =3D pinctrl_scmi_map_pinconf_type(config_type, &type); + ret =3D pinctrl_scmi_map_pinconf_type_get(config_type, &type); if (ret) return ret; =20 @@ -363,7 +382,7 @@ static int pinctrl_scmi_pinconf_set(struct pinctrl_dev = *pctldev, =20 for (i =3D 0; i < num_configs; i++) { param =3D pinconf_to_config_param(configs[i]); - ret =3D pinctrl_scmi_map_pinconf_type(param, &p_config_type[i]); + ret =3D pinctrl_scmi_map_pinconf_type_set(param, &p_config_type[i]); if (ret) { dev_err(pmx->dev, "Error map pinconf_type %d\n", ret); goto free_config; @@ -405,7 +424,7 @@ static int pinctrl_scmi_pinconf_group_set(struct pinctr= l_dev *pctldev, =20 for (i =3D 0; i < num_configs; i++) { param =3D pinconf_to_config_param(configs[i]); - ret =3D pinctrl_scmi_map_pinconf_type(param, &p_config_type[i]); + ret =3D pinctrl_scmi_map_pinconf_type_set(param, &p_config_type[i]); if (ret) { dev_err(pmx->dev, "Error map pinconf_type %d\n", ret); goto free_config; @@ -440,7 +459,7 @@ static int pinctrl_scmi_pinconf_group_get(struct pinctr= l_dev *pctldev, return -EINVAL; =20 config_type =3D pinconf_to_config_param(*config); - ret =3D pinctrl_scmi_map_pinconf_type(config_type, &type); + ret =3D pinctrl_scmi_map_pinconf_type_get(config_type, &type); if (ret) { dev_err(pmx->dev, "Error map pinconf_type %d\n", ret); return ret; --=20 2.51.0 From nobody Mon Apr 6 23:25:00 2026 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8834B3EAC82 for ; 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charset="utf-8" The argument for PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS is supposed to be expressed in terms of ohms. But the pinctrl-scmi driver was implementing it the same as PIN_CONFIG_OUTPUT and writing either a zero or one to the pin. The SCMI protocol doesn't have an support configuration type so just delete this code instead of replacing it. Cc: Peng Fan Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-scmi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index 5d347e6b2e4c..de8c113bc61d 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -254,9 +254,6 @@ static int pinctrl_scmi_map_pinconf_type(enum pin_confi= g_param param, case PIN_CONFIG_OUTPUT_ENABLE: *type =3D SCMI_PIN_OUTPUT_MODE; break; - case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: - *type =3D SCMI_PIN_OUTPUT_VALUE; - break; case PIN_CONFIG_POWER_SOURCE: *type =3D SCMI_PIN_POWER_SOURCE; break; --=20 2.51.0 From nobody Mon Apr 6 23:25:00 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E75BC3EAC9A for ; Tue, 17 Mar 2026 14:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 17 Mar 2026 07:40:41 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b976cc220basm753466566b.28.2026.03.17.07.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 07:40:40 -0700 (PDT) Date: Tue, 17 Mar 2026 17:40:38 +0300 From: Dan Carpenter To: Sudeep Holla , AKASHI Takahiro Cc: Cristian Marussi , Linus Walleij , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Bartosz Golaszewski , Vincent Guittot , Khaled Ali Ahmed , Michal Simek Subject: [PATCH v4 4/7] pinctrl-scmi: ignore PIN_CONFIG_PERSIST_STATE Message-ID: <10c43dfe5f72eedb259db533004acddd5579e168.1773757772.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PIN_CONFIG_PERSIST_STATE setting ensures that the pin state persists across a sleep or controller reset. The SCMI spec does not have an equivalent command to this so just ignore it. Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-scmi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index de8c113bc61d..f22be6b7b82a 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -361,7 +361,7 @@ static int pinctrl_scmi_pinconf_set(struct pinctrl_dev = *pctldev, unsigned long *configs, unsigned int num_configs) { - int i, ret; + int i, cnt, ret; struct scmi_pinctrl *pmx =3D pinctrl_dev_get_drvdata(pctldev); enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS]; u32 config_value[SCMI_NUM_CONFIGS]; @@ -377,17 +377,21 @@ static int pinctrl_scmi_pinconf_set(struct pinctrl_de= v *pctldev, if (ret) return ret; =20 + cnt =3D 0; for (i =3D 0; i < num_configs; i++) { param =3D pinconf_to_config_param(configs[i]); - ret =3D pinctrl_scmi_map_pinconf_type_set(param, &p_config_type[i]); + if (param =3D=3D PIN_CONFIG_PERSIST_STATE) + continue; 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Tue, 17 Mar 2026 07:40:53 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4855640d915sm118222495e9.4.2026.03.17.07.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 07:40:53 -0700 (PDT) Date: Tue, 17 Mar 2026 17:40:50 +0300 From: Dan Carpenter To: Sudeep Holla , AKASHI Takahiro Cc: Cristian Marussi , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Vincent Guittot , Khaled Ali Ahmed , Michal Simek Subject: [PATCH v4 5/7] arm_scmi: pinctrl: allow PINCTRL_REQUEST to return EOPNOTSUPP Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SCMI protocol specification says that the PINCTRL_REQUEST and PINCTRL_RELEASE commands are optional. So if the SCMI server returns -EOPNOTSUPP, then treat that as success and continue. Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij Reviewed-by: Sudeep Holla --- drivers/firmware/arm_scmi/pinctrl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/arm_scmi/pinctrl.c b/drivers/firmware/arm_scm= i/pinctrl.c index a020e23d7c49..42cb1aef1fe1 100644 --- a/drivers/firmware/arm_scmi/pinctrl.c +++ b/drivers/firmware/arm_scmi/pinctrl.c @@ -578,6 +578,8 @@ static int scmi_pinctrl_request_free(const struct scmi_= protocol_handle *ph, tx->flags =3D cpu_to_le32(type); =20 ret =3D ph->xops->do_xfer(ph, t); + if (ret =3D=3D -EOPNOTSUPP) + ret =3D 0; ph->xops->xfer_put(ph, t); =20 return ret; --=20 2.51.0 From nobody Mon Apr 6 23:25:00 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 864483E8687 for ; Tue, 17 Mar 2026 14:41:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: AKASHI Takahiro Add a dt binding for the gpio-by-pinctrl driver. The driver is used for doing GPIO over the SCMI pinctrl protocol. There are a few mandatory properties such as gpio-ranges and ngpios, but it's not mandatory to specify the pin-mux. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij --- v4: Changed additionalProperties: true to false. My concern here was that there might be a lot of gpio properties which I wasn't familiar with. To check I did: grep :$ Documentation/devicetree/bindings/gpio/* | \ cut -d : -f 2- | perl -ne 's/[\ ]*//g; print "$_\n"' | \ sort | uniq -c The only property that I decided to add was gpio-line-names. Deleted the extra bonus example. .../bindings/gpio/pin-control-gpio.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/pin-control-gpio= .yaml diff --git a/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml b= /Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml new file mode 100644 index 000000000000..ebc3fdd039fd --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/pin-control-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin control based generic GPIO controller + +description: + The pin control-based GPIO will facilitate a pin controller's ability + to drive electric lines high/low and other generic properties of a + pin controller to perform general-purpose one-bit binary I/O. + +maintainers: + - Dan Carpenter + +properties: + compatible: + const: scmi-pinctrl-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: true + + gpio-ranges: true + + ngpios: true + +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + +required: + - compatible + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - ngpios + +additionalProperties: false + +examples: + - | + gpio { + compatible =3D "scmi-pinctrl-gpio"; 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Tue, 17 Mar 2026 07:41:05 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6634fdb6421sm6834806a12.8.2026.03.17.07.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 07:41:05 -0700 (PDT) Date: Tue, 17 Mar 2026 17:41:02 +0300 From: Dan Carpenter To: Linus Walleij , AKASHI Takahiro Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , arm-scmi@vger.kernel.org, Vincent Guittot , Khaled Ali Ahmed , Michal Simek Subject: [PATCH v4 7/7] gpio: add pinctrl based generic gpio driver Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AKASHI Takahiro The ARM SCMI pinctrl protocol allows GPIO access. Instead of creating a new SCMI gpio driver, this driver is a generic GPIO driver that uses standard pinctrl interfaces. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij Acked-by: Bartosz Golaszewski --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-by-pinctrl.c | 124 +++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/gpio/gpio-by-pinctrl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b45fb799e36c..4c8d2589c412 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -246,6 +246,13 @@ config GPIO_BRCMSTB help Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs. =20 +config GPIO_BY_PINCTRL + tristate "GPIO support based on a pure pin control backend" + depends on GPIOLIB + help + Select this option to support GPIO devices based solely on pin + control. This is used to do GPIO over the ARM SCMI protocol. + config GPIO_CADENCE tristate "Cadence GPIO support" depends on OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c05f7d795c43..20d4a57afdaa 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_GPIO_BD9571MWV) +=3D gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BLZP1600) +=3D gpio-blzp1600.o obj-$(CONFIG_GPIO_BRCMSTB) +=3D gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) +=3D gpio-bt8xx.o +obj-$(CONFIG_GPIO_BY_PINCTRL) +=3D gpio-by-pinctrl.o obj-$(CONFIG_GPIO_CADENCE) +=3D gpio-cadence.o obj-$(CONFIG_GPIO_CGBC) +=3D gpio-cgbc.o obj-$(CONFIG_GPIO_CLPS711X) +=3D gpio-clps711x.o diff --git a/drivers/gpio/gpio-by-pinctrl.c b/drivers/gpio/gpio-by-pinctrl.c new file mode 100644 index 000000000000..51d99723d3ca --- /dev/null +++ b/drivers/gpio/gpio-by-pinctrl.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2023 Linaro Inc. +// Author: AKASHI takahiro + +#include +#include +#include +#include +#include +#include +#include "gpiolib.h" + +struct pin_control_gpio_priv { + struct gpio_chip chip; +}; + +static int pin_control_gpio_get_direction(struct gpio_chip *gc, unsigned i= nt offset) +{ + unsigned long config; + bool in, out; + int ret; + + config =3D PIN_CONFIG_INPUT_ENABLE; + ret =3D pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + in =3D config; + + config =3D PIN_CONFIG_OUTPUT_ENABLE; + ret =3D pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + out =3D config; + + /* Consistency check - in theory both can be enabled! */ + if (in && !out) + return GPIO_LINE_DIRECTION_IN; + if (!in && out) + return GPIO_LINE_DIRECTION_OUT; + + return -EINVAL; +} + +static int pin_control_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + return pinctrl_gpio_direction_output(chip, offset); +} + +static int pin_control_gpio_get(struct gpio_chip *chip, unsigned int offse= t) +{ + unsigned long config; + int ret; + + config =3D PIN_CONFIG_LEVEL; + ret =3D pinctrl_gpio_get_config(chip, offset, &config); + if (ret) + return ret; + + return !!config; +} + +static int pin_control_gpio_set(struct gpio_chip *chip, unsigned int offse= t, + int val) +{ + unsigned long config; + + config =3D PIN_CONF_PACKED(PIN_CONFIG_LEVEL, val); + return pinctrl_gpio_set_config(chip, offset, config); +} + +static int pin_control_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pin_control_gpio_priv *priv; + struct gpio_chip *chip; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + chip =3D &priv->chip; + chip->label =3D dev_name(dev); + chip->parent =3D dev; + chip->base =3D -1; + + chip->request =3D gpiochip_generic_request; + chip->free =3D gpiochip_generic_free; + chip->get_direction =3D pin_control_gpio_get_direction; + chip->direction_input =3D pinctrl_gpio_direction_input; + chip->direction_output =3D pin_control_gpio_direction_output; + chip->get =3D pin_control_gpio_get; + chip->set =3D pin_control_gpio_set; + chip->set_config =3D gpiochip_generic_config; + + ret =3D devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id pin_control_gpio_match[] =3D { + { .compatible =3D "scmi-pinctrl-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pin_control_gpio_match); + +static struct platform_driver pin_control_gpio_driver =3D { + .probe =3D pin_control_gpio_probe, + .driver =3D { + .name =3D "pin-control-gpio", + .of_match_table =3D pin_control_gpio_match, + }, +}; +module_platform_driver(pin_control_gpio_driver); + +MODULE_AUTHOR("AKASHI Takahiro "); +MODULE_DESCRIPTION("Pinctrl based GPIO driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0