From nobody Tue Apr 7 04:45:25 2026 Received: from out198-29.us.a.mail.aliyun.com (out198-29.us.a.mail.aliyun.com [47.90.198.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C355268690 for ; Mon, 16 Mar 2026 03:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.29 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773632873; cv=none; b=EFQHCmQrRCjwXU2CCCUCZX7ttg7d49+Odsi9DG9Ac0k90XDCI4djCMhQb05gRbJIDVlgEkq4vc3eGi0PvZXFPtwJZzC9USf++UL6Vae8O3Itm5sDXrzLqmAKYuDzAZlxr8PPKdgXmM9f2TXiQw6yve4E64jIu4+OFeU6i4GNnJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773632873; c=relaxed/simple; bh=Ai+7H3+vD6vtSz9JJkEoHvvfXHoahWAthv/9WEh6V0E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ITPe85mmcreDav5c9d69gYk30R4tXAWHmSmkwG3ELIAwwXQvPDsHfAEbIQ63IzgXsPWkSneSs31Idd51kC5Kn4dEtNUa+4EazZ8j5iVWeLZAUhfdPBOmwYkz6oggFyrsJdPSfV+VaV0QSAepSUbpmmOnSVIXReZgUuTTrYnm43U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=antgroup.com; spf=pass smtp.mailfrom=antgroup.com; dkim=pass (1024-bit key) header.d=antgroup.com header.i=@antgroup.com header.b=akM1Likr; arc=none smtp.client-ip=47.90.198.29 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=antgroup.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=antgroup.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=antgroup.com header.i=@antgroup.com header.b="akM1Likr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antgroup.com; s=default; t=1773632854; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=c9/X8odBS2n9mVEmqOXdQw5uNgbPFfBggNNq8a/rnIo=; b=akM1Likrv31rVlE4zVyzj5kUlr5hMh5EYEt6QvOj4x7h+wHWOxbQdmZeCTMqeYNnIzSFnlNzJ4X+NJgelTnYs+A0zD1GqSJNv1YVhdXO6grLQoBJ39EwDuJ1QXDc7LtRsqBN99B4JA3LLrd5mMhbCnPj06J9yPzohSHE5VaSA9A= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R991e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037031241;MF=houwenlong.hwl@antgroup.com;NM=1;PH=DS;RN=47;SR=0;TI=SMTPD_---.gt2oRKf_1773632851; Received: from localhost(mailfrom:houwenlong.hwl@antgroup.com fp:SMTPD_---.gt2oRKf_1773632851 cluster:ay29) by smtp.aliyun-inc.com; Mon, 16 Mar 2026 11:47:32 +0800 From: Hou Wenlong To: linux-kernel@vger.kernel.org Cc: Hou Wenlong , Alex Deucher , Alex Hung , Alvin Lee , amd-gfx@lists.freedesktop.org, Ankit Nautiyal , Aurabindo Pillai , Ausef Yousof , Bhuvanachandra Pinninti , Chaitanya Kumar Borah , Charlene Liu , Chenyu Chen , Chris Park , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Dillon Varone , Dmytro Laktyushkin , dri-devel@lists.freedesktop.org, Gustavo Sousa , Harold Sun , Harry Wentland , intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Jun Lei , Karthi Kandasamy , Leo Chen , Leo Li , Lohita Mudimela , Lucas De Marchi , Meenakshikumar Somasundaram , Nicholas Carbones , Ray Wu , Relja Vojvodic , Rodrigo Siqueira , Rodrigo Vivi , Ryan Seto , Samson Tam , Simona Vetter , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Tvrtko Ursulin , Wayne Lin , Wenjing Liu , Yan Li , Zhenyu Wang , Zhi Wang Subject: [PATCH 1/2] drm/i915/gvt: Rename struct 'pixel_format' to 'gvt_pixel_format' Date: Mon, 16 Mar 2026 11:46:28 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the local struct 'pixel_format' to 'gvt_pixel_format' to avoid potential name conflicts with the 'pixel_format' struct defined in include/video/pixel_format.h. Signed-off-by: Hou Wenlong Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/fb_decoder.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/g= vt/fb_decoder.c index d7abf38df532..25fffc77f138 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -48,13 +48,13 @@ #include "i915_reg.h" =20 #define PRIMARY_FORMAT_NUM 16 -struct pixel_format { +struct gvt_pixel_format { int drm_format; /* Pixel format in DRM definition */ int bpp; /* Bits per pixel, 0 indicates invalid */ const char *desc; /* The description */ }; =20 -static const struct pixel_format bdw_pixel_formats[] =3D { +static const struct gvt_pixel_format bdw_pixel_formats[] =3D { {DRM_FORMAT_C8, 8, "8-bit Indexed"}, {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, @@ -67,7 +67,7 @@ static const struct pixel_format bdw_pixel_formats[] =3D { {} }; =20 -static const struct pixel_format skl_pixel_formats[] =3D { +static const struct gvt_pixel_format skl_pixel_formats[] =3D { {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"}, {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"}, {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"}, --=20 2.31.1 From nobody Tue Apr 7 04:45:25 2026 Received: from out28-2.mail.aliyun.com (out28-2.mail.aliyun.com [115.124.28.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 072522836E for ; Mon, 16 Mar 2026 03:48:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773632905; cv=none; b=eLtv2If0TEN7RY6XaQdYjNCcvxOB8c93LvIcOZOIsj8gCReyAlzIE+E6Qvwn3956zjk79SkAZcJpeUtVyVvCxwfyf3krUybrE1ZyANXTIClid6VUysVXRX2tm5xphzb95bKcHecdbVemIsSgvbjlziKP7WdwQBbwpcOaASwNZ00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773632905; c=relaxed/simple; bh=cxjvUiMepfsUhY8XLXJb2CavsAMh14SspgZ73d4+CzQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rxUy4UX3V53eeGTx8dM8H/+eqouXBePQHZR7/bTo94hOA0T2wF7714fWDSpqsFcJCqOfyO9GQuQPEprOlW9Coskkv4/Q6bMFExmnYTuxtXtJCW2Je1oSLCxBE1gyq1zgP/Y88x3XjWaIbb2yhGeIHJ3rLz8KdqnC3qGxYxWShRo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=antgroup.com; spf=pass smtp.mailfrom=antgroup.com; dkim=pass (1024-bit key) header.d=antgroup.com header.i=@antgroup.com header.b=iNlQNQ5h; arc=none smtp.client-ip=115.124.28.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=antgroup.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=antgroup.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=antgroup.com header.i=@antgroup.com header.b="iNlQNQ5h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antgroup.com; s=default; t=1773632895; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=EYW9eEgTMJ7uWMekujL7MMTcejAzJsQIxJcJx52I16g=; b=iNlQNQ5hLop0KWXwTm5Yr8QXi8U9x3sz1IJsQhyG5r56JcjZBtTFZ9mN5TTVxYQjTaNUf0XzPInzJy8VMK75/mjwnekbEEi9GNRvQSv9NKsYxJ0xOYffUu0nqjzktCwdz6w3ulsqCLy4Bjf54+qNiIQugBJKBzoyi+lAPdNO2Z4= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R921e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033032053168;MF=houwenlong.hwl@antgroup.com;NM=1;PH=DS;RN=47;SR=0;TI=SMTPD_---.gt1LISf_1773632892; Received: from localhost(mailfrom:houwenlong.hwl@antgroup.com fp:SMTPD_---.gt1LISf_1773632892 cluster:ay29) by smtp.aliyun-inc.com; Mon, 16 Mar 2026 11:48:13 +0800 From: Hou Wenlong To: linux-kernel@vger.kernel.org Cc: Hou Wenlong , Alex Deucher , Alex Hung , Alvin Lee , amd-gfx@lists.freedesktop.org, Ankit Nautiyal , Aurabindo Pillai , Ausef Yousof , Bhuvanachandra Pinninti , Chaitanya Kumar Borah , Charlene Liu , Chenyu Chen , Chris Park , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Dillon Varone , Dmytro Laktyushkin , dri-devel@lists.freedesktop.org, Gustavo Sousa , Harold Sun , Harry Wentland , intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Jun Lei , Karthi Kandasamy , Leo Chen , Leo Li , Lohita Mudimela , Lucas De Marchi , Meenakshikumar Somasundaram , Nicholas Carbones , Ray Wu , Relja Vojvodic , Rodrigo Siqueira , Rodrigo Vivi , Ryan Seto , Samson Tam , Simona Vetter , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Tvrtko Ursulin , Wayne Lin , Wenjing Liu , Yan Li , Zhenyu Wang , Zhi Wang Subject: [PATCH 2/2] drm/amd/display: Rename enum 'pixel_format' to 'dc_pixel_format' Date: Mon, 16 Mar 2026 11:46:29 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the enum 'pixel_format' to 'dc_pixel_format' to avoid potential name conflicts with the pixel_format struct defined in include/video/pixel_format.h. Signed-off-by: Hou Wenlong Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 3 ++- drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +- 7 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gp= u/drm/amd/display/dc/core/dc_resource.c index 03d125f794b0..cadc52728108 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -742,10 +742,10 @@ struct clock_source *resource_find_used_clk_src_for_s= haring( return NULL; } =20 -static enum pixel_format convert_pixel_format_to_dalsurface( +static enum dc_pixel_format convert_pixel_format_to_dalsurface( enum surface_pixel_format surface_pixel_format) { - enum pixel_format dal_pixel_format =3D PIXEL_FORMAT_UNKNOWN; + enum dc_pixel_format dal_pixel_format =3D PIXEL_FORMAT_UNKNOWN; =20 switch (surface_pixel_format) { case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm= /amd/display/dc/dc_hw_types.h index cfa569a7bff1..81d12df8f54e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -218,7 +218,7 @@ enum surface_pixel_format { =20 =20 /* Pixel format */ -enum pixel_format { +enum dc_pixel_format { /*graph*/ PIXEL_FORMAT_UNINITIALIZED, PIXEL_FORMAT_INDEX8, diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gp= u/drm/amd/display/dc/dc_spl_translate.c index 37d1a79e8241..854d50ab1a6c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -63,7 +63,8 @@ static void populate_inits_from_splinits(struct scl_inits= *inits, inits->h_c =3D dc_fixpt_from_int_dy(spl_inits->h_filter_init_int_c, spl_i= nits->h_filter_init_frac_c >> 5, 0, 19); inits->v_c =3D dc_fixpt_from_int_dy(spl_inits->v_filter_init_int_c, spl_i= nits->v_filter_init_frac_c >> 5, 0, 19); } -static void populate_splformat_from_format(enum spl_pixel_format *spl_pixe= l_format, const enum pixel_format pixel_format) +static void populate_splformat_from_format(enum spl_pixel_format *spl_pixe= l_format, + const enum dc_pixel_format pixel_format) { if (pixel_format < PIXEL_FORMAT_INVALID) *spl_pixel_format =3D (enum spl_pixel_format)pixel_format; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/dr= ivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c index 808bca9fb804..0d2c9fcd3362 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c @@ -102,7 +102,7 @@ static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_= depth depth) } } =20 -static bool dpp1_dscl_is_video_format(enum pixel_format format) +static bool dpp1_dscl_is_video_format(enum dc_pixel_format format) { if (format >=3D PIXEL_FORMAT_VIDEO_BEGIN && format <=3D PIXEL_FORMAT_VIDEO_END) @@ -111,7 +111,7 @@ static bool dpp1_dscl_is_video_format(enum pixel_format= format) return false; } =20 -static bool dpp1_dscl_is_420_format(enum pixel_format format) +static bool dpp1_dscl_is_420_format(enum dc_pixel_format format) { if (format =3D=3D PIXEL_FORMAT_420BPP8 || format =3D=3D PIXEL_FORMAT_420BPP10) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/= drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index a62c4733ed3b..e2489eaf0004 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -94,7 +94,7 @@ static int dpp401_dscl_get_pixel_depth_val(enum lb_pixel_= depth depth) } } =20 -static bool dpp401_dscl_is_video_format(enum pixel_format format) +static bool dpp401_dscl_is_video_format(enum dc_pixel_format format) { if (format >=3D PIXEL_FORMAT_VIDEO_BEGIN && format <=3D PIXEL_FORMAT_VIDEO_END) @@ -103,7 +103,7 @@ static bool dpp401_dscl_is_video_format(enum pixel_form= at format) return false; } =20 -static bool dpp401_dscl_is_420_format(enum pixel_format format) +static bool dpp401_dscl_is_420_format(enum dc_pixel_format format) { if (format =3D=3D PIXEL_FORMAT_420BPP8 || format =3D=3D PIXEL_FORMAT_420BPP10) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gp= u/drm/amd/display/dc/inc/hw/hw_shared.h index a61d12ec61bc..b4a95807b73b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -240,7 +240,7 @@ struct default_adjustment { enum dc_color_space out_color_space; enum dc_color_space in_color_space; enum dc_color_depth color_depth; - enum pixel_format surface_pixel_format; + enum dc_pixel_format surface_pixel_format; enum graphics_csc_adjust_type csc_adjust_type; bool force_hw_default; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gp= u/drm/amd/display/dc/inc/hw/transform.h index 5a1d9b708a9d..30990355985d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -160,7 +160,7 @@ struct scaler_data { struct scaling_ratios ratios; struct scl_inits inits; struct sharpness_adj sharpness; - enum pixel_format format; + enum dc_pixel_format format; struct line_buffer_params lb_params; // Below struct holds the scaler values to program hw registers struct dscl_prog_data dscl_prog_data; --=20 2.31.1