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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by MW1PEPF0001615B.mail.protection.outlook.com (10.167.249.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9700.0 via Frontend Transport; Thu, 5 Mar 2026 15:40:14 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 5 Mar 2026 09:40:06 -0600 Received: from localhost (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17 via Frontend Transport; Thu, 5 Mar 2026 09:40:05 -0600 From: Michal Simek To: , , , CC: Conor Dooley , Krzysztof Kozlowski , Michael Turquette , "Rob Herring" , Stephen Boyd , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:COMMON CLK FRAMEWORK" Subject: [PATCH 1/2] dt-bindings: clock: versal-clk: Reorder if/then conditions for Versal NET Date: Thu, 5 Mar 2026 16:39:49 +0100 Message-ID: <7241fe512ff677f7aa5b7212ae4056fba01f1f59.1772725183.git.michal.simek@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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charset="utf-8" The Versal NET clock controller compatible is specified as: compatible =3D "xlnx,versal-net-clk", "xlnx,versal-clk"; with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET. Restructure the allOf conditions to check for xlnx,versal-net-clk first. If matched, allow 3 clocks (ref, pl_alt_ref, alt_ref). Otherwise fall back to the xlnx,versal-clk case with 2 clocks (ref, pl_alt_ref). Add a dedicated example for the Versal NET 3-clock configuration and split all examples into separate blocks so each compatible variant is validated independently by dt_binding_check. Signed-off-by: Michal Simek --- .../bindings/clock/xlnx,versal-clk.yaml | 49 ++++++++++--------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b= /Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index bef109d163a8..65d926d8f464 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -51,28 +51,7 @@ allOf: properties: compatible: contains: - enum: - - xlnx,versal-clk - - then: - properties: - clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - clock-names: - items: - - const: ref - - const: pl_alt_ref - - - if: - properties: - compatible: - contains: - enum: - - xlnx,versal-net-clk - + const: xlnx,versal-net-clk then: properties: clocks: @@ -86,6 +65,23 @@ allOf: - const: ref - const: pl_alt_ref - const: alt_ref + else: + if: + properties: + compatible: + contains: + const: xlnx,versal-clk + then: + properties: + clocks: + items: + - description: reference clock + - description: alternate reference clock for programmable lo= gic + + clock-names: + items: + - const: ref + - const: pl_alt_ref =20 - if: properties: @@ -135,6 +131,15 @@ examples: }; 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charset="utf-8" Switch Versal NET from using fixed clocks (versal-net-clk.dtsi) to the firmware-based CCF clock interface (versal-net-clk-ccf.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions. Add DT macro headers for Versal NET and base Versal clocks, power domains and resets that are required by the CCF clock dtsi. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/versal-net-clk-ccf.dtsi | 378 ++++++++++++++++++ .../xilinx/versal-net-vn-x-b2197-01-revA.dts | 3 +- arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h | 123 ++++++ .../boot/dts/xilinx/xlnx-versal-net-clk.h | 78 ++++ .../boot/dts/xilinx/xlnx-versal-net-power.h | 38 ++ .../boot/dts/xilinx/xlnx-versal-net-resets.h | 53 +++ .../arm64/boot/dts/xilinx/xlnx-versal-power.h | 54 +++ .../boot/dts/xilinx/xlnx-versal-resets.h | 105 +++++ 8 files changed, 831 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h diff --git a/arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi b/arch/arm6= 4/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file mode 100644 index 000000000000..1b8c7bbbcf5c --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal with PM + * + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "xlnx-versal-net-clk.h" +#include "xlnx-versal-net-power.h" +#include "xlnx-versal-net-resets.h" + +/ { + ref_clk: ref-clk { + bootph-all; + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <33333333>; + clock-output-names =3D "ref_clk"; + }; + + rtc_clk: rtc-clk { + bootph-all; + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "rtc_clk"; + }; + + can0_clk: can0-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&versal_net_clk CAN0_REF_2X>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "can0_clk"; + }; + + can1_clk: can1-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&versal_net_clk CAN1_REF_2X>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "can1_clk"; + }; + + firmware { + versal_net_firmware: versal-net-firmware { + compatible =3D "xlnx,versal-net-firmware", "xlnx,versal-firmware"; + bootph-all; + method =3D "smc"; + #power-domain-cells =3D <1>; + + versal_net_reset: reset-controller { + compatible =3D "xlnx,versal-net-reset"; + #reset-cells =3D <1>; + }; + + versal_net_clk: clock-controller { + bootph-all; + #clock-cells =3D <1>; + compatible =3D "xlnx,versal-net-clk", "xlnx,versal-clk"; + clocks =3D <&ref_clk>, <&ref_clk>, <&ref_clk>; + clock-names =3D "ref", "pl_alt_ref", "alt_ref"; + }; + + versal_net_power: power-management { /* untested */ + compatible =3D "xlnx,zynqmp-power"; + interrupt-parent =3D <&gic>; + interrupts =3D <0 57 4>; + mboxes =3D <&ipi_mailbox_pmu1 0>, + <&ipi_mailbox_pmu1 1>; + mbox-names =3D "tx", "rx"; + }; + }; + }; + + zynqmp-ipi { + compatible =3D "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent =3D <&gic>; + interrupts =3D <0 57 4>; + xlnx,ipi-id =3D <2>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@eb3f0440 { + compatible =3D "xlnx,zynqmp-ipi-dest-mailbox"; + reg =3D <0 0xeb3f0440 0 0x20>, + <0 0xeb3f0460 0 0x20>, + <0 0xeb3f0280 0 0x20>, + <0 0xeb3f02a0 0 0x20>; + reg-names =3D "local_request_region", "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells =3D <1>; + xlnx,ipi-id =3D <1>; + }; + }; +}; + +&cpu0 { + clocks =3D <&versal_net_clk ACPU_0>; +}; + +&cpu100 { + clocks =3D <&versal_net_clk ACPU_0>; +}; + +&cpu200 { + clocks =3D <&versal_net_clk ACPU_0>; +}; + +&cpu300 { + clocks =3D <&versal_net_clk ACPU_0>; +}; + +&cpu10000 { + clocks =3D <&versal_net_clk ACPU_1>; +}; + +&cpu10100 { + clocks =3D <&versal_net_clk ACPU_1>; +}; + +&cpu10200 { + clocks =3D <&versal_net_clk ACPU_1>; +}; + +&cpu10300 { + clocks =3D <&versal_net_clk ACPU_1>; +}; + +&cpu20000 { + clocks =3D <&versal_net_clk ACPU_2>; +}; + +&cpu20100 { + clocks =3D <&versal_net_clk ACPU_2>; +}; + +&cpu20200 { + clocks =3D <&versal_net_clk ACPU_2>; +}; + +&cpu20300 { + clocks =3D <&versal_net_clk ACPU_2>; +}; + +&cpu30000 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&cpu30100 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&cpu30200 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&cpu30300 { + clocks =3D <&versal_net_clk ACPU_3>; +}; + +&can0 { + clocks =3D <&can0_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_CAN_FD_0>; +}; + +&can1 { + clocks =3D <&can1_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_CAN_FD_1>; +}; + +&gem0 { + clocks =3D <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, + <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; + power-domains =3D <&versal_net_firmware PM_DEV_GEM_0>; +}; + +&gem1 { + clocks =3D <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, + <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; + power-domains =3D <&versal_net_firmware PM_DEV_GEM_1>; +}; + +&gpio0 { + clocks =3D <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_GPIO>; +}; + +&gpio1 { + clocks =3D <&versal_net_clk PMC_LSBUS_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_GPIO_PMC>; +}; + +&i2c0 { + clocks =3D <&versal_net_clk I3C0_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_0>; +}; + +&i2c1 { + clocks =3D <&versal_net_clk I3C1_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_1>; +}; + +&i3c0 { + clocks =3D <&versal_net_clk I3C0_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_0>; +}; + +&i3c1 { + clocks =3D <&versal_net_clk I3C1_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_I2C_1>; +}; + +&adma0 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_0>; +}; + +&adma1 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_1>; +}; + +&adma2 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_2>; +}; + +&adma3 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_3>; +}; + +&adma4 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_4>; +}; + +&adma5 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_5>; +}; + +&adma6 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_6>; +}; + +&adma7 { + clocks =3D <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_ADMA_7>; +}; + +&qspi { + clocks =3D <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_QSPI>; +}; + +&ospi { + clocks =3D <&versal_net_clk OSPI_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_OSPI>; +}; + +&rtc { + clocks =3D <&rtc_clk>; + clock-names =3D "rtc"; + power-domains =3D <&versal_net_firmware PM_DEV_RTC>; +}; + +&serial0 { + clocks =3D <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_UART_0>; +}; + +&serial1 { + clocks =3D <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_UART_1>; +}; + +&sdhci0 { + clocks =3D <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_SDIO_0>; +}; + +&sdhci1 { + clocks =3D <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_SDIO_1>; +}; + +&spi0 { + clocks =3D <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_SPI_0>; +}; + +&spi1 { + clocks =3D <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains =3D <&versal_net_firmware PM_DEV_SPI_1>; +}; + +&ttc0 { + clocks =3D <&versal_net_clk TTC0>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_0>; +}; + +&ttc1 { + clocks =3D <&versal_net_clk TTC1>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_1>; +}; + +&ttc2 { + clocks =3D <&versal_net_clk TTC2>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_2>; +}; + +&ttc3 { + clocks =3D <&versal_net_clk TTC3>; + power-domains =3D <&versal_net_firmware PM_DEV_TTC_3>; +}; + +&usb0 { + clocks =3D <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_USB_0>; + resets =3D <&versal_net_reset VERSAL_RST_USB_0>; +}; + +&dwc3_0 { + clocks =3D <&versal_net_clk USB0_BUS_REF>; +}; + +&usb1 { + clocks =3D <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; + power-domains =3D <&versal_net_firmware PM_DEV_USB_1>; + resets =3D <&versal_net_reset VERSAL_RST_USB_1>; +}; + +&dwc3_1 { + clocks =3D <&versal_net_clk USB1_BUS_REF>; +}; + +&wwdt0 { + clocks =3D <&versal_net_clk FPD_WWDT0>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_0>; +}; + +&wwdt1 { + clocks =3D <&versal_net_clk FPD_WWDT1>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_1>; +}; + +&wwdt2 { + clocks =3D <&versal_net_clk FPD_WWDT2>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_2>; +}; + +&wwdt3 { + clocks =3D <&versal_net_clk FPD_WWDT3>; + power-domains =3D <&versal_net_firmware PM_DEV_FPD_SWDT_3>; +}; + +&lpd_wwdt0 { + clocks =3D <&versal_net_clk LPD_WWDT0>; + power-domains =3D <&versal_net_firmware PM_DEV_LPD_SWDT_0>; +}; + +&lpd_wwdt1 { + clocks =3D <&versal_net_clk LPD_WWDT1>; + power-domains =3D <&versal_net_firmware PM_DEV_LPD_SWDT_1>; +}; diff --git a/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts b= /arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts index 06b2301f48a0..322ef8f6340d 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts +++ b/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts @@ -11,8 +11,9 @@ /dts-v1/; =20 #include "versal-net.dtsi" -#include "versal-net-clk.dtsi" +#include "versal-net-clk-ccf.dtsi" #include +#include "xlnx-versal-net-power.h" =20 / { compatible =3D "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,v= ersal-net"; diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h b/arch/arm64/boot= /dts/xilinx/xlnx-versal-clk.h new file mode 100644 index 000000000000..264d634d226e --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_H +#define _DT_BINDINGS_CLK_VERSAL_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h b/arch/arm64/= boot/dts/xilinx/xlnx-versal-net-clk.h new file mode 100644 index 000000000000..f894d044c6f9 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_NET_H +#define _DT_BINDINGS_CLK_VERSAL_NET_H + +#include "xlnx-versal-clk.h" + +#define GEM0_REF_RX 0xA9 +#define GEM0_REF_TX 0xA8 +#define GEM1_REF_RX 0xA2 +#define GEM1_REF_TX 0xA1 +#define CAN0_REF_2X 0x9E +#define CAN1_REF_2X 0xAC +#define FPD_WWDT0 0xB5 +#define FPD_WWDT1 0xB6 +#define FPD_WWDT2 0xB7 +#define FPD_WWDT3 0xB8 +#define LPD_WWDT0 0xB9 +#define LPD_WWDT1 0xBA +#define ACPU_0 0x98 +#define ACPU_1 0x9B +#define ACPU_2 0x9A +#define ACPU_3 0x99 +#define I3C0_REF 0x9D +#define I3C1_REF 0x9F +#define USB1_BUS_REF 0xAE +#define LPD_WWDT 0xAD + +/* Remove Versal specific node IDs */ +#undef APU_PLL +#undef RPU_PLL +#undef CPM_PLL +#undef APU_PRESRC +#undef APU_POSTCLK +#undef APU_PLL_OUT +#undef APLL +#undef RPU_PRESRC +#undef RPU_POSTCLK +#undef RPU_PLL_OUT +#undef RPLL +#undef CPM_PRESRC +#undef CPM_POSTCLK +#undef CPM_PLL_OUT +#undef CPLL +#undef APLL_TO_XPD +#undef RPLL_TO_XPD +#undef RCLK_PMC +#undef RCLK_LPD +#undef WDT +#undef MUXED_IRO_DIV2 +#undef MUXED_IRO_DIV4 +#undef PSM_REF +#undef CPM_CORE_REF +#undef CPM_LSBUS_REF +#undef CPM_DBG_REF +#undef CPM_AUX0_REF +#undef CPM_AUX1_REF +#undef CPU_R5 +#undef CPU_R5_CORE +#undef CPU_R5_OCM +#undef CPU_R5_OCM2 +#undef CAN0_REF +#undef CAN1_REF +#undef I2C0_REF +#undef I2C1_REF +#undef CPM_TOPSW_REF +#undef USB3_DUAL_REF +#undef MUXED_IRO +#undef PL_EXT +#undef PL_LB +#undef MIO_50_OR_51 +#undef MIO_24_OR_25 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h b/arch/arm6= 4/boot/dts/xilinx/xlnx-versal-net-power.h new file mode 100644 index 000000000000..34f99695655d --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H +#define _DT_BINDINGS_VERSAL_NET_POWER_H + +#include "xlnx-versal-power.h" + +#define PM_DEV_USB_1 (0x182240D7U) +#define PM_DEV_FPD_SWDT_0 (0x182240DBU) +#define PM_DEV_FPD_SWDT_1 (0x182240DCU) +#define PM_DEV_FPD_SWDT_2 (0x182240DDU) +#define PM_DEV_FPD_SWDT_3 (0x182240DEU) +#define PM_DEV_TCM_A_0A (0x183180CBU) +#define PM_DEV_TCM_A_0B (0x183180CCU) +#define PM_DEV_TCM_A_0C (0x183180CDU) +#define PM_DEV_RPU_A_0 (0x181100BFU) +#define PM_DEV_LPD_SWDT_0 (0x182240D9U) +#define PM_DEV_LPD_SWDT_1 (0x182240DAU) + +/* Remove Versal specific node IDs */ +#undef PM_DEV_RPU0_0 +#undef PM_DEV_RPU0_1 +#undef PM_DEV_OCM_0 +#undef PM_DEV_OCM_1 +#undef PM_DEV_OCM_2 +#undef PM_DEV_OCM_3 +#undef PM_DEV_TCM_0_A +#undef PM_DEV_TCM_1_A +#undef PM_DEV_TCM_0_B +#undef PM_DEV_TCM_1_B +#undef PM_DEV_SWDT_FPD +#undef PM_DEV_AI + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h b/arch/arm= 64/boot/dts/xilinx/xlnx-versal-net-resets.h new file mode 100644 index 000000000000..b26ad78f6dc8 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H +#define _DT_BINDINGS_VERSAL_NET_RESETS_H + +#include "xlnx-versal-resets.h" + +#define VERSAL_RST_USB_1 (0xC1040C6U) + +/* Remove Versal specific reset IDs */ +#undef VERSAL_RST_ACPU_0_POR +#undef VERSAL_RST_ACPU_1_POR +#undef VERSAL_RST_OCM2_POR +#undef VERSAL_RST_APU +#undef VERSAL_RST_ACPU_0 +#undef VERSAL_RST_ACPU_1 +#undef VERSAL_RST_ACPU_L2 +#undef VERSAL_RST_RPU_ISLAND +#undef VERSAL_RST_RPU_AMBA +#undef VERSAL_RST_R5_0 +#undef VERSAL_RST_R5_1 +#undef VERSAL_RST_OCM2_RST +#undef VERSAL_RST_I2C_PMC +#undef VERSAL_RST_I2C_0 +#undef VERSAL_RST_I2C_1 +#undef VERSAL_RST_SWDT_FPD +#undef VERSAL_RST_SWDT_LPD +#undef VERSAL_RST_USB +#undef VERSAL_RST_DPC +#undef VERSAL_RST_DBG_TRACE +#undef VERSAL_RST_DBG_TSTMP +#undef VERSAL_RST_RPU0_DBG +#undef VERSAL_RST_RPU1_DBG +#undef VERSAL_RST_HSDP +#undef VERSAL_RST_CPMDBG +#undef VERSAL_RST_PCIE_CFG +#undef VERSAL_RST_PCIE_CORE0 +#undef VERSAL_RST_PCIE_CORE1 +#undef VERSAL_RST_PCIE_DMA +#undef VERSAL_RST_L2_0 +#undef VERSAL_RST_L2_1 +#undef VERSAL_RST_ADDR_REMAP +#undef VERSAL_RST_CPI0 +#undef VERSAL_RST_CPI1 +#undef VERSAL_RST_XRAM +#undef VERSAL_RST_AIE_ARRAY +#undef VERSAL_RST_AIE_SHIM + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h b/arch/arm64/bo= ot/dts/xilinx/xlnx-versal-power.h new file mode 100644 index 000000000000..7db3969a4277 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2021 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_POWER_H +#define _DT_BINDINGS_VERSAL_POWER_H + +#define PM_DEV_RPU0_0 (0x18110005U) +#define PM_DEV_RPU0_1 (0x18110006U) +#define PM_DEV_OCM_0 (0x18314007U) +#define PM_DEV_OCM_1 (0x18314008U) +#define PM_DEV_OCM_2 (0x18314009U) +#define PM_DEV_OCM_3 (0x1831400aU) +#define PM_DEV_TCM_0_A (0x1831800bU) +#define PM_DEV_TCM_0_B (0x1831800cU) +#define PM_DEV_TCM_1_A (0x1831800dU) +#define PM_DEV_TCM_1_B (0x1831800eU) +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_LPD (0x18224028U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_I2C_PMC (0x1822402dU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h b/arch/arm64/b= oot/dts/xilinx/xlnx-versal-resets.h new file mode 100644 index 000000000000..895424e9b0e5 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_RESETS_H +#define _DT_BINDINGS_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif --=20 2.43.0