From nobody Wed Apr 15 12:40:45 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CB9823C39A; Wed, 4 Mar 2026 00:19:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772583586; cv=none; b=uBK7eK7NNHyMtvH4LJ+mYGwNZPUJlo7VVt4dH7qBT+6kMMiq04lBlZuAVVfivAo1OZ8HkDcIP02Xk4lJCa+pCR3mEucF6r55yIkMRMRkx8ZWQ9lnX9Dx2FdWflUkqJy2n7WeVWTWUhw7R7Khw++EPezhi+vjtm8Z2Eo/pCQJLeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772583586; c=relaxed/simple; bh=nxf43kamxazjMsxMuuiU2UtYRi3XjR/XIy+ZjiDgMPg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WltRgaBQdBcXrnYUcCjDNQPWWE6I5BEC2rIUuS5dRytQbNABUQYqqjg2Oek5bS4eVxwexNgucPyLBBQ/7KyTd6piFMyPO26+UEMtJCRguuNOQ+FDv9V2eYTxmfowF+Fmagn7n5ObhA3Ku+WeodyGZcewpfA5pfa4GouHQF4Cd+8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A7RI3dMr; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A7RI3dMr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772583585; x=1804119585; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nxf43kamxazjMsxMuuiU2UtYRi3XjR/XIy+ZjiDgMPg=; b=A7RI3dMr3GWkQmRFK/GZLHKprT0RFet+nOZZ+YDl8e1s7a++KHO40XTl FF1O0vzC5GelqDQr46A/bed8NyIefyeeUYpztskmGBdNhXeyvP/+awSyA BEWtL+Y5jOwhFZ55cxXAM1eIhm2sbaj0YWEOovviZhHhbOToSmmPloCGN 0sjbbM8QEsY4qxD1OD4NoE4+Mw4r5cIfNvCv3ppkc7eAep6IMzrVPZg3W d+pNTQIpJ1+CwBAkJDwZCmSryRihpXUNpn3Xe5X6F3L7pz+erqitnWWKZ 3kznKD8LxheWucNBdLzrqqJ+paEFYMkxZqevrmopyN+mHMgZxlyAeN/ti g==; X-CSE-ConnectionGUID: dsx2CLT4RiajryVfJ49YTg== X-CSE-MsgGUID: OiQ6GwJHQnWpDyCkK6Horw== X-IronPort-AV: E=McAfee;i="6800,10657,11718"; a="73544996" X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="73544996" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:44 -0800 X-CSE-ConnectionGUID: l0BkX0olSI2PVg6Pm+IXgA== X-CSE-MsgGUID: f5sCj29FTBK0lIcHNmS7Jg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="218120384" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:44 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 1/9] selftests/resctrl: Improve accuracy of cache occupancy test Date: Tue, 3 Mar 2026 16:19:30 -0800 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dave Martin reported inconsistent CMT test failures. In one experiment the first run of the CMT test failed because of too large (24%) difference between measured and achievable cache occupancy while the second run passed with an acceptable 4% difference. The CMT test is susceptible to interference from the rest of the system. This can be demonstrated with a utility like stress-ng by running the CMT test while introducing cache misses using: stress-ng --matrix-3d 0 --matrix-3d-zyx Below shows an example of the CMT test failing because of a significant difference between measured and achievable cache occupancy when run with interference: # Starting CMT test ... # Mounting resctrl to "/sys/fs/resctrl" # Cache size :56623104 # Writing benchmark parameters to resctrl FS # Benchmark PID: 3275 # Checking for pass/fail # Fail: Check cache miss rate within 15% # Percent diff=3D97 # Number of bits: 5 # Average LLC val: 501350 # Cache span (bytes): 23592960 not ok 1 CMT: test The CMT test creates a new control group that is also capable of monitoring and assigns the workload to it. The workload allocates a buffer that by default fills a portion of the L3 and keeps reading from the buffer, measuring the L3 occupancy at intervals. The test passes if the workload's L3 occupancy is within 15% of the buffer size. By not adjusting any capacity bitmasks the workload shares the cache with the rest of the system. Any other task that may be running could evict the workload's data from the cache causing it to have low cache occupancy. Reduce interference from the rest of the system by ensuring that the workload's control group uses the capacity bitmask found in the user parameters for L3 and that the rest of the system can only allocate into the inverse of the workload's L3 cache portion. Other tasks can thus no longer evict the workload's data from L3. Take the L2 cache into account to further improve test accuracy. By default the buffer size is the same as the L3 portion that the workload can allocate into. This buffer size does not take into account that some of the workload's data may land in L2/L1. Address this in two ways: - Reduce the amount of L2 cache the workload can allocate into to the minimum on systems that support L2 cache allocation. - Increase the buffer size to accommodate data that may be allocated into the L2 cache. Use a buffer size double the L3 portion to keep using the L3 portion size as goal for L3 occupancy while taking into account that some of the data may be in L2. With the above adjustments the CMT test is more consistent. Repeating the CMT test while generating interference with stress-ng on a sample system after applying the fixes show significant improvement in test accuracy: # Starting CMT test ... # Mounting resctrl to "/sys/fs/resctrl" # Cache size :56623104 # Writing benchmark parameters to resctrl FS # Write schema "L3:0=3Dfe0" to resctrl FS # Write schema "L3:0=3D1f" to resctrl FS # Benchmark PID: 3223 # Checking for pass/fail # Pass: Check cache miss rate within 15% # Percent diff=3D3 # Number of bits: 5 # Average LLC val: 22811443 # Cache span (bytes): 23592960 ok 1 CMT: test Reported-by: Dave Martin Closes: https://lore.kernel.org/lkml/aO+7MeSMV29VdbQs@e133380.arm.com/ Signed-off-by: Reinette Chatre Tested-by: Chen Yu --- Changes since v1: - Fix typo in changelog: "data my be in L2" -> "data may be in L2". --- tools/testing/selftests/resctrl/cmt_test.c | 35 ++++++++++++++++--- tools/testing/selftests/resctrl/mba_test.c | 4 ++- tools/testing/selftests/resctrl/mbm_test.c | 4 ++- tools/testing/selftests/resctrl/resctrl.h | 4 ++- tools/testing/selftests/resctrl/resctrl_val.c | 2 +- 5 files changed, 41 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/resctrl/cmt_test.c b/tools/testing/sel= ftests/resctrl/cmt_test.c index d09e693dc739..44e9938dfafd 100644 --- a/tools/testing/selftests/resctrl/cmt_test.c +++ b/tools/testing/selftests/resctrl/cmt_test.c @@ -19,12 +19,39 @@ #define CON_MON_LCC_OCCUP_PATH \ "%s/%s/mon_data/mon_L3_%02d/llc_occupancy" =20 -static int cmt_init(const struct resctrl_val_param *param, int domain_id) +/* + * Initialize capacity bitmasks (CBMs) for control group being tested, + * default resource group to prevent its tasks from interfering with test, + * and L2 resource of control group to minimize allocations into L2 if + * possible to better predict L3 occupancy. + */ +static int cmt_init(const struct resctrl_test *test, + const struct user_params *uparams, + const struct resctrl_val_param *param, int domain_id) { + unsigned long long_mask; + char schemata[64]; + int ret; + sprintf(llc_occup_path, CON_MON_LCC_OCCUP_PATH, RESCTRL_PATH, param->ctrlgrp, domain_id); =20 - return 0; + ret =3D get_full_cbm(test->resource, &long_mask); + if (ret) + return ret; + + snprintf(schemata, sizeof(schemata), "%lx", ~param->mask & long_mask); + ret =3D write_schemata("", schemata, uparams->cpu, test->resource); + if (ret) + return ret; + + snprintf(schemata, sizeof(schemata), "%lx", param->mask); + ret =3D write_schemata(param->ctrlgrp, schemata, uparams->cpu, test->reso= urce); + + if (!ret && !strcmp(test->resource, "L3") && resctrl_resource_exists("L2"= )) + ret =3D write_schemata(param->ctrlgrp, "0x1", uparams->cpu, "L2"); + + return ret; } =20 static int cmt_setup(const struct resctrl_test *test, @@ -153,11 +180,11 @@ static int cmt_run_test(const struct resctrl_test *te= st, const struct user_param span =3D cache_portion_size(cache_total_size, param.mask, long_mask); =20 if (uparams->fill_buf) { - fill_buf.buf_size =3D span; + fill_buf.buf_size =3D span * 2; fill_buf.memflush =3D uparams->fill_buf->memflush; param.fill_buf =3D &fill_buf; } else if (!uparams->benchmark_cmd[0]) { - fill_buf.buf_size =3D span; + fill_buf.buf_size =3D span * 2; fill_buf.memflush =3D true; param.fill_buf =3D &fill_buf; } diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index c7e9adc0368f..cd4c715b7ffd 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -17,7 +17,9 @@ #define ALLOCATION_MIN 10 #define ALLOCATION_STEP 10 =20 -static int mba_init(const struct resctrl_val_param *param, int domain_id) +static int mba_init(const struct resctrl_test *test, + const struct user_params *uparams, + const struct resctrl_val_param *param, int domain_id) { int ret; =20 diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index 84d8bc250539..58201f844740 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -83,7 +83,9 @@ static int check_results(size_t span) return ret; } =20 -static int mbm_init(const struct resctrl_val_param *param, int domain_id) +static int mbm_init(const struct resctrl_test *test, + const struct user_params *uparams, + const struct resctrl_val_param *param, int domain_id) { int ret; =20 diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index afe635b6e48d..c72045c74ac4 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -135,7 +135,9 @@ struct resctrl_val_param { char filename[64]; unsigned long mask; int num_of_runs; - int (*init)(const struct resctrl_val_param *param, + int (*init)(const struct resctrl_test *test, + const struct user_params *uparams, + const struct resctrl_val_param *param, int domain_id); int (*setup)(const struct resctrl_test *test, const struct user_params *uparams, diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 7c08e936572d..a5a8badb83d4 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -569,7 +569,7 @@ int resctrl_val(const struct resctrl_test *test, goto reset_affinity; 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03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 2/9] selftests/resctrl: Do not store iMC counter value in counter config structure Date: Tue, 3 Mar 2026 16:19:31 -0800 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MBM and MBA tests compare MBM memory bandwidth measurements against the memory bandwidth event values obtained from each memory controller's PMU. The memory bandwidth event settings are discovered from the memory controller details found in /sys/bus/event_source/devices/uncore_imc_N and stored in struct imc_counter_config. In addition to event settings struct imc_counter_config contains imc_counter_config::return_value in which the associated event value is stored on every read. The event value is consumed and immediately recorded at regular intervals. The stored value is never consumed afterwards, making its storage as part of event configuration unnecessary. Remove the return_value member from struct imc_counter_config. Instead just use a local variable for use during event reading. Signed-off-by: Reinette Chatre Reviewed-by: Ilpo J=C3=A4rvinen Tested-by: Chen Yu --- tools/testing/selftests/resctrl/resctrl_val.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index a5a8badb83d4..2cc22f61a1f8 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -32,7 +32,6 @@ struct imc_counter_config { __u64 event; __u64 umask; struct perf_event_attr pe; - struct membw_read_format return_value; int fd; }; =20 @@ -312,23 +311,23 @@ static int get_read_mem_bw_imc(float *bw_imc) * Take overflow into consideration before calculating total bandwidth. */ for (imc =3D 0; imc < imcs; imc++) { + struct membw_read_format return_value; struct imc_counter_config *r =3D &imc_counters_config[imc]; =20 - if (read(r->fd, &r->return_value, - sizeof(struct membw_read_format)) =3D=3D -1) { + if (read(r->fd, &return_value, sizeof(return_value)) =3D=3D -1) { ksft_perror("Couldn't get read bandwidth through iMC"); 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d="scan'208";a="218120391" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 3/9] selftests/resctrl: Prepare for parsing multiple events per iMC Date: Tue, 3 Mar 2026 16:19:32 -0800 Message-ID: <14c1a6e0dfc6a287851de00becc41d67983a4c9a.1772582958.git.reinette.chatre@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The events needed to read memory bandwidth are discovered by iterating over every memory controller (iMC) within /sys/bus/event_source/devices. Each iMC's PMU is assumed to have one event to measure read memory bandwidth that is represented by the sysfs cas_count_read file. The event's configuration is read from "cas_count_read" and stored as an element of imc_counters_config[] by read_from_imc_dir() that receives the index of the array where to store the configuration as argument. It is possible that an iMC's PMU may have more than one event that should be used to measure memory bandwidth. Change semantics to not provide the index of the array to read_from_imc_dir() but instead a pointer to the index. This enables read_from_imc_dir() to store configurations for more than one event by incrementing the index to imc_counters_config[] itself. Ensure that the same type is consistently used for the index as it is passed around during counter configuration. Signed-off-by: Reinette Chatre Reviewed-by: Zide Chen Tested-by: Chen Yu --- Changes since v1: - Add Zide Chen's RB tag. --- tools/testing/selftests/resctrl/resctrl_val.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 2cc22f61a1f8..25c8101631e0 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -73,7 +73,7 @@ static void read_mem_bw_ioctl_perf_event_ioc_disable(int = i) * @cas_count_cfg: Config * @count: iMC number */ -static void get_read_event_and_umask(char *cas_count_cfg, int count) +static void get_read_event_and_umask(char *cas_count_cfg, unsigned int cou= nt) { char *token[MAX_TOKENS]; int i =3D 0; @@ -110,7 +110,7 @@ static int open_perf_read_event(int i, int cpu_no) } =20 /* Get type and config of an iMC counter's read event. */ -static int read_from_imc_dir(char *imc_dir, int count) +static int read_from_imc_dir(char *imc_dir, unsigned int *count) { char cas_count_cfg[1024], imc_counter_cfg[1024], imc_counter_type[1024]; FILE *fp; @@ -123,7 +123,7 @@ static int read_from_imc_dir(char *imc_dir, int count) =20 return -1; } - if (fscanf(fp, "%u", &imc_counters_config[count].type) <=3D 0) { + if (fscanf(fp, "%u", &imc_counters_config[*count].type) <=3D 0) { ksft_perror("Could not get iMC type"); fclose(fp); =20 @@ -147,7 +147,8 @@ static int read_from_imc_dir(char *imc_dir, int count) } fclose(fp); =20 - get_read_event_and_umask(cas_count_cfg, count); + get_read_event_and_umask(cas_count_cfg, *count); + *count +=3D 1; =20 return 0; } @@ -196,13 +197,12 @@ static int num_of_imcs(void) if (temp[0] >=3D '0' && temp[0] <=3D '9') { sprintf(imc_dir, "%s/%s/", DYN_PMU_PATH, ep->d_name); - ret =3D read_from_imc_dir(imc_dir, count); + ret =3D read_from_imc_dir(imc_dir, &count); if (ret) { closedir(dp); =20 return ret; } - count++; } } closedir(dp); --=20 2.50.1 From nobody Wed Apr 15 12:40:45 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBE172E8DEB; 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a="73545022" X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="73545022" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 X-CSE-ConnectionGUID: 2Vbwq8QaRwWduQc1VFGVLQ== X-CSE-MsgGUID: ic75MViWR76SsKgaC1oZrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="218120394" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 4/9] selftests/resctrl: Support multiple events associated with iMC Date: Tue, 3 Mar 2026 16:19:33 -0800 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resctrl selftests discover needed parameters to perf_event_open() via sysfs. The PMU associated with every memory controller (iMC) is discovered via the /sys/bus/event_source/devices/uncore_imc_N/type file while the read memory bandwidth event type and umask is discovered via /sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read. Newer systems may have multiple events that expose read memory bandwidth. For example, /sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read_sch0 /sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read_sch1 Support parsing of iMC PMU properties when the PMU may have multiple events to measure read memory bandwidth. The PMU only needs to be discovered once. Split the parsing of event details from actual PMU discovery in order to loop over all events associated with the PMU. Match all events with the cas_count_read prefix instead of requiring there to be one file with that name. Make the parsing code more robust. With strings passed around to create needed paths, use snprintf() instead of sprintf() to ensure there is always enough space to create the path. Ensure there is enough room in imc_counters_config[] before attempting to add an entry. Signed-off-by: Reinette Chatre Reviewed-by: Zide Chen Tested-by: Chen Yu --- Changes since v1: - Add Zide Chen's RB tag. --- tools/testing/selftests/resctrl/resctrl_val.c | 112 ++++++++++++++---- 1 file changed, 90 insertions(+), 22 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 25c8101631e0..7aae0cc5aee9 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -11,10 +11,10 @@ #include "resctrl.h" =20 #define UNCORE_IMC "uncore_imc" -#define READ_FILE_NAME "events/cas_count_read" +#define READ_FILE_NAME "cas_count_read" #define DYN_PMU_PATH "/sys/bus/event_source/devices" #define SCALE 0.00006103515625 -#define MAX_IMCS 20 +#define MAX_IMCS 40 #define MAX_TOKENS 5 =20 #define CON_MBM_LOCAL_BYTES_PATH \ @@ -109,21 +109,102 @@ static int open_perf_read_event(int i, int cpu_no) return 0; } =20 +static int parse_imc_read_bw_events(char *imc_dir, unsigned int type, + unsigned int *count) +{ + char imc_events[1024], imc_counter_cfg[1024], cas_count_cfg[1024]; + unsigned int org_count =3D *count; + struct dirent *ep; + int path_len; + int ret =3D -1; + FILE *fp; + DIR *dp; + + path_len =3D snprintf(imc_events, sizeof(imc_events), "%sevents", imc_dir= ); + if (path_len >=3D sizeof(imc_events)) { + ksft_print_msg("Unable to create path to %sevents\n", imc_dir); + return -1; + } + dp =3D opendir(imc_events); + if (dp) { + while ((ep =3D readdir(dp))) { + /* + * Parse all event files with READ_FILE_NAME + * prefix that contain the event number and umask. + * Skip files containing "." that contain unused + * properties of event. + */ + if (!strstr(ep->d_name, READ_FILE_NAME) || + strchr(ep->d_name, '.')) + continue; + + path_len =3D snprintf(imc_counter_cfg, sizeof(imc_counter_cfg), + "%s/%s", imc_events, ep->d_name); + if (path_len >=3D sizeof(imc_counter_cfg)) { + ksft_print_msg("Unable to create path to %s/%s\n", + imc_events, ep->d_name); + goto out_close; + } + fp =3D fopen(imc_counter_cfg, "r"); + if (!fp) { + ksft_perror("Failed to open iMC config file"); + goto out_close; + } + if (fscanf(fp, "%1023s", cas_count_cfg) <=3D 0) { + ksft_perror("Could not get iMC cas count read"); + fclose(fp); + goto out_close; + } + fclose(fp); + if (*count >=3D MAX_IMCS) { + ksft_print_msg("Maximum iMC count exceeded\n"); + goto out_close; + } + + imc_counters_config[*count].type =3D type; + get_read_event_and_umask(cas_count_cfg, *count); + /* Do not fail after incrementing *count. */ + *count +=3D 1; + } + if (*count =3D=3D org_count) { + ksft_print_msg("Unable to find events in %s\n", imc_events); + goto out_close; + } + } else { + ksft_perror("Unable to open PMU events directory"); + goto out; + } + ret =3D 0; +out_close: + closedir(dp); +out: + return ret; +} + /* Get type and config of an iMC counter's read event. */ static int read_from_imc_dir(char *imc_dir, unsigned int *count) { - char cas_count_cfg[1024], imc_counter_cfg[1024], imc_counter_type[1024]; + char imc_counter_type[1024]; + unsigned int type; + int path_len; FILE *fp; + int ret; =20 /* Get type of iMC counter */ - sprintf(imc_counter_type, "%s%s", imc_dir, "type"); + path_len =3D snprintf(imc_counter_type, sizeof(imc_counter_type), + "%s%s", imc_dir, "type"); + if (path_len >=3D sizeof(imc_counter_type)) { + ksft_print_msg("Unable to create path to %s%s\n", + imc_dir, "type"); + return -1; + } fp =3D fopen(imc_counter_type, "r"); if (!fp) { ksft_perror("Failed to open iMC counter type file"); =20 return -1; } - if (fscanf(fp, "%u", &imc_counters_config[*count].type) <=3D 0) { + if (fscanf(fp, "%u", &type) <=3D 0) { ksft_perror("Could not get iMC type"); fclose(fp); =20 @@ -131,24 +212,11 @@ static int read_from_imc_dir(char *imc_dir, unsigned = int *count) } fclose(fp); =20 - /* Get read config */ - sprintf(imc_counter_cfg, "%s%s", imc_dir, READ_FILE_NAME); - fp =3D fopen(imc_counter_cfg, "r"); - if (!fp) { - ksft_perror("Failed to open iMC config file"); - - return -1; - } - if (fscanf(fp, "%1023s", cas_count_cfg) <=3D 0) { - ksft_perror("Could not get iMC cas count read"); - fclose(fp); - - return -1; + ret =3D parse_imc_read_bw_events(imc_dir, type, count); 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03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 5/9] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Date: Tue, 3 Mar 2026 16:19:34 -0800 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Errata for Sierra Forest [1] (SRF42) and Granite Rapids[2] (GNR12) describe the problem that MBM on Intel RDT may overcount memory bandwidth measurements. The resctrl tests compare memory bandwidth reported by iMC PMU to that reported by MBM causing the tests to fail on these systems depending on the settings of the platform related to the errata. Since the resctrl tests need to run under various conditions it is not possible to ensure system settings are such that MBM will not overcount. It has been observed that the overcounting can be controlled via the buffer size used in the MBM and MBA tests that rely on comparisons between iMC PMU and MBM measurements. Running the MBM test on affected platforms with different buffer sizes it can be observed that the difference between iMC PMU and MBM counts reduce as the buffer size increases. After increasing the buffer size to more than 4X the differences between iMC PMU and MBM become insignificant. Increase the buffer size used in MBM and MBA tests to 4X L3 size to reduce possibility of tests failing due to difference in counts reported by iMC PMU and MBM. Signed-off-by: Reinette Chatre Link: https://edc.intel.com/content/www/us/en/design/products-and-solutions= /processors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-co= res-specification-update/errata-details/ # [1] Link: https://edc.intel.com/content/www/us/en/design/products-and-solutions= /processors-and-chipsets/birch-stream/xeon-6900-6700-6500-series-processors= -with-p-cores-specification-update/011US/errata-details/ # [2] Tested-by: Chen Yu --- tools/testing/selftests/resctrl/fill_buf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/sel= ftests/resctrl/fill_buf.c index 19a01a52dc1a..b9fa7968cd6e 100644 --- a/tools/testing/selftests/resctrl/fill_buf.c +++ b/tools/testing/selftests/resctrl/fill_buf.c @@ -139,6 +139,6 @@ ssize_t get_fill_buf_size(int cpu_no, const char *cache= _type) if (ret) return ret; =20 - return cache_total_size * 2 > MINIMUM_SPAN ? - cache_total_size * 2 : MINIMUM_SPAN; + return cache_total_size * 4 > MINIMUM_SPAN ? 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This is needed because MBM and the PMUs do not have an identical view of memory bandwidth since PMUs can count all memory traffic while MBM does not count "overhead" (for example RAS) traffic that cannot be attributed to an RMID. As a ratio this difference in view of memory bandwidth is pronounced at low memory bandwidths. The 750MiB threshold was chosen arbitrarily after comparisons on different platforms. Exposed to more platforms after introduction this threshold has proven to be inadequate. Having accurate comparison between performance counters and MBM requires careful management of system load as well as control of features that introduce extra memory traffic, for example, patrol scrub. This is not appropriate for the resctrl selftests that are intended to run on a variety of systems with various configurations. Increase the memory bandwidth threshold under which no comparison is made between performance counters and MBM. Add additional leniency by increasing the percentage of difference that will be tolerated between these counts. There is no impact to the validity of the resctrl selftests results as a measure of resctrl subsystem health. Signed-off-by: Reinette Chatre Tested-by: Chen Yu --- tools/testing/selftests/resctrl/mba_test.c | 2 +- tools/testing/selftests/resctrl/mbm_test.c | 2 +- tools/testing/selftests/resctrl/resctrl.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index cd4c715b7ffd..39cee9898359 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -12,7 +12,7 @@ =20 #define RESULT_FILE_NAME "result_mba" #define NUM_OF_RUNS 5 -#define MAX_DIFF_PERCENT 8 +#define MAX_DIFF_PERCENT 15 #define ALLOCATION_MAX 100 #define ALLOCATION_MIN 10 #define ALLOCATION_STEP 10 diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index 58201f844740..6dbbc3b76003 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -11,7 +11,7 @@ #include "resctrl.h" =20 #define RESULT_FILE_NAME "result_mbm" -#define MAX_DIFF_PERCENT 8 +#define MAX_DIFF_PERCENT 15 #define NUM_OF_RUNS 5 =20 static int diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index c72045c74ac4..861bf25f2f28 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -55,7 +55,7 @@ * and MBM respectively, for instance generating "overhead" traffic which * is not counted against any specific RMID. */ -#define THROTTLE_THRESHOLD 750 +#define THROTTLE_THRESHOLD 2500 =20 /* * fill_buf_param: "fill_buf" benchmark parameters --=20 2.50.1 From nobody Wed Apr 15 12:40:45 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 623522F60B2; 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a="73545042" X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="73545042" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 X-CSE-ConnectionGUID: JbREEryDRQWFXWmRPcn5eg== X-CSE-MsgGUID: PHjZHtpCTuuulGxUrxOgRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="218120403" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 7/9] selftests/resctrl: Remove requirement on cache miss rate Date: Tue, 3 Mar 2026 16:19:36 -0800 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the CAT test reads the same buffer into different sized cache portions it compares the number of cache misses against an expected percentage based on the size of the cache portion. Systems and test conditions vary. The CAT test is a test of resctrl subsystem health and not a test of the hardware architecture so it is not required to place requirements on the size of the difference in cache misses, just that the number of cache misses when reading a buffer increase as the cache portion used for the buffer decreases. Remove additional constraint on how big the difference between cache misses should be as the cache portion size changes. Only test that the cache misses increase as the cache portion size decreases. This remains a good sanity check of resctrl subsystem health while reducing impact of hardware architectural differences and the various conditions under which the test may run. Increase the size difference between cache portions to additionally avoid any consequences resulting from smaller increments. Signed-off-by: Reinette Chatre Tested-by: Chen Yu --- tools/testing/selftests/resctrl/cat_test.c | 33 ++++------------------ 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index f00b622c1460..8bc47f06679a 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -14,42 +14,20 @@ #define RESULT_FILE_NAME "result_cat" #define NUM_OF_RUNS 5 =20 -/* - * Minimum difference in LLC misses between a test with n+1 bits CBM to the - * test with n bits is MIN_DIFF_PERCENT_PER_BIT * (n - 1). With e.g. 5 vs 4 - * bits in the CBM mask, the minimum difference must be at least - * MIN_DIFF_PERCENT_PER_BIT * (4 - 1) =3D 3 percent. - * - * The relationship between number of used CBM bits and difference in LLC - * misses is not expected to be linear. With a small number of bits, the - * margin is smaller than with larger number of bits. For selftest purpose= s, - * however, linear approach is enough because ultimately only pass/fail - * decision has to be made and distinction between strong and stronger - * signal is irrelevant. - */ -#define MIN_DIFF_PERCENT_PER_BIT 1UL - static int show_results_info(__u64 sum_llc_val, int no_of_bits, unsigned long cache_span, - unsigned long min_diff_percent, unsigned long num_of_runs, bool platform, __s64 *prev_avg_llc_val) { __u64 avg_llc_val =3D 0; - float avg_diff; int ret =3D 0; =20 avg_llc_val =3D sum_llc_val / num_of_runs; if (*prev_avg_llc_val) { - float delta =3D (__s64)(avg_llc_val - *prev_avg_llc_val); - - avg_diff =3D delta / *prev_avg_llc_val; - ret =3D platform && (avg_diff * 100) < (float)min_diff_percent; - - ksft_print_msg("%s Check cache miss rate changed more than %.1f%%\n", - ret ? "Fail:" : "Pass:", (float)min_diff_percent); + ret =3D platform && (avg_llc_val < *prev_avg_llc_val); =20 - ksft_print_msg("Percent diff=3D%.1f\n", avg_diff * 100); + ksft_print_msg("%s Check cache miss rate increased\n", + ret ? "Fail:" : "Pass:"); } *prev_avg_llc_val =3D avg_llc_val; =20 @@ -58,10 +36,10 @@ static int show_results_info(__u64 sum_llc_val, int no_= of_bits, return ret; } =20 -/* Remove the highest bit from CBM */ +/* Remove the highest bits from CBM */ static unsigned long next_mask(unsigned long current_mask) { - return current_mask & (current_mask >> 1); + return current_mask & (current_mask >> 2); } =20 static int check_results(struct resctrl_val_param *param, const char *cach= e_type, @@ -112,7 +90,6 @@ static int check_results(struct resctrl_val_param *param= , const char *cache_type =20 ret =3D show_results_info(sum_llc_perf_miss, bits, alloc_size / 64, - MIN_DIFF_PERCENT_PER_BIT * (bits - 1), runs, get_vendor() =3D=3D ARCH_INTEL, &prev_avg_llc_val); if (ret) --=20 2.50.1 From nobody Wed Apr 15 12:40:45 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8CA72F6565; Wed, 4 Mar 2026 00:19:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772583592; cv=none; b=CEGfplKjnq6uYS/kxbrqe9KVRCE3vKMPLmiLx1JVykfMjpvhwIou1CiXzMpAQR/H6MicjpuZFKYrgXjj7At5cfiSn1Gkg3gn6b5vtEWCJ2Ag2TfQT5eBLuZ6nTwkIfsi40PEEej8S0180Mh74n1yX921MKT1yc0NbDjdBj6br7o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772583592; c=relaxed/simple; bh=cBIUYkcTaLcFGaaS2gjR42fcrLXFw9Kcvy5bKM/KiC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mtv5fiDFyEsnDL5TOrYHGJ0KJcMKbkUIkaulNW/K43SdflkapTFdMmeVQrEu5FmhDu/wwCw3iUJ0WXm8+jCMjY08lq7Zv9vjSHomXUmKKiSogN/TnYEb/I0ANUI/qO6ajy+mbj43hVnIbx61jBuu/2laExb4E3N/a8766epq1ik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=USuBSJX+; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="USuBSJX+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772583591; x=1804119591; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cBIUYkcTaLcFGaaS2gjR42fcrLXFw9Kcvy5bKM/KiC8=; b=USuBSJX+tjXxqW/CSwHtJtA7uAgP+L+sg5mconBqnNUrJp7P8f64MEZx hqYymAGe5lZInZLJyU7Fv4OUtbN9h2T3UTKzdK+D/uczI1WRukL/n7Y6X 5xA0T3cXk+LqX+zpqHT8AafteuL0i41BrcoGEz6g37oAaRPdw9/RyQz4k KHw6iVQDW14Yr+ZiPDzajv811NBE8R+24IigQ7fFxcbGYbdiChGrabUeR zSg4hyE4unUGylf5K7Wld7giT2fP5vpy/3OlwjQHJ8nk0tq0GEcXIIQo6 zVPSEnTOk09LGCqEkOPawNIz4P2/YVaW9KO3jfbWskH7GH5Ru36h2juZL A==; X-CSE-ConnectionGUID: FcTJCmk2Rf2oYdrXSUESHw== X-CSE-MsgGUID: SqO2sgopQVymkVY5P/tvZQ== X-IronPort-AV: E=McAfee;i="6800,10657,11718"; a="73545049" X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="73545049" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 X-CSE-ConnectionGUID: +N+uQ2N4SXSYV95RFeDglA== X-CSE-MsgGUID: 11b0snK6QLWNaiYU1Kb7+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,323,1763452800"; d="scan'208";a="218120407" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 8/9] selftests/resctrl: Simplify perf usage in CAT test Date: Tue, 3 Mar 2026 16:19:37 -0800 Message-ID: <42ea6df7c8c8aceecdd1037f09b13b4cc34521f6.1772582958.git.reinette.chatre@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CAT test relies on the PERF_COUNT_HW_CACHE_MISSES event to determine if modifying a cache portion size is successful. This event is configured to report the data as part of an event group, but no other events are added to the group. Remove the unnecessary PERF_FORMAT_GROUP format setting. This eliminates the need for struct perf_event_read and results in read() of the associated file descriptor to return just one value associated with the PERF_COUNT_HW_CACHE_MISSES event of interest. Signed-off-by: Reinette Chatre Tested-by: Chen Yu --- tools/testing/selftests/resctrl/cache.c | 17 +++++------------ tools/testing/selftests/resctrl/cat_test.c | 4 +--- tools/testing/selftests/resctrl/resctrl.h | 11 +---------- 3 files changed, 7 insertions(+), 25 deletions(-) diff --git a/tools/testing/selftests/resctrl/cache.c b/tools/testing/selfte= sts/resctrl/cache.c index 1ff1104e6575..03313a5ff905 100644 --- a/tools/testing/selftests/resctrl/cache.c +++ b/tools/testing/selftests/resctrl/cache.c @@ -10,7 +10,6 @@ void perf_event_attr_initialize(struct perf_event_attr *p= ea, __u64 config) memset(pea, 0, sizeof(*pea)); pea->type =3D PERF_TYPE_HARDWARE; pea->size =3D sizeof(*pea); - pea->read_format =3D PERF_FORMAT_GROUP; pea->exclude_kernel =3D 1; pea->exclude_hv =3D 1; pea->exclude_idle =3D 1; @@ -37,19 +36,13 @@ int perf_event_reset_enable(int pe_fd) return 0; } =20 -void perf_event_initialize_read_format(struct perf_event_read *pe_read) -{ - memset(pe_read, 0, sizeof(*pe_read)); - pe_read->nr =3D 1; -} - int perf_open(struct perf_event_attr *pea, pid_t pid, int cpu_no) { int pe_fd; =20 pe_fd =3D perf_event_open(pea, pid, cpu_no, -1, PERF_FLAG_FD_CLOEXEC); if (pe_fd =3D=3D -1) { - ksft_perror("Error opening leader"); + ksft_perror("Unable to set up performance monitoring"); return -1; } =20 @@ -132,9 +125,9 @@ static int print_results_cache(const char *filename, pi= d_t bm_pid, __u64 llc_val * * Return: =3D0 on success. <0 on failure. */ -int perf_event_measure(int pe_fd, struct perf_event_read *pe_read, - const char *filename, pid_t bm_pid) +int perf_event_measure(int pe_fd, const char *filename, pid_t bm_pid) { + __u64 value; int ret; =20 /* Stop counters after one span to get miss rate */ @@ -142,13 +135,13 @@ int perf_event_measure(int pe_fd, struct perf_event_r= ead *pe_read, if (ret < 0) return ret; =20 - ret =3D read(pe_fd, pe_read, sizeof(*pe_read)); + ret =3D read(pe_fd, &value, sizeof(value)); if (ret =3D=3D -1) { ksft_perror("Could not get perf value"); return -1; } =20 - return print_results_cache(filename, bm_pid, pe_read->values[0].value); + return print_results_cache(filename, bm_pid, value); } =20 /* diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index 8bc47f06679a..6aac03147d41 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -135,7 +135,6 @@ static int cat_test(const struct resctrl_test *test, struct resctrl_val_param *param, size_t span, unsigned long current_mask) { - struct perf_event_read pe_read; struct perf_event_attr pea; cpu_set_t old_affinity; unsigned char *buf; @@ -159,7 +158,6 @@ static int cat_test(const struct resctrl_test *test, goto reset_affinity; =20 perf_event_attr_initialize(&pea, PERF_COUNT_HW_CACHE_MISSES); - perf_event_initialize_read_format(&pe_read); pe_fd =3D perf_open(&pea, bm_pid, uparams->cpu); if (pe_fd < 0) { ret =3D -1; @@ -192,7 +190,7 @@ static int cat_test(const struct resctrl_test *test, =20 fill_cache_read(buf, span, true); =20 - ret =3D perf_event_measure(pe_fd, &pe_read, param->filename, bm_pid); + ret =3D perf_event_measure(pe_fd, param->filename, bm_pid); if (ret) goto free_buf; } diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 861bf25f2f28..e04b313dd7f7 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -148,13 +148,6 @@ struct resctrl_val_param { struct fill_buf_param *fill_buf; }; =20 -struct perf_event_read { - __u64 nr; /* The number of events */ - struct { - __u64 value; /* The value of the event */ - } values[2]; -}; - /* * Memory location that consumes values compiler must not optimize away. * Volatile ensures writes to this location cannot be optimized away by @@ -210,11 +203,9 @@ unsigned int count_bits(unsigned long n); int snc_kernel_support(void); =20 void perf_event_attr_initialize(struct perf_event_attr *pea, __u64 config); -void perf_event_initialize_read_format(struct perf_event_read *pe_read); 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d="scan'208";a="218120409" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 16:19:45 -0800 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v2 9/9] selftests/resctrl: Reduce L2 impact on CAT test Date: Tue, 3 Mar 2026 16:19:38 -0800 Message-ID: <74657e85c607b1494c898353087fa40e80a8af01.1772582958.git.reinette.chatre@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The L3 CAT test loads a buffer into cache that is proportional to the L3 size allocated for the workload and measures cache misses when accessing the buffer as a test of L3 occupancy. When loading the buffer it can be assumed that a portion of the buffer will be loaded into the L2 cache and depending on cache design may not be present in L3. It is thus possible for data to not be in L3 but also not trigger an L3 cache miss when accessed. Reduce impact of L2 on the L3 CAT test by, if L2 allocation is supported, minimizing the portion of L2 that the workload can allocate into. This encourages most of buffer to be loaded into L3 and support better comparison between buffer size, cache portion, and cache misses when accessing the buffer. Signed-off-by: Reinette Chatre Tested-by: Chen Yu --- tools/testing/selftests/resctrl/cat_test.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index 6aac03147d41..26062684a9f4 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -157,6 +157,12 @@ static int cat_test(const struct resctrl_test *test, if (ret) goto reset_affinity; =20 + if (!strcmp(test->resource, "L3") && resctrl_resource_exists("L2")) { + ret =3D write_schemata(param->ctrlgrp, "0x1", uparams->cpu, "L2"); + if (ret) + goto reset_affinity; + } + perf_event_attr_initialize(&pea, PERF_COUNT_HW_CACHE_MISSES); pe_fd =3D perf_open(&pea, bm_pid, uparams->cpu); if (pe_fd < 0) { --=20 2.50.1