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Mon, 2 Mar 2026 07:25:22 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , , Subject: [PATCH 1/3] dt-bindings: iio: adc: ad4130: Add new supported parts Date: Sat, 28 Feb 2026 09:38:43 -0300 Message-ID: <0b290dbdfeada56bdb513b7a57994d84e971fb34.1772078999.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: wOzX4ao2AKRUkbczwnUGwsHET3FjXDAT X-Proofpoint-ORIG-GUID: wOzX4ao2AKRUkbczwnUGwsHET3FjXDAT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDEwNCBTYWx0ZWRfX1kukaLRnz21C RqO94WkhN2laJrepMWd/5o3Vh5itjo45KEpHiAULW0bQ1D8h3Y2Ba5iabY/GwH8uAEhnAIf0IR7 ChVR85E+0JJeFivQ0WfBlZEoorNhOrNWY+7qO2l+2mTmpEs6CtOcTqu1EDZGN4jtRn8k5FkKJlf 1h3BV3JJNB0AxtheJqCT1E2u16RvWgUy6cLKL+ktqfsZm0sGN4bXMZCtCn650ajURMK3QJN++q6 MpnXo5AMiYTzwOEy3D3ieA82bPE0saJo1anfl8HB2hK9sPDT071LBHuRcSTcA8Ts6EtxoA+te/L tktii+Vs4Jxc9BDOtVXMXmJNTtLfLjczF6cjnaHo2/2H/4wAFMBACUvORLbP/YRb+j1m8ri4lAI 80mfQohByGtalsviReuS1qnRttf994E6mW3ENJjDi+toDOfF8MpkmbahqxBRSM2PSL+IR2FJMRo oSat15CIkVpKECfACEg== X-Authority-Analysis: v=2.4 cv=HtJ72kTS c=1 sm=1 tr=0 ts=69a581be cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gEfo2CItAAAA:8 a=gAnH3GRIAAAA:8 a=asbD4md8-q6e6i43ReAA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_03,2026-02-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1011 impostorscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603020104 Content-Type: text/plain; charset="utf-8" Extend driver support for AD4129-4/8, AD4130-4, and AD4131-4/8 ADC variants. Signed-off-by: Jonathan Santos Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/iio/adc/adi,ad4130.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4130.yaml index d00690a8d3fb..075ce62cb4e7 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml @@ -5,19 +5,30 @@ $id: http://devicetree.org/schemas/iio/adc/adi,ad4130.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Analog Devices AD4130 ADC device driver +title: Analog Devices AD4130 family ADC device driver =20 maintainers: - Cosmin Tanislav =20 description: | - Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here: + Bindings for the Analog Devices AD4130 family ADCs. + Datasheets can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD= 4129-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD= 4129-8.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD= 4130-4.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/AD= 4130-8.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD= 4131-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD= 4131-8.pdf =20 properties: compatible: enum: + - adi,ad4129-4 + - adi,ad4129-8 + - adi,ad4130-4 - adi,ad4130 + - adi,ad4131-4 + - adi,ad4131-8 =20 reg: maxItems: 1 --=20 2.34.1 From nobody Thu Apr 16 10:42:20 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DA7E3A0EBB; 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Mon, 2 Mar 2026 07:25:31 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , , Subject: [PATCH 2/3] iio: adc: ad4130: introduce chip info for future multidevice support Date: Sat, 28 Feb 2026 09:38:53 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=adpsXBot c=1 sm=1 tr=0 ts=69a581c6 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=iK7pNCdl7K3njzu4ZfAA:9 X-Proofpoint-GUID: uRTBUugSssVqWcZugOHXZzmkLkxwJNok X-Proofpoint-ORIG-GUID: uRTBUugSssVqWcZugOHXZzmkLkxwJNok X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDEwNCBTYWx0ZWRfX4nfvxuQnnSf0 vRylcci8m9Ugf0LBf5zx0K85ZJQs0rffPLiZrrjk3GiKz/chJgC3expiHKlSZ3nns4IgJ9B63N2 aGPDOsqvRq2NUD58rIwXIunjAHBa4fnekHjJ6r50KYnS44LI9UCYZjBmz/bRESS1Sqns7csG9uv qvoNKVtfHwfV9c8horimST6510DUgE0aZQ+ghWJeUuDc/R95LLZt/f+fdzqG6GCFIy2FEK2Z5Vq ZXl7b4HnArLCMZq9+xuRxGAccE8Rbh6xUK5jcP6fyqDLhLiylSu9knvOULooZTNXAiYnEhvoR9c LzKSKAjplwfMHKkYW0yofGP8uC8bSZfCuYmiat6miu6rY5UcYrQwn6Ov5dVSVeI6PYzScU25rlb NK1v2F/B7uXfX3AWvI3gOflcHin6ZkHXNwGnAVIstd9u/1SBkQKnIIcnQyVDUa8p/1DnKNOvp6Y utLzmX/BNgfCVqZ7syw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_03,2026-02-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603020104 Content-Type: text/plain; charset="utf-8" Introduce a chip_info structure to abstract device-specific parameters and prepare the driver for supporting multiple AD4130 family variants. Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad4130.c | 48 ++++++++++++++++++++++++++++++---------- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/iio/adc/ad4130.c b/drivers/iio/adc/ad4130.c index 5567ae5dee88..138fc0b99d81 100644 --- a/drivers/iio/adc/ad4130.c +++ b/drivers/iio/adc/ad4130.c @@ -224,6 +224,14 @@ enum ad4130_pin_function { AD4130_PIN_FN_VBIAS =3D BIT(3), }; =20 +struct ad4130_chip_info { + const char *name; + unsigned int max_analog_pins; + const struct iio_info *info; + const unsigned int *reg_size; + const unsigned int reg_size_length; +}; + /* * If you make adaptations in this struct, you most likely also have to ad= apt * ad4130_setup_info_eq(), too. @@ -268,6 +276,7 @@ struct ad4130_state { struct regmap *regmap; struct spi_device *spi; struct clk *mclk; + const struct ad4130_chip_info *chip_info; struct regulator_bulk_data regulators[4]; u32 irq_trigger; u32 inv_irq_trigger; @@ -394,10 +403,10 @@ static const char * const ad4130_filter_types_str[] = =3D { static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, unsigned int *size) { - if (reg >=3D ARRAY_SIZE(ad4130_reg_size)) + if (reg >=3D st->chip_info->reg_size_length) return -EINVAL; =20 - *size =3D ad4130_reg_size[reg]; + *size =3D st->chip_info->reg_size[reg]; =20 return 0; } @@ -1291,6 +1300,14 @@ static const struct iio_info ad4130_info =3D { .debugfs_reg_access =3D ad4130_reg_access, }; =20 +static const struct ad4130_chip_info ad4130_8_chip_info =3D { + .name =3D "ad4130-8", + .max_analog_pins =3D 16, + .info =3D &ad4130_info, + .reg_size =3D ad4130_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4130_reg_size), +}; + static int ad4130_buffer_postenable(struct iio_dev *indio_dev) { struct ad4130_state *st =3D iio_priv(indio_dev); @@ -1504,7 +1521,7 @@ static int ad4130_validate_diff_channel(struct ad4130= _state *st, u32 pin) return dev_err_probe(dev, -EINVAL, "Invalid differential channel %u\n", pin); =20 - if (pin >=3D AD4130_MAX_ANALOG_PINS) + if (pin >=3D st->chip_info->max_analog_pins) return 0; =20 if (st->pins_fn[pin] =3D=3D AD4130_PIN_FN_SPECIAL) @@ -1536,7 +1553,7 @@ static int ad4130_validate_excitation_pin(struct ad41= 30_state *st, u32 pin) { struct device *dev =3D &st->spi->dev; =20 - if (pin >=3D AD4130_MAX_ANALOG_PINS) + if (pin >=3D st->chip_info->max_analog_pins) return dev_err_probe(dev, -EINVAL, "Invalid excitation pin %u\n", pin); =20 @@ -1554,7 +1571,7 @@ static int ad4130_validate_vbias_pin(struct ad4130_st= ate *st, u32 pin) { struct device *dev =3D &st->spi->dev; =20 - if (pin >=3D AD4130_MAX_ANALOG_PINS) + if (pin >=3D st->chip_info->max_analog_pins) return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n", pin); =20 @@ -1730,7 +1747,7 @@ static int ad4310_parse_fw(struct iio_dev *indio_dev) =20 ret =3D device_property_count_u32(dev, "adi,vbias-pins"); if (ret > 0) { - if (ret > AD4130_MAX_ANALOG_PINS) + if (ret > st->chip_info->max_analog_pins) return dev_err_probe(dev, -EINVAL, "Too many vbias pins %u\n", ret); =20 @@ -1994,6 +2011,8 @@ static int ad4130_probe(struct spi_device *spi) =20 st =3D iio_priv(indio_dev); =20 + st->chip_info =3D device_get_match_data(dev); + memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); init_completion(&st->completion); mutex_init(&st->lock); @@ -2011,9 +2030,9 @@ static int ad4130_probe(struct spi_device *spi) spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, ARRAY_SIZE(st->fifo_xfer)); =20 - indio_dev->name =3D AD4130_NAME; + indio_dev->name =3D st->chip_info->name; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->info =3D &ad4130_info; + indio_dev->info =3D st->chip_info->info; =20 st->regmap =3D devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); if (IS_ERR(st->regmap)) @@ -2056,7 +2075,7 @@ static int ad4130_probe(struct spi_device *spi) ad4130_fill_scale_tbls(st); =20 st->gc.owner =3D THIS_MODULE; - st->gc.label =3D AD4130_NAME; + st->gc.label =3D st->chip_info->name; st->gc.base =3D -1; st->gc.ngpio =3D AD4130_MAX_GPIOS; st->gc.parent =3D dev; @@ -2102,19 +2121,24 @@ static int ad4130_probe(struct spi_device *spi) } =20 static const struct of_device_id ad4130_of_match[] =3D { - { - .compatible =3D "adi,ad4130", - }, + { .compatible =3D "adi,ad4130", .data =3D &ad4130_8_chip_info }, { } }; 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charset="utf-8" Add support for AD4129-4/8, AD4130-4, and AD4131-4/8 variants. The AD4129 series supports the same FIFO interface as the AD4130 but with reduced resolution (16-bit). The AD4131 series lacks FIFO support, so triggered buffer functionality is introduced. The 4-channel variants feature fewer analog inputs, GPIOs, and sparse pin mappings for VBIAS, analog inputs, and excitation currents. The driver now handles these differences with chip-specific configurations, including pin mappings and GPIO counts. Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad4130.c | 435 ++++++++++++++++++++++++++++++++------- 1 file changed, 365 insertions(+), 70 deletions(-) diff --git a/drivers/iio/adc/ad4130.c b/drivers/iio/adc/ad4130.c index 138fc0b99d81..e3a3b373e99d 100644 --- a/drivers/iio/adc/ad4130.c +++ b/drivers/iio/adc/ad4130.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,7 @@ #include #include #include +#include #include =20 #include @@ -30,6 +32,9 @@ #include #include #include +#include +#include +#include =20 #define AD4130_NAME "ad4130" =20 @@ -40,6 +45,7 @@ #define AD4130_ADC_CONTROL_REG 0x01 #define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14) #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13) +#define AD4130_ADC_CONTROL_CONT_READ_MASK BIT(11) #define AD4130_INT_REF_2_5V 2500000 #define AD4130_INT_REF_1_25V 1250000 #define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9) @@ -54,7 +60,9 @@ #define AD4130_IO_CONTROL_REG 0x03 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8) #define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4) +#define AD4130_4_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 6) #define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0) +#define AD4130_4_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 2) =20 #define AD4130_VBIAS_REG 0x04 =20 @@ -125,6 +133,28 @@ =20 #define AD4130_INVALID_SLOT -1 =20 +static const unsigned int ad4129_reg_size[] =3D { + [AD4130_STATUS_REG] =3D 1, + [AD4130_ADC_CONTROL_REG] =3D 2, + [AD4130_DATA_REG] =3D 2, + [AD4130_IO_CONTROL_REG] =3D 2, + [AD4130_VBIAS_REG] =3D 2, + [AD4130_ID_REG] =3D 1, + [AD4130_ERROR_REG] =3D 2, + [AD4130_ERROR_EN_REG] =3D 2, + [AD4130_MCLK_COUNT_REG] =3D 1, + [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1= )] =3D 3, + [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 3, + [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] =3D 2, + [AD4130_MISC_REG] =3D 2, + [AD4130_FIFO_CONTROL_REG] =3D 3, + [AD4130_FIFO_STATUS_REG] =3D 1, + [AD4130_FIFO_THRESHOLD_REG] =3D 3, + [AD4130_FIFO_DATA_REG] =3D 2, +}; + static const unsigned int ad4130_reg_size[] =3D { [AD4130_STATUS_REG] =3D 1, [AD4130_ADC_CONTROL_REG] =3D 2, @@ -147,6 +177,24 @@ static const unsigned int ad4130_reg_size[] =3D { [AD4130_FIFO_DATA_REG] =3D 3, }; =20 +static const unsigned int ad4131_reg_size[] =3D { + [AD4130_STATUS_REG] =3D 1, + [AD4130_ADC_CONTROL_REG] =3D 2, + [AD4130_DATA_REG] =3D 2, + [AD4130_IO_CONTROL_REG] =3D 2, + [AD4130_VBIAS_REG] =3D 2, + [AD4130_ID_REG] =3D 1, + [AD4130_ERROR_REG] =3D 2, + [AD4130_ERROR_EN_REG] =3D 2, + [AD4130_MCLK_COUNT_REG] =3D 1, + [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1= )] =3D 3, + [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 3, + [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = =3D 2, + [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] =3D 2, + [AD4130_MISC_REG] =3D 2, +}; + enum ad4130_int_ref_val { AD4130_INT_REF_VAL_2_5V, AD4130_INT_REF_VAL_1_25V, @@ -224,12 +272,32 @@ enum ad4130_pin_function { AD4130_PIN_FN_VBIAS =3D BIT(3), }; =20 +/* Map logical pins to register value */ +static const u8 ad4130_4_pin_map[] =3D { + 0x00, /* AIN0/VBIAS_0 */ + 0x01, /* AIN1/VBIAS_1 */ + 0x04, /* AIN2/VBIAS_2 */ + 0x05, /* AIN3/VBIAS_3 */ + 0x0A, /* AIN4/VBIAS_4 */ + 0x0B, /* AIN5/VBIAS_5 */ + 0x0E, /* AIN6/VBIAS_6 */ + 0x0F, /* AIN7/VBIAS_7 */ +}; + +static const u8 ad4130_8_pin_map[] =3D { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* AIN0/VBIAS_0-AIN7/VBIA= S_7 */ + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, /* AIN8/VBIAS_8-AIN15/VBI= AS_15 */ +}; + struct ad4130_chip_info { const char *name; unsigned int max_analog_pins; + unsigned int num_gpios; const struct iio_info *info; const unsigned int *reg_size; const unsigned int reg_size_length; + const u8 *pin_map; + bool has_fifo; }; =20 /* @@ -303,6 +371,7 @@ struct ad4130_state { u32 mclk_sel; bool int_ref_en; bool bipolar; + bool buffer_wait_for_irq; =20 unsigned int num_enabled_channels; unsigned int effective_watermark; @@ -310,6 +379,7 @@ struct ad4130_state { =20 struct spi_message fifo_msg; struct spi_transfer fifo_xfer[2]; + struct iio_trigger *trig; =20 /* * DMA (thus cache coherency maintenance) requires any transfer @@ -324,6 +394,12 @@ struct ad4130_state { u8 fifo_tx_buf[2]; u8 fifo_rx_buf[AD4130_FIFO_SIZE * AD4130_FIFO_MAX_SAMPLE_SIZE]; + + /* Triggered buffer data structure */ + struct { + u32 channels[AD4130_MAX_CHANNELS]; + s64 timestamp; + } scan __aligned(8); }; =20 static const char * const ad4130_int_pin_names[] =3D { @@ -514,7 +590,8 @@ static int ad4130_gpio_init_valid_mask(struct gpio_chip= *gc, =20 /* * Output-only GPIO functionality is available on pins AIN2 through - * AIN5. If these pins are used for anything else, do not expose them. + * AIN5 for some parts and AIN2 through AIN3 for others. If these pins + * are used for anything else, do not expose them. */ for (i =3D 0; i < ngpios; i++) { unsigned int pin =3D i + AD4130_AIN2_P1; @@ -535,8 +612,14 @@ static int ad4130_gpio_set(struct gpio_chip *gc, unsig= ned int offset, int value) { struct ad4130_state *st =3D gpiochip_get_data(gc); - unsigned int mask =3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK, - BIT(offset)); + unsigned int mask; + + if (st->chip_info->num_gpios =3D=3D AD4130_MAX_GPIOS) + mask =3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK, + BIT(offset)); + else + mask =3D FIELD_PREP(AD4130_4_IO_CONTROL_GPIO_DATA_MASK, + BIT(offset)); =20 return regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, value ? mask : 0); @@ -597,10 +680,43 @@ static irqreturn_t ad4130_irq_handler(int irq, void *= private) struct iio_dev *indio_dev =3D private; struct ad4130_state *st =3D iio_priv(indio_dev); =20 - if (iio_buffer_enabled(indio_dev)) - ad4130_push_fifo_data(indio_dev); - else + if (iio_buffer_enabled(indio_dev)) { + if (st->chip_info->has_fifo) + ad4130_push_fifo_data(indio_dev); + else if (st->buffer_wait_for_irq) + complete(&st->completion); + else + iio_trigger_poll(st->trig); + } else { complete(&st->completion); + } + + return IRQ_HANDLED; +} + +static irqreturn_t ad4130_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4130_state *st =3D iio_priv(indio_dev); + unsigned int data_reg_size =3D ad4130_data_reg_size(st); + unsigned int num_en_chn =3D bitmap_weight(indio_dev->active_scan_mask, + iio_get_masklength(indio_dev)); + struct spi_transfer xfer =3D { + .rx_buf =3D st->scan.channels, + .len =3D data_reg_size * num_en_chn, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret < 0) + goto err_unlock; + + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan, + iio_get_time_ns(indio_dev)); + +err_unlock: + iio_trigger_notify_done(indio_dev->trig); =20 return IRQ_HANDLED; } @@ -1300,12 +1416,77 @@ static const struct iio_info ad4130_info =3D { .debugfs_reg_access =3D ad4130_reg_access, }; =20 +static const struct iio_info ad4131_info =3D { + .read_raw =3D ad4130_read_raw, + .read_avail =3D ad4130_read_avail, + .write_raw_get_fmt =3D ad4130_write_raw_get_fmt, + .write_raw =3D ad4130_write_raw, + .update_scan_mode =3D ad4130_update_scan_mode, + .debugfs_reg_access =3D ad4130_reg_access, +}; + +static const struct ad4130_chip_info ad4129_4_chip_info =3D { + .name =3D "ad4129-4", + .max_analog_pins =3D 8, + .num_gpios =3D 2, + .info =3D &ad4130_info, + .reg_size =3D ad4129_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4129_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_4_pin_map, +}; + +static const struct ad4130_chip_info ad4129_8_chip_info =3D { + .name =3D "ad4129-8", + .max_analog_pins =3D 16, + .num_gpios =3D 4, + .info =3D &ad4130_info, + .reg_size =3D ad4129_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4129_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_8_pin_map, +}; + +static const struct ad4130_chip_info ad4130_4_chip_info =3D { + .name =3D "ad4130-4", + .max_analog_pins =3D 16, + .num_gpios =3D 2, + .info =3D &ad4130_info, + .reg_size =3D ad4130_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4130_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_4_pin_map, +}; + static const struct ad4130_chip_info ad4130_8_chip_info =3D { .name =3D "ad4130-8", .max_analog_pins =3D 16, + .num_gpios =3D 4, .info =3D &ad4130_info, .reg_size =3D ad4130_reg_size, .reg_size_length =3D ARRAY_SIZE(ad4130_reg_size), + .has_fifo =3D true, + .pin_map =3D ad4130_8_pin_map, +}; + +static const struct ad4130_chip_info ad4131_4_chip_info =3D { + .name =3D "ad4131-4", + .max_analog_pins =3D 8, + .num_gpios =3D 2, + .info =3D &ad4131_info, + .reg_size =3D ad4131_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4131_reg_size), + .pin_map =3D ad4130_4_pin_map, +}; + +static const struct ad4130_chip_info ad4131_8_chip_info =3D { + .name =3D "ad4131-8", + .max_analog_pins =3D 16, + .num_gpios =3D 4, + .info =3D &ad4131_info, + .reg_size =3D ad4131_reg_size, + .reg_size_length =3D ARRAY_SIZE(ad4131_reg_size), + .pin_map =3D ad4130_8_pin_map, }; =20 static int ad4130_buffer_postenable(struct iio_dev *indio_dev) @@ -1315,44 +1496,91 @@ static int ad4130_buffer_postenable(struct iio_dev = *indio_dev) =20 guard(mutex)(&st->lock); =20 - ret =3D ad4130_set_watermark_interrupt_en(st, true); - if (ret) - return ret; + if (st->chip_info->has_fifo) { + ret =3D ad4130_set_watermark_interrupt_en(st, true); + if (ret) + return ret; =20 - ret =3D irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); - if (ret) - return ret; + ret =3D irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); + if (ret) + return ret; + + ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); + if (ret) + return ret; + } =20 - ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); + ret =3D ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); if (ret) return ret; =20 - return ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); + /* + * When using triggered buffer, Entering continuous read mode must + * be the last command sent. No configuration changes are allowed until + * exiting this mode. + */ + if (!st->chip_info->has_fifo) { + ret =3D regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, + AD4130_ADC_CONTROL_CONT_READ_MASK, + FIELD_PREP(AD4130_ADC_CONTROL_CONT_READ_MASK, 1)); + if (ret) + return ret; + } + + return 0; } =20 static int ad4130_buffer_predisable(struct iio_dev *indio_dev) { struct ad4130_state *st =3D iio_priv(indio_dev); unsigned int i; + u32 temp; int ret; =20 guard(mutex)(&st->lock); =20 + if (!st->chip_info->has_fifo) { + temp =3D 0x42; + reinit_completion(&st->completion); + + /* + * In continuous read mode, when all samples are read, the data + * ready signal returns high until the next conversion result is + * ready. To exit this mode, the command must be sent when data + * ready is low. In order to ensure that condition, wait for the + * next interrupt (when the new conversion is finished), allowing + * data ready to return low before sending the exit command. + */ + st->buffer_wait_for_irq =3D true; + ret =3D wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(1000)); + st->buffer_wait_for_irq =3D false; + if (!ret) + dev_warn(&st->spi->dev, "Conversion timed out\n"); + + /* Perform a read data command to exit continuous read mode (0x42) */ + ret =3D spi_write(st->spi, &temp, 1); + if (ret) + return ret; + } + ret =3D ad4130_set_mode(st, AD4130_MODE_IDLE); if (ret) return ret; =20 - ret =3D irq_set_irq_type(st->spi->irq, st->irq_trigger); - if (ret) - return ret; + if (st->chip_info->has_fifo) { + ret =3D irq_set_irq_type(st->spi->irq, st->irq_trigger); + if (ret) + return ret; =20 - ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); - if (ret) - return ret; + ret =3D ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); + if (ret) + return ret; =20 - ret =3D ad4130_set_watermark_interrupt_en(st, false); - if (ret) - return ret; + ret =3D ad4130_set_watermark_interrupt_en(st, false); + if (ret) + return ret; + } =20 /* * update_scan_mode() is not called in the disable path, disable all @@ -1427,6 +1655,34 @@ static const struct iio_dev_attr *ad4130_fifo_attrib= utes[] =3D { NULL }; =20 +static const struct iio_trigger_ops ad4130_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + +static int ad4130_triggered_buffer_setup(struct iio_dev *indio_dev) +{ + struct ad4130_state *st =3D iio_priv(indio_dev); + int ret; + + st->trig =3D devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", + indio_dev->name, iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + + st->trig->ops =3D &ad4130_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret =3D devm_iio_trigger_register(indio_dev->dev.parent, st->trig); + if (ret) + return ret; + + indio_dev->trig =3D iio_trigger_get(st->trig); + + return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, + &iio_pollfunc_store_time, + &ad4130_trigger_handler, + &ad4130_buffer_ops); +} + static int _ad4130_find_table_index(const unsigned int *tbl, size_t len, unsigned int val) { @@ -1513,6 +1769,17 @@ static int ad4130_parse_fw_setup(struct ad4130_state= *st, return 0; } =20 +static unsigned int ad4130_translate_pin(struct ad4130_state *st, + unsigned int logical_pin) +{ + /* For analog input pins, use the chip-specific pin mapping */ + if (logical_pin < st->chip_info->max_analog_pins) + return st->chip_info->pin_map[logical_pin]; + + /* For internal channels, pass through unchanged */ + return logical_pin; +} + static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) { struct device *dev =3D &st->spi->dev; @@ -1931,9 +2198,14 @@ static int ad4130_setup(struct iio_dev *indio_dev) * function of P2 takes priority over the GPIO out function. */ val =3D 0; - for (i =3D 0; i < AD4130_MAX_GPIOS; i++) - if (st->pins_fn[i + AD4130_AIN2_P1] =3D=3D AD4130_PIN_FN_NONE) - val |=3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); + for (i =3D 0; i < st->chip_info->num_gpios; i++) { + if (st->pins_fn[i + AD4130_AIN2_P1] =3D=3D AD4130_PIN_FN_NONE) { + if (st->chip_info->num_gpios =3D=3D 2) + val |=3D FIELD_PREP(AD4130_4_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); + else + val |=3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); + } + } =20 val |=3D FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); =20 @@ -1943,21 +2215,23 @@ static int ad4130_setup(struct iio_dev *indio_dev) =20 val =3D 0; for (i =3D 0; i < st->num_vbias_pins; i++) - val |=3D BIT(st->vbias_pins[i]); + val |=3D BIT(ad4130_translate_pin(st, st->vbias_pins[i])); =20 ret =3D regmap_write(st->regmap, AD4130_VBIAS_REG, val); if (ret) return ret; =20 - ret =3D regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, - AD4130_FIFO_CONTROL_HEADER_MASK); - if (ret) - return ret; + if (st->chip_info->has_fifo) { + ret =3D regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, + AD4130_FIFO_CONTROL_HEADER_MASK); + if (ret) + return ret; =20 - /* FIFO watermark interrupt starts out as enabled, disable it. */ - ret =3D ad4130_set_watermark_interrupt_en(st, false); - if (ret) - return ret; + /* FIFO watermark interrupt starts out as enabled, disable it. */ + ret =3D ad4130_set_watermark_interrupt_en(st, false); + if (ret) + return ret; + } =20 /* Setup channels. */ for (i =3D 0; i < indio_dev->num_channels; i++) { @@ -1965,10 +2239,14 @@ static int ad4130_setup(struct iio_dev *indio_dev) struct iio_chan_spec *chan =3D &st->chans[i]; unsigned int val; =20 - val =3D FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) | - FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) | - FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) | - FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1); + val =3D FIELD_PREP(AD4130_CHANNEL_AINP_MASK, + ad4130_translate_pin(st, chan->channel)) | + FIELD_PREP(AD4130_CHANNEL_AINM_MASK, + ad4130_translate_pin(st, chan->channel2)) | + FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, + ad4130_translate_pin(st, chan_info->iout0)) | + FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, + ad4130_translate_pin(st, chan_info->iout1)); =20 ret =3D regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); if (ret) @@ -2018,17 +2296,19 @@ static int ad4130_probe(struct spi_device *spi) mutex_init(&st->lock); st->spi =3D spi; =20 - /* - * Xfer: [ XFR1 ] [ XFR2 ] - * Master: 0x7D N ...................... - * Slave: ...... DATA1 DATA2 ... DATAN - */ - st->fifo_tx_buf[0] =3D AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; - st->fifo_xfer[0].tx_buf =3D st->fifo_tx_buf; - st->fifo_xfer[0].len =3D sizeof(st->fifo_tx_buf); - st->fifo_xfer[1].rx_buf =3D st->fifo_rx_buf; - spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, - ARRAY_SIZE(st->fifo_xfer)); + if (st->chip_info->has_fifo) { + /* + * Xfer: [ XFR1 ] [ XFR2 ] + * Master: 0x7D N ...................... + * Slave: ...... DATA1 DATA2 ... DATAN + */ + st->fifo_tx_buf[0] =3D AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; + st->fifo_xfer[0].tx_buf =3D st->fifo_tx_buf; + st->fifo_xfer[0].len =3D sizeof(st->fifo_tx_buf); + st->fifo_xfer[1].rx_buf =3D st->fifo_rx_buf; + spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, + ARRAY_SIZE(st->fifo_xfer)); + } =20 indio_dev->name =3D st->chip_info->name; indio_dev->modes =3D INDIO_DIRECT_MODE; @@ -2077,7 +2357,7 @@ static int ad4130_probe(struct spi_device *spi) st->gc.owner =3D THIS_MODULE; st->gc.label =3D st->chip_info->name; st->gc.base =3D -1; - st->gc.ngpio =3D AD4130_MAX_GPIOS; + st->gc.ngpio =3D st->chip_info->num_gpios; st->gc.parent =3D dev; st->gc.can_sleep =3D true; st->gc.init_valid_mask =3D ad4130_gpio_init_valid_mask; @@ -2088,9 +2368,12 @@ static int ad4130_probe(struct spi_device *spi) if (ret) return ret; =20 - ret =3D devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, - &ad4130_buffer_ops, - ad4130_fifo_attributes); + if (st->chip_info->has_fifo) + ret =3D devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, + &ad4130_buffer_ops, + ad4130_fifo_attributes); + else + ret =3D ad4130_triggered_buffer_setup(indio_dev); if (ret) return ret; =20 @@ -2100,34 +2383,46 @@ static int ad4130_probe(struct spi_device *spi) if (ret) return dev_err_probe(dev, ret, "Failed to request irq\n"); =20 - /* - * When the chip enters FIFO mode, IRQ polarity is inverted. - * When the chip exits FIFO mode, IRQ polarity returns to normal. - * See datasheet pages: 65, FIFO Watermark Interrupt section, - * and 71, Bit Descriptions for STATUS Register, RDYB. - * Cache the normal and inverted IRQ triggers to set them when - * entering and exiting FIFO mode. - */ - st->irq_trigger =3D irq_get_trigger_type(spi->irq); - if (st->irq_trigger & IRQF_TRIGGER_RISING) - st->inv_irq_trigger =3D IRQF_TRIGGER_FALLING; - else if (st->irq_trigger & IRQF_TRIGGER_FALLING) - st->inv_irq_trigger =3D IRQF_TRIGGER_RISING; - else - return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", - st->irq_trigger); + if (st->chip_info->has_fifo) { + /* + * When the chip enters FIFO mode, IRQ polarity is inverted. + * When the chip exits FIFO mode, IRQ polarity returns to normal. + * See datasheet pages: 65, FIFO Watermark Interrupt section, + * and 71, Bit Descriptions for STATUS Register, RDYB. + * Cache the normal and inverted IRQ triggers to set them when + * entering and exiting FIFO mode. + */ + st->irq_trigger =3D irq_get_trigger_type(spi->irq); + if (st->irq_trigger & IRQF_TRIGGER_RISING) + st->inv_irq_trigger =3D IRQF_TRIGGER_FALLING; + else if (st->irq_trigger & IRQF_TRIGGER_FALLING) + st->inv_irq_trigger =3D IRQF_TRIGGER_RISING; + else + return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", + st->irq_trigger); + } =20 return devm_iio_device_register(dev, indio_dev); } =20 static const struct of_device_id ad4130_of_match[] =3D { + { .compatible =3D "adi,ad4129-4", .data =3D &ad4129_4_chip_info }, + { .compatible =3D "adi,ad4129-8", .data =3D &ad4129_8_chip_info }, + { .compatible =3D "adi,ad4130-4", .data =3D &ad4130_4_chip_info }, { .compatible =3D "adi,ad4130", .data =3D &ad4130_8_chip_info }, + { .compatible =3D "adi,ad4131-4", .data =3D &ad4131_4_chip_info }, + { .compatible =3D "adi,ad4131-8", .data =3D &ad4131_8_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4130_of_match); =20 static const struct spi_device_id ad4130_id_table[] =3D { + { "ad4129-4", (kernel_ulong_t)&ad4129_4_chip_info }, + { "ad4129-8", (kernel_ulong_t)&ad4129_8_chip_info }, + { "ad4130-4", (kernel_ulong_t)&ad4130_4_chip_info }, { "ad4130", (kernel_ulong_t)&ad4130_8_chip_info }, + { "ad4131-4", (kernel_ulong_t)&ad4131_4_chip_info }, + { "ad4131-8", (kernel_ulong_t)&ad4131_8_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4130_id_table); --=20 2.34.1