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Mon, 23 Feb 2026 08:26:36 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH v3 1/6] arm64: dts: mt8167: Reorder nodes according to mmio address Date: Mon, 23 Feb 2026 16:22:45 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding display nodes. No other changes. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++------------ 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts= /mediatek/mt8167.dtsi index 2374c0953057..27cf32d7ae35 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -29,12 +29,6 @@ infracfg: infracfg@10001000 { #clock-cells =3D <1>; }; =20 - apmixedsys: apmixedsys@10018000 { - compatible =3D "mediatek,mt8167-apmixedsys", "syscon"; - reg =3D <0 0x10018000 0 0x710>; - #clock-cells =3D <1>; - }; - scpsys: syscon@10006000 { compatible =3D "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg =3D <0 0x10006000 0 0x1000>; @@ -101,18 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN { }; }; =20 - imgsys: syscon@15000000 { - compatible =3D "mediatek,mt8167-imgsys", "syscon"; - reg =3D <0 0x15000000 0 0x1000>; - #clock-cells =3D <1>; - }; - - vdecsys: syscon@16000000 { - compatible =3D "mediatek,mt8167-vdecsys", "syscon"; - reg =3D <0 0x16000000 0 0x1000>; - #clock-cells =3D <1>; - }; - pio: pinctrl@1000b000 { compatible =3D "mediatek,mt8167-pinctrl"; reg =3D <0 0x1000b000 0 0x1000>; @@ -124,12 +106,36 @@ pio: pinctrl@1000b000 { interrupts =3D ; }; =20 + apmixedsys: apmixedsys@10018000 { + compatible =3D "mediatek,mt8167-apmixedsys", "syscon"; + reg =3D <0 0x10018000 0 0x710>; + #clock-cells =3D <1>; + }; + + iommu: m4u@10203000 { + compatible =3D "mediatek,mt8167-m4u"; + reg =3D <0 0x10203000 0 0x1000>; + mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>; + interrupts =3D ; + #iommu-cells =3D <1>; + }; + mmsys: syscon@14000000 { compatible =3D "mediatek,mt8167-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb0: larb@14016000 { + compatible =3D "mediatek,mt8167-smi-larb"; + reg =3D <0 0x14016000 0 0x1000>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + }; + smi_common: smi@14017000 { compatible =3D "mediatek,mt8167-smi-common"; reg =3D <0 0x14017000 0 0x1000>; @@ -139,14 +145,10 @@ smi_common: smi@14017000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 - larb0: larb@14016000 { - compatible =3D "mediatek,mt8167-smi-larb"; - reg =3D <0 0x14016000 0 0x1000>; - mediatek,smi =3D <&smi_common>; - clocks =3D <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names =3D "apb", "smi"; - power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + imgsys: syscon@15000000 { + compatible =3D "mediatek,mt8167-imgsys", "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; }; =20 larb1: larb@15001000 { @@ -159,6 +161,12 @@ larb1: larb@15001000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_ISP>; }; =20 + vdecsys: syscon@16000000 { + compatible =3D "mediatek,mt8167-vdecsys", "syscon"; + reg =3D <0 0x16000000 0 0x1000>; + #clock-cells =3D <1>; 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Mon, 23 Feb 2026 08:26:38 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d5463dsm19120357f8f.34.2026.02.23.08.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 08:26:38 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH v3 2/6] dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167 Date: Mon, 23 Feb 2026 16:22:46 +0000 Message-ID: <66eafae30f9fe00b469e79d385c1ddd24d209475.1771863641.git.l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibles for various display-related blocks of MediaTek mt8167. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 4 +++- 7 files changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aa= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.ya= ml index daf90ebb39bf..4bbea72b292a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -33,6 +33,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt6795-disp-aal + - mediatek,mt8167-disp-aal - const: mediatek,mt8173-disp-aal - items: - enum: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cc= orr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccor= r.yaml index fca8e7bb0cbc..5c5068128d0c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -25,7 +25,9 @@ properties: - mediatek,mt8183-disp-ccorr - mediatek,mt8192-disp-ccorr - items: - - const: mediatek,mt8365-disp-ccorr + - enum: + - mediatek,mt8167-disp-ccorr + - mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorr - items: - enum: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,di= ther.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dit= her.yaml index abaf27916d13..891c95be15b9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml @@ -26,6 +26,7 @@ properties: - mediatek,mt8183-disp-dither - items: - enum: + - mediatek,mt8167-disp-dither - mediatek,mt8186-disp-dither - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ga= mma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamm= a.yaml index 48542dc7e784..ec1054bb06d4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-gamma + - mediatek,mt8167-disp-gamma - const: mediatek,mt8173-disp-gamma - items: - enum: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ov= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.ya= ml index 4f110635afb6..679f731f0f15 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt2701-disp-ovl + - mediatek,mt8167-disp-ovl - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rd= ma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.= yaml index 878f676b581f..cb187a95c11e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -36,6 +36,7 @@ properties: - enum: - mediatek,mt7623-disp-rdma - mediatek,mt2712-disp-rdma + - mediatek,mt8167-disp-rdma - const: mediatek,mt2701-disp-rdma - items: - enum: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wd= ma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.= yaml index a3a2b71a4523..816841a96133 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml @@ -24,7 +24,9 @@ properties: - enum: - mediatek,mt8173-disp-wdma - items: - - const: mediatek,mt6795-disp-wdma + - enum: + - mediatek,mt6795-disp-wdma + - mediatek,mt8167-disp-wdma - const: mediatek,mt8173-disp-wdma =20 reg: --=20 2.43.0 From nobody Thu Mar 5 08:10:34 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B14E23126A9 for ; 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Mon, 23 Feb 2026 08:26:41 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d5463dsm19120357f8f.34.2026.02.23.08.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 08:26:40 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH v3 3/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167 Date: Mon, 23 Feb 2026 16:22:47 +0000 Message-ID: <92530e0a31eca1feb822f5c5fd4ac894937dd6c7.1771863641.git.l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the MediaTek mt8167 SoC: the DSI PHY found in this chip is fully compatible with the one found in the mt2701 SoC. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/= Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index acdbce937b0a..c6d0bbdbe0e2 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -23,6 +23,7 @@ properties: - items: - enum: - mediatek,mt7623-mipi-tx + - mediatek,mt8167-mipi-tx - const: mediatek,mt2701-mipi-tx - items: - enum: --=20 2.43.0 From nobody Thu Mar 5 08:10:34 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0229031326C for ; Mon, 23 Feb 2026 16:26:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 23 Feb 2026 08:26:43 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d5463dsm19120357f8f.34.2026.02.23.08.26.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 08:26:42 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH v3 4/6] arm64: dts: mediatek: mt8167: Add DRM nodes Date: Mon, 23 Feb 2026 16:22:48 +0000 Message-ID: <36762766bc2b6629eefc5f1adb5e98555df1f34b.1771863641.git.l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add all the DRM nodes required to get DSI to work on MT8167 SoC. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 317 +++++++++++++++++++++++ 1 file changed, 317 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts= /mediatek/mt8167.dtsi index 27cf32d7ae35..32d3895baaa6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -16,6 +16,20 @@ / { compatible =3D "mediatek,mt8167"; =20 + aliases { + aal0 =3D &aal; + ccorr0 =3D &ccorr; + color0 =3D &color; + dither0 =3D &dither; + dsi0 =3D &dsi; + gamma0 =3D γ + ovl0 =3D &ovl0; + pwm0 =3D &disp_pwm; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + wdma0 =3D &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible =3D "mediatek,mt8167-topckgen", "syscon"; @@ -120,10 +134,303 @@ iommu: m4u@10203000 { #iommu-cells =3D <1>; }; =20 + disp_pwm: pwm@1100f000 { + compatible =3D "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm"; + reg =3D <0 0x1100f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_PWM_26M>, <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names =3D "main", "mm"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + mmsys: syscon@14000000 { compatible =3D "mediatek,mt8167-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; #clock-cells =3D <1>; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mmsys_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + + mmsys_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_in>; + }; + }; + }; + + ovl0: ovl0@14007000 { + compatible =3D "mediatek,mt8167-disp-ovl"; + reg =3D <0 0x14007000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ovl0_in: endpoint { + remote-endpoint =3D <&mmsys_main>; + }; + }; + + port@1 { + reg =3D <1>; + ovl0_out: endpoint { + remote-endpoint =3D <&color_in>; + }; + }; + }; + }; + + rdma0: rdma0@14009000 { + compatible =3D "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg =3D <0 0x14009000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + rdma0_in: endpoint { + remote-endpoint =3D <&dither_out>; + }; + }; + + port@1 { + reg =3D <1>; + rdma0_out: endpoint { + remote-endpoint =3D <&dsi_in>; + }; + }; + }; + }; + + rdma1: rdma1@1400a000 { + compatible =3D "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg =3D <0 0x1400a000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + rdma1_in: endpoint { + remote-endpoint =3D <&mmsys_ext>; + }; + }; + + port@1 { + reg =3D <1>; + rdma1_out: endpoint { }; + }; + }; + }; + + wdma: wdma0@1400b000 { + compatible =3D "mediatek,mt8167-disp-wdma", "mediatek,mt8173-disp-wdma"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_WDMA>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_WDMA0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + }; + + color: color@1400c000 { + compatible =3D "mediatek,mt8167-disp-color"; + reg =3D <0 0x1400c000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + color_in: endpoint { + remote-endpoint =3D <&ovl0_out>; + }; + }; + + port@1 { + reg =3D <1>; + color_out: endpoint { + remote-endpoint =3D <&ccorr_in>; + }; + }; + }; + }; + + ccorr: ccorr@1400d000 { + compatible =3D "mediatek,mt8167-disp-ccorr", "mediatek,mt8183-disp-ccor= r"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ccorr_in: endpoint { + remote-endpoint =3D <&color_out>; + }; + }; + + port@1 { + reg =3D <1>; + ccorr_out: endpoint { + remote-endpoint =3D <&aal_in>; + }; + }; + }; + }; + + aal: aal@1400e000 { + compatible =3D "mediatek,mt8167-disp-aal", "mediatek,mt8173-disp-aal"; + reg =3D <0 0x1400e000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_AAL>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + aal_in: endpoint { + remote-endpoint =3D <&ccorr_out>; + }; + }; + + port@1 { + reg =3D <1>; + aal_out: endpoint { + remote-endpoint =3D <&gamma_in>; + }; + }; + }; + }; + + gamma: gamma@1400f000 { + compatible =3D "mediatek,mt8167-disp-gamma", "mediatek,mt8173-disp-gamm= a"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + gamma_in: endpoint { + remote-endpoint =3D <&aal_out>; + }; + }; + + port@1 { + reg =3D <1>; + gamma_out: endpoint { + remote-endpoint =3D <&dither_in>; + }; + }; + }; + }; + + dither: dither@14010000 { + compatible =3D "mediatek,mt8167-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x14010000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dither_in: endpoint { + remote-endpoint =3D <&gamma_out>; + }; + }; + + port@1 { + reg =3D <1>; + dither_out: endpoint { + remote-endpoint =3D <&rdma0_in>; + }; + }; + }; + }; + + dsi: dsi@14012000 { + compatible =3D "mediatek,mt8167-dsi"; + reg =3D <0 0x14012000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names =3D "engine", "digital", "hs"; + interrupts =3D ; + phys =3D <&mipi_tx>; + phy-names =3D "dphy"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi_in: endpoint { + remote-endpoint =3D <&rdma0_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi_out: endpoint { }; + }; + }; + }; + + mutex: mutex@14015000 { + compatible =3D "mediatek,mt8167-disp-mutex"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 larb0: larb@14016000 { @@ -145,6 +452,16 @@ smi_common: smi@14017000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 + mipi_tx: dsi-phy@14018000 { + compatible =3D "mediatek,mt8167-mipi-tx", "mediatek,mt2701-mipi-tx"; + reg =3D <0 0x14018000 0 0x90>; + clocks =3D <&topckgen CLK_TOP_MIPI_26M_DBG>; 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charset="utf-8" The mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index af4871de9e4c..ad10e86b161d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1301,6 +1301,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_dr= iver_data =3D { =20 static const struct of_device_id mtk_dsi_of_match[] =3D { { .compatible =3D "mediatek,mt2701-dsi", .data =3D &mt2701_dsi_driver_dat= a }, + { .compatible =3D "mediatek,mt8167-dsi", .data =3D &mt2701_dsi_driver_dat= a }, { .compatible =3D "mediatek,mt8173-dsi", .data =3D &mt8173_dsi_driver_dat= a }, { .compatible =3D "mediatek,mt8183-dsi", .data =3D &mt8183_dsi_driver_dat= a }, { .compatible =3D "mediatek,mt8186-dsi", .data =3D &mt8186_dsi_driver_dat= a }, --=20 2.43.0 From nobody Thu Mar 5 08:10:34 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12CF9313E3F for ; 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Mon, 23 Feb 2026 08:26:47 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d5463dsm19120357f8f.34.2026.02.23.08.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 08:26:46 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Val Packett , Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH v3 6/6] gpu: drm: mediatek: ovl: add specific entry for mt8167 Date: Mon, 23 Feb 2026 16:22:50 +0000 Message-ID: <5f880f1334aa93184afee3e36132ca42628821fb.1771863641.git.l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Val Packett While this configuration is otherwise identical to mt8173, according to Android kernel sources, this SoC does need smi_id_en. Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index e0236353d499..97a899e4bd99 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_drive= r_data =3D { .num_formats =3D ARRAY_SIZE(mt8173_formats), }; =20 +static const struct mtk_disp_ovl_data mt8167_ovl_driver_data =3D { + .addr =3D DISP_REG_OVL_ADDR_MT8173, + .gmc_bits =3D 8, + .layer_nr =3D 4, + .fmt_rgb565_is_0 =3D true, + .smi_id_en =3D true, + .formats =3D mt8173_formats, + .num_formats =3D ARRAY_SIZE(mt8173_formats), +}; + static const struct mtk_disp_ovl_data mt8173_ovl_driver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 8, @@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { static const struct of_device_id mtk_disp_ovl_driver_dt_match[] =3D { { .compatible =3D "mediatek,mt2701-disp-ovl", .data =3D &mt2701_ovl_driver_data}, + { .compatible =3D "mediatek,mt8167-disp-ovl", + .data =3D &mt8167_ovl_driver_data}, { .compatible =3D "mediatek,mt8173-disp-ovl", .data =3D &mt8173_ovl_driver_data}, { .compatible =3D "mediatek,mt8183-disp-ovl", --=20 2.43.0