From nobody Sat Feb 7 08:42:45 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 182CC1C84DE; Fri, 6 Feb 2026 19:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404448; cv=none; b=u6w/CeG3E/xb0RJG1rrq76inK+Xsd1Z9166tQ+/xdAkzdszXpsbWMYY4BO+7UcAD1zikE8R67fKXtCF3RGtJFM105JMCIPz/8B4/2mC0sKrmVr3ueZAELEt4wXZ6CbBYkl41BxLLB9xHfQndVAuc+qR1WaRkqvVoNzELS89wK+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404448; c=relaxed/simple; bh=adSjX2UpOkyJj/sBCT1RL8auPMy93T83fL/KA1ih2Ys=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YbZoKiSO9K4uOGCq6zUGtW7VzGxG+hCvZBtTOxVdp8XAroXhfU+vqokY9/tPAXo/ogeL+HuXavuFfXVwmkxiOkBwhqBGbXgQcTY3/PC00b9tHjkJtAZRsK9EqJy0mYCrl0SgWELCEW8ArsNfYfZexdfbeMA4WXXYPByBmB4+RsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=iNY8jJic; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="iNY8jJic" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLgsQ452354; Fri, 6 Feb 2026 14:00:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=+CnSX z86jFUOk9ZAWFBrXnEKhswUkaQmNSXH9YVarRY=; b=iNY8jJic40xGLtvmiV2cS Y8yAKzGPvo4ck3iEmU5hMgZskzv4P5HsdC5tkPY/KE4UAlgYc8CioMT/dxC2IrV0 PLJJYe/8Ton7R0EiaFYEClgwOQKxgH8pwC7Lv1EhZFJ4j2uNgfnOL00/NglEXREP 9Lw8JutopvkeGqQikt1rPzCGA3MBH/3HCWuS9IDaSvc750NGjgT0Bjhu9Ge4G88d U1mroHIKRaWj6XgRMq7hT9FoTvGu6/f7nHLywsknrXupjPMgjhnin3povxOoXIFK Ivt21gUZwJ1CNdrBqOBfaFmTdlKDoNnWJZyfbtd0FdGmpvliI2CuJT/2L/mHrd5z A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c4ygqw0xh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:00:40 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J0dYp012615 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:00:39 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:00:39 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:00:37 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:00:37 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J0NJw008942; Fri, 6 Feb 2026 14:00:26 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Conor Dooley Subject: [PATCH v8 1/8] dt-bindings: iio: adc: adi,ad4030: Reference spi-peripheral-props Date: Fri, 6 Feb 2026 16:00:23 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: vzB1QbkUkf-GyByBUP1-mKiJ3xQ-bbGq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX1HvTK4ePbVXG 2mp+XAajUusmruLKXbiPOTQObODz2oo11cY5lik2R0ZbXBezlo/FbWqC6nkLc/wHtk9C3sp5SZ5 98CrlIJlJkw3t9800TaiSBhWC9T1l1PfII9soDT4Alodhhsv7IHSqBgawFzgvSUePnAyEh9pIHh gfJxDjFZOnOYjhfr2cBDHbBBfkotP5iVqen97gprz5RMgUBNZ5X/g2KdZZNo5N8i30VC3Jaze6+ kgH5htqr2mYqX9VU0gYDVRBT8TeCZlifqPwVkKzNyTjy6WgD94xeEdfyCnizxlDsOdvHkkeaSPe VdE80XiM4rn2qS2PKJUFKbh1HFm1cuBMMyFiRvcTOshMtSUNVt74ZSjE7U/Ys4C2B+AnmKgSB86 M48taSO7JlHRbv46tcmgK0Uin/zrSEcnUl8axuoBp+GH30pIUry7emLzCqFQawAauOM/2TZds00 E+yYwONdO4RuuV+Bavw== X-Proofpoint-ORIG-GUID: vzB1QbkUkf-GyByBUP1-mKiJ3xQ-bbGq X-Authority-Analysis: v=2.4 cv=CLUnnBrD c=1 sm=1 tr=0 ts=69863a59 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gAnH3GRIAAAA:8 a=XYAwZIGsAAAA:8 a=EfQ9L3lKGMo9VN_2EekA:9 a=E8ToXWR_bxluHZ7gmE-Z:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Content-Type: text/plain; charset="utf-8" AD4030 and similar devices all connect to the system as SPI peripherals. Reference spi-peripheral-props so common SPI peripheral can be used from ad4030 dt-binding. Acked-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index e22d518135f2..29e266865805 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -20,6 +20,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf =20 +$ref: /schemas/spi/spi-peripheral-props.yaml# + properties: compatible: enum: --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DE78314A9F; Fri, 6 Feb 2026 19:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404463; cv=none; b=Jzb1uIZ3VrvIMWcMX2hEynWIdKVhLJP6uJXXh9+JG25BJGYpzFLYW8wbQAljpag3ALH15ebX7x+98faIgkfC/P7JjNUGyD6Etj+UMuHJXoOYoHkxaHngdlLPPZY6Q2jLi63aaM0kvtQIlVhg1rDKadiGuFkcgJIfia/EED78aNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404463; c=relaxed/simple; bh=vreuyB1oJMX28dl3w587JJSbrdpOaZ848torossb2pI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=miiuFUjeKFbaLZCIzC4zALiSrUhA1FGwyNHH70mz29tQZM6a8zZfPvXx5JCV12AD+20WL3881F2JfjbwPxaGGiIz6x8ximCrDltfufb6iZ5gmHdnBgjRQoScEtVMNikm0Nrox7VklJQaHwUDqk2bPOTihPAcd35Vaa4XPOLpGkM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=wWqHuYtv; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="wWqHuYtv" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLQHw3814513; Fri, 6 Feb 2026 14:00:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=/m5lg W9LZdYxB6YJs1TYPvAh9FlaVDaMUHUk0YNse/U=; b=wWqHuYtv6eDGWue/vtxqO REUAeU4sKyDxssGU5IYhO/iLwwkec8C3mzWMP87+dwKb3p9bM0/mktcCHTbb30vr GJ4GHxyYdexxkn/xv/QHXq8O+ax41HOEjAkTcXM2KZI50llVWBRojhSAfmx2ku71 ogXPpNNkwUYNybFJBDXNQG4pxP9gUGphv0Htz/Bv4YqHCK/fptACObmh5/raAC8r t93lrglmhhFxOdxeAMxIJQJP9Fm+ItPZQQ+Fu+60DrudI/cAZvKopomsMeAps8Yb rGqQOwE2IDrLfRrhJdSMBbSf4spuc67Awbx7KfVokEFxyvD1mPl7C0dMXwEI28Th g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c58722yek-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:00:56 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J0t4m012658 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:00:55 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:00:55 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:00:54 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:00:54 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J0fQL008970; Fri, 6 Feb 2026 14:00:43 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v8 2/8] Docs: iio: ad4030: Add double PWM SPI offload doc Date: Fri, 6 Feb 2026 16:00:40 -0300 Message-ID: <0dfcdf2c2018b1174f2057f0c66e336b0b550bab.1770403407.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 83HkkueDhrqSw8jeIoCEjm3emVODsmGW X-Proofpoint-GUID: 83HkkueDhrqSw8jeIoCEjm3emVODsmGW X-Authority-Analysis: v=2.4 cv=eqzSD4pX c=1 sm=1 tr=0 ts=69863a68 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=wI1k2SEZAAAA:8 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=Z7BqY8bEq__jAXHbdh4A:9 a=qcg49hLlgF0N60+LroqrWnV/Vu4=:19 a=6HWbV-4b7c7AdzY24d_u:22 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX+VVpo2ADRAP0 tAKvPFG1KKoMspTgb5YqjRnTyhAKkfXZgyaCzxj/GE+GjP8C2jIx9KGMQg6E4oveXDpj6egguTj ZWDrCrIqiEEq87ETyovzfmBBLwu8PuH7WAZOCDaE5tkCPtpyO16TQpac861MvApzLt5NUARYqVI 135/BayLzbLhiVDMR3A62bOkIobLY7i6110qUxrA7R3flarFwzVGqGQGJxuFnQengQ4Uqtqme2t K7zhDpmtvaxHuwswyedq/eXsz18uOVKeCDzky8H8iTxjU8TDXznRRDW+YvvDZuaUZ/RNU+jYupp 579zInGZWzTim38ILCyR3hpNTBKtAeawbWl7nyyqSwGkvtWQ+uofeAGe64obn6t/+TowJ9UkJmc +cEmFQPSd28LlX+p0agRRKhEYxJu7sQnQJTFmlzO+fJ1nLur0AWAKKQnun1dnuICVi/ykm2Igts wd3lPMh5R+W5yPLWmpA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Content-Type: text/plain; charset="utf-8" Document double PWM setup SPI offload wiring schema. Reviewed-by: David Lechner Signed-off-by: Marcelo Schmitt --- Documentation/iio/ad4030.rst | 39 ++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst index b57424b650a8..9caafa4148b0 100644 --- a/Documentation/iio/ad4030.rst +++ b/Documentation/iio/ad4030.rst @@ -92,6 +92,45 @@ Interleaved mode In this mode, both channels conversion results are bit interleaved one SDO= line. As such the wiring is the same as `One lane mode`_. =20 +SPI offload wiring +^^^^^^^^^^^^^^^^^^ + +.. code-block:: + + +-------------+ +-------------+ + | CNV |<-----+--| GPIO | + | | +--| PWM0 | + | | | | + | | +--| PWM1 | + | | | +-------------+ + | | +->| TRIGGER | + | CS |<--------| CS | + | | | | + | ADC | | SPI | + | | | | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | SCLK |<--------| SCLK | + +-------------+ +-------------+ + +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are require= d. +The ``pwms`` property specifies the PWM that is connected to the ADC CNV p= in. +The SPI offload will have a ``trigger-sources`` property to indicate the S= PI +offload (PWM) trigger source. For AD4030 and similar ADCs, there are two +possible data transfer zones for sample N. One of them (zone 1) starts aft= er the +data conversion for sample N is complete while the other one (zone 2) star= ts 9.8 +nanoseconds after the rising edge of CNV for sample N + 1. + +The configuration depicted in the above diagram is intended to perform data +transfer in zone 2. To achieve high sample rates while meeting ADC timing +requirements, an offset is added between the rising edges of PWM0 and PWM1= to +delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This +requires a specialized PWM controller that can provide such an offset. +The `AD4630-FMC HDL project`_, for example, can be configured to sample AD= 4030 +data during zone 2 data read window. + +.. _AD4630-FMC HDL project: https://analogdevicesinc.github.io/hdl/project= s/ad4630_fmc/index.html + SPI Clock mode -------------- =20 --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03865346E4F; Fri, 6 Feb 2026 19:01:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404520; cv=none; b=h5yCoiRJMZf76lbD4tJ9EiAjvz74Zn6ghWs/z99pNzAg02vwoZ6R5ns3RDE5c+8fRG3d7s+rCmWtQb+GSPdT4V7ji6fLr3FvR4bsAypX50EOUBH3HtaKiMf6S1T6dh5zlSkyhhex9bN3xXN3eELb43JoB5EHWUzqr5SSymSQyDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404520; c=relaxed/simple; bh=ImxRjUqLTd7MSzQV/1lQmCc0nXq3Fh00lJAgwH6Ymp0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dsPuw8SqecK6x2hKc1NUi7ItF1u9+qj0FIh5O0vizXSHNBpx9micYbq7h1BTloHazRNTthYodY1eqyy/TYrrS676XgJadJSGms0BWaPNHEd/HVSpi3NUWEH1rgNFWLtXv+M/xxyGt/Zlhh6IAykNUiGJ5PxnodI1g54B9pDv9gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=mC3BtvW6; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="mC3BtvW6" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLdNb1708598; Fri, 6 Feb 2026 14:01:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=tiW7Z i7GaUCIE0LLmX+P4SP954s+emDE6PzhOjezIYo=; b=mC3BtvW6m67XpPu1/kdDm vVb7ymzUdIQTAcP1E1MpP0tSSz528pma+EVOBTQ/J9TnM3z22JjxgiG+v3rC+Ex6 Qi+LxyUCICXcsssS3kptYQXqifD57FKPRoMMl9r55EU0ik5LeG81NTtea/fsdnCD stMlGiEozIKySkMudFnvrVmYKhYrl7wtzQkhCYjS4PAnH9jmqHUhCZpWYOyhaHib j3f9roGYntrHoP7I6yvfOpI4uNMY+iEwh3ie2bJA8501JHAUGNxANAA/nEGXnEd2 5wqA5jCCLjIaPGvYscjtGKaC0Ia+gl2nPUJQPCni1hi5m/y4voSE1e0BYCxtRZ43 Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c4q2feww9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:01:50 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J1FEn012774 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:01:15 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:01:15 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:01:15 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J0viu008975; Fri, 6 Feb 2026 14:00:59 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Conor Dooley Subject: [PATCH v8 3/8] dt-bindings: iio: adc: adi,ad4030: Add PWM Date: Fri, 6 Feb 2026 16:00:56 -0300 Message-ID: <36bf61bf9106e43798b5ccac974d97eb7176e1af.1770403407.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 1DwLy3TzzRL84oQUjBj63oqtvvnH8T06 X-Proofpoint-GUID: 1DwLy3TzzRL84oQUjBj63oqtvvnH8T06 X-Authority-Analysis: v=2.4 cv=MpVfKmae c=1 sm=1 tr=0 ts=69863a9e cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=IpJZQVW2AAAA:8 a=XYAwZIGsAAAA:8 a=gAnH3GRIAAAA:8 a=DUOLLnRY7vFq0fwDtzIA:9 a=IawgGOuG5U0WyFbmm1f5:22 a=E8ToXWR_bxluHZ7gmE-Z:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX3G/4A0n3+sQP NFwSVMlmtepMHRM2/onPtGXeoMZQadfJTCPrD0v+JxmD5bNpzkF60UgywJeAi35Vv9YL2bmCAyK PmEJJBf8Z/q6eiOxEcYskmQ3/av4U3Mc4ZGM3UeU3hhTtBd35a54XINm2KFm2PgiLlHS4Myq/mQ eewzelHgTuGs2z43qRvufL3sSV7CQRHA8JSZxeTBE8paOUNcSHX9XERPmcZ8WeTUMnK5L6jm/p0 bMQvFb0cZvTXnbzlU8447pAWkTj/qRMf9bMKh2k1fT9KzOZyGzLSXk3InPnIIdFsQggM9V6sEfN Lsf+nxDozTAJeTZLPdDpJuiDsIBnSAJcwEuxOMcS/AF1B35iZcu0xJeD0eB6qv0PoXhBI6jLfKC LDHmNjMS0f/JKCKMeoTF5NSWHJZ4lJcElyWPG3bZUtsn8tLM7CFfDM+AuFT/qaLnTItzEIx/QgL 7vh25uw5C81p+l7pJJQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Content-Type: text/plain; charset="utf-8" In setups designed for high speed data rate capture, a PWM is used to generate the CNV signal that issues data captures from the ADC. Document the use of a PWM for AD4030 and similar devices. Reviewed-by: David Lechner Acked-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 29e266865805..a135c66142df 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -72,6 +72,10 @@ properties: The Reset Input (/RST). Used for asynchronous device reset. maxItems: 1 =20 + pwms: + description: PWM signal connected to the CNV pin. + maxItems: 1 + interrupts: description: The BUSY pin is used to signal that the conversions results are avai= lable --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E255426D0B; Fri, 6 Feb 2026 19:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404522; cv=none; b=H6Pwrf0YDYVzSps3C6gQVcVkmkm/echOTfnG9Q/ejMTFYQy2j9e2dR3awqyG99yr0/zD5wH5HwhyNGNKMP+1XPy/jPQEWXkp+ZOre5FhO3RRJ77hmgl27U171EAD1NyBDUuhxbTlKRT+hyF01kYMkiFq0QBznPxCStjslCfSVQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404522; c=relaxed/simple; bh=DHmWundTSxcWzwJxHA32hKXxHl7YYLhamWTRaVyqnfw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U7WgGDCOQ9llueGIw13WjRQhiEG9qxbtCpJhygcMLAndQkr/BEFjpK7yx05YC1BF/7oHFc/6AhAvsy7xk6b6aSc2GQXRRlBPPXfdIWdcablGt/aHbZaBBXDm5xCvjDYxYoht8WrdBGZROvvT3u1qu+36ZPK2johb1whqRBAr8rQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=S2+xTDul; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="S2+xTDul" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLmng1708723; Fri, 6 Feb 2026 14:01:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=3h4bm Xnr76A55wzBt3DWeNJu8vwb3IMAtasO5q91v+I=; b=S2+xTDulGlm7tx3DGpSgi aF5RM8ZXMO86TcPhkaPgnja6c80rWy04IffEEgO/dy/iqX4lndWHYF6XjRb9seQX fLRUGUdzoZu4HzWeZCY6XyniGMCWGTtR4EH9O4VpcMSdQDp0pIdVYD2qdd9vkrF/ UiIR3ALHXr6fdfRM0/mjIY6vpkzz+EbncnxCOwS7BzsgBX9vk2/IzFdC2h4gTxxi FFos9OiXDJwJVVCxeGiPerMjk53z1a/TOOem4d6iauCuoNEhRLEKirvQtIqh4mSW Xy6WlYIXvyDm8WlBucs0wYxdcy3l1jeq3EevfHMQEJ7Gd/koK5auOR3QJufqsBdY w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c4q2fex1g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:01:56 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J1TUC012810 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:01:29 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:01:29 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:01:28 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J1ElQ009012; Fri, 6 Feb 2026 14:01:17 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Andy Shevchenko Subject: [PATCH v8 4/8] iio: adc: ad4030: Use BIT macro to improve code readability Date: Fri, 6 Feb 2026 16:01:14 -0300 Message-ID: <416b1087ea1572206238b8fabebbed738998f816.1770403407.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: MFCZ6FWXBhBCv-0cz5EKS3mXC3C6GGVY X-Proofpoint-GUID: MFCZ6FWXBhBCv-0cz5EKS3mXC3C6GGVY X-Authority-Analysis: v=2.4 cv=MpVfKmae c=1 sm=1 tr=0 ts=69863aa4 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=pGLkceISAAAA:8 a=gAnH3GRIAAAA:8 a=HwBGVG7bte8kWS4IyKsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=br55WurUj89AL1qEz8Q6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX5jx7nCDB/dTK zbmZkY2OGiI16A5BulcOKb5/VP6jdktg/ZWIh+CtU5buekejOXJYHhMevkbkaWij78jMy5lMzb2 wcjQphfPOZQ9gimkS37u/vXB7NiaYT4BxhhfIvYBvs2W6MMNSTA2qtUGKUB4okWGtv8oZKDUkCd jlaFq5teAfE4CM3frZ+B7Jr9ROn5byUaRQCsQ5Xwy/iQG7EcrmfyOvvl8uFxG9afyZdti6JjHyI Y9FG9hdAM/NwqIV6xhPu9i1AEog/Ql1PL6GLUeH09hG+v3aGwfzDi65RBMYvPC2PsTnrARO+TYn tYrgtlRzycpdE8qDXQRMFgo4wwguaKrA8Dq9SML6Mp5qCWBPAonjbaVt8PJZ/N+jhZEThK8qIsG 7ndolMxG9G1b3pPDfS1Romy1o4C3Kp6abt0kjWd1KoYr6lP6W/NXxONN7fzUSIYlqfBcwg4ks7P sjBo9CW0i1bStCKZxxA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Use BIT macro to make the list of average modes more readable. Suggested-by: Andy Shevchenko Reviewed-by: Nuno S=C3=A1 Acked-by: Andy Shevchenko Signed-off-by: Marcelo Schmitt --- Change log v7 -> v8 - Added comment in the list of available average modes to prevent regroupin= g in the future. drivers/iio/adc/ad4030.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 68446db9bef1..def3e1d01ceb 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -232,10 +232,16 @@ struct ad4030_state { .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +/* + * AD4030 can average over 2^N samples, where N =3D 1, 2, 3, ..., 16. + * We use N =3D 0 to mean no sample averaging. + */ static const int ad4030_average_modes[] =3D { - 1, 2, 4, 8, 16, 32, 64, 128, - 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, - 65536, + BIT(0), /* No sampling average */ + BIT(1), BIT(2), BIT(3), BIT(4), + BIT(5), BIT(6), BIT(7), BIT(8), + BIT(9), BIT(10), BIT(11), BIT(12), + BIT(13), BIT(14), BIT(15), BIT(16), }; =20 static int ad4030_enter_config_mode(struct ad4030_state *st) --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 489A6428847; Fri, 6 Feb 2026 19:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404523; cv=none; b=SviSr9kRVCwA80HzH057QufaM1zPLqKsRfENI5chpG6OK+VOGxEJePfmB8R5gCS/2XjFejTX0uH6hk4Sp/mXA+YMTQI0udMcHZ5NZxtHTFDExd2MVvfqlzf4QvvY2CcZxrAu8SNLMh7es/iqsxkCA9JJu0UK4bmEWj7R61xM1ic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404523; c=relaxed/simple; bh=xgat/s6MOA8GBJd7e2DihjG+2stuC0ABNhGCHkj1mtY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o9ZWLGdJBNH67jfBOq8qE3f7FvBFJbR7VKZVaWqExXcTWnwPKzFYO4a/5JELgDZcGSLwRKtr4Wj9czCG8XDzpd8trgw6SVLqA36SP47biB53zbxl24ZpIPlKP3/LYkhHV+crsFeQUf0H2QTvyYYbNV0rg1Lx/18JOCq/d5w0iog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=UKI0JeU+; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="UKI0JeU+" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLPtS1622577; Fri, 6 Feb 2026 14:01:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=x8a31 jI0cvwrTRnMdgrvxTrUyUjopzCKCmucL0jv3oc=; b=UKI0JeU+UzXi1miyu5lZz I7p4ZTQ0tBXCqC2s7OtdN5pUiDv4ZnE2gwIgrsgSyVzkHW2Srvg5BDksTvemkqTY 6b39kQ5Id8MHjlnkmsdX2SYjYLO28Jk4OAPdzbkW3NC6017NDSF4ZP9bRc0SqsVd p4L6HeKP8j3MyIa2cNbyuDSjEGMiVXA3Q5XjAQKyIFIx3veFfoWopeIPXMgJwizE TjIuFNbPp1GBdkV8HW2VxcSPmqTv+FpGgOxNZa9eP4pNhc//NhDVYahi7idhn6YV BGu9OfC4u/J9aMoEsKNqihyppFdIfnS9mnWFAdbT20p7X00vPa7XzJAit5aUpV0N Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4c5e32hrbc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:01:51 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J1onB012828 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:01:50 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:01:50 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:01:50 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J1Ycj009024; Fri, 6 Feb 2026 14:01:36 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Trevor Gamblin , Axel Haslam Subject: [PATCH v8 5/8] iio: adc: ad4030: Add SPI offload support Date: Fri, 6 Feb 2026 16:01:33 -0300 Message-ID: <315c614e65e40634251e624d73d83fdea4c51c78.1770403407.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: 1DtZ-Wfs59GtNZSHiPYhzxpnpYq_cSXS X-Proofpoint-ORIG-GUID: 1DtZ-Wfs59GtNZSHiPYhzxpnpYq_cSXS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX45enfKrlsy/X 5sxq2bF72wxlOAoXF+HuNK/tpJcb8GriNr6M+3vfFMNxuFpbndEWKYwFdJUhk9f7S6XccU+egV3 rF3T0P+//49LutkE5q6FW3ThVLRQGyfXxO8QYJ6qKMswa/WVzJk8pRbvPzIEqY96ED0AgLhcvQM sQuHEfqkdDsYbrbGWRWym2qCjqnxRIbjvUVO1d+9z87afsGbWzTwSmjSbKIqYCBuaxkgYqjdqwp EJ8ph0QYoObdFfK19FGUeP4hDmxZU2CyhdtP/ZI42J6yShNeQrMfUDyDjMIokEvOiZgtlvBtga8 F7T+Bat0ykqosiBDEsMjYkVYaDzDTpl4XKcwI0qBeMg7wY0lU+jDt8XVPLTfbyXwUTeLJpa4Sm+ SNxDzsG8cYU7DcnkcBn0R/EKalHBDzmxoLgoDYgKKB3M7c2TXB4LQYG6o0M57UHC+RTbww9PR2p isFhZVx6QylmtM2dONw== X-Authority-Analysis: v=2.4 cv=NPzYOk6g c=1 sm=1 tr=0 ts=69863a9f cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=IvjRRIT8uyO-NJnUH0kA:9 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Content-Type: text/plain; charset="utf-8" AD4030 and similar ADCs can capture data at sample rates up to 2 mega samples per second (MSPS). Not all SPI controllers are able to achieve such high throughputs and even when the controller is fast enough to run transfers at the required speed, it may be costly to the CPU to handle transfer data at such high sample rates. Add SPI offload support for AD4030 and similar ADCs to enable data capture at maximum sample rates. Reviewed-by: David Lechner Co-developed-by: Trevor Gamblin Signed-off-by: Trevor Gamblin Co-developed-by: Axel Haslam Signed-off-by: Axel Haslam Signed-off-by: Marcelo Schmitt --- Change log v7 -> v8 - Reuse dev pointer in probe(). - Refactor to check -ENODEV only once. - Grouped includes for features from IIO subsystem. - Downgraded offload_period_ns type and use DIV_ROUND_UP() instead of DIV_R= OUND_UP_ULL(). - Use HZ_PER_GHZ. drivers/iio/adc/Kconfig | 5 + drivers/iio/adc/ad4030.c | 399 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 387 insertions(+), 17 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58da8255525e..a7fe2e728d65 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -60,9 +60,14 @@ config AD4030 tristate "Analog Devices AD4030 ADC Driver" depends on SPI depends on GPIOLIB + depends on PWM select REGMAP select IIO_BUFFER + select IIO_BUFFER_DMA + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER + select SPI_OFFLOAD + select SPI_OFFLOAD_TRIGGER_PWM help Say yes here to build support for Analog Devices AD4030 and AD4630 high= speed SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index def3e1d01ceb..8f14cf58f860 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -14,15 +14,26 @@ */ =20 #include +#include #include -#include -#include -#include +#include +#include +#include +#include +#include +#include #include #include +#include #include #include #include +#include + +#include +#include +#include +#include =20 #define AD4030_REG_INTERFACE_CONFIG_A 0x00 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) @@ -111,6 +122,8 @@ #define AD4632_TCYC_NS 2000 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) #define AD4030_TRESET_COM_DELAY_MS 750 +/* Datasheet says 9.8ns, so use the closest integer value */ +#define AD4030_TQUIET_CNV_DELAY_NS 10 =20 enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, @@ -136,11 +149,13 @@ struct ad4030_chip_info { const char *name; const unsigned long *available_masks; const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; + const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; + unsigned int max_sample_rate_hz; }; =20 struct ad4030_state { @@ -153,6 +168,14 @@ struct ad4030_state { int offset_avail[3]; unsigned int avg_log2; enum ad4030_out_mode mode; + /* Offload sampling */ + struct spi_transfer offload_xfer; + struct spi_message offload_msg; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger_config offload_trigger_config; + struct pwm_device *cnv_trigger; + struct pwm_waveform cnv_wf; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -209,8 +232,9 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define AD4030_CHAN_DIFF(_idx, _scan_type) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ .info_mask_shared_by_all =3D \ + (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -232,6 +256,12 @@ struct ad4030_state { .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +#define AD4030_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + +#define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + /* * AD4030 can average over 2^N samples, where N =3D 1, 2, 3, ..., 16. * We use N =3D 0 to mean no sample averaging. @@ -244,6 +274,11 @@ static const int ad4030_average_modes[] =3D { BIT(13), BIT(14), BIT(15), BIT(16), }; =20 +static const struct spi_offload_config ad4030_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + static int ad4030_enter_config_mode(struct ad4030_state *st) { st->tx_data[0] =3D AD4030_REG_ACCESS; @@ -457,6 +492,94 @@ static int ad4030_get_chan_calibbias(struct iio_dev *i= ndio_dev, } } =20 +static void ad4030_get_sampling_freq(struct ad4030_state *st, int *freq) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + + /* + * Conversion data is fetched from the device when the offload transfer + * is triggered. Thus, provide the SPI offload trigger frequency as the + * sampling frequency. + */ + *freq =3D config->periodic.frequency_hz; +} + +static int ad4030_update_conversion_rate(struct ad4030_state *st, + unsigned int freq_hz, unsigned int avg_log2) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + unsigned int offload_period_ns, cnv_rate_hz; + struct pwm_waveform cnv_wf =3D { }; + u64 target =3D AD4030_TCNVH_NS; + u64 offload_offset_ns; + int ret; + + /* + * When averaging/oversampling over N samples, we fire the offload + * trigger once at every N pulses of the CNV signal. Conversely, the CNV + * signal needs to be N times faster than the offload trigger. Take that + * into account to correctly re-evaluate both the PWM waveform connected + * to CNV and the SPI offload trigger. + */ + cnv_rate_hz =3D freq_hz << avg_log2; + + cnv_wf.period_length_ns =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, cnv_rate_hz); + /* + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the + * rounded PWM's value is less than 10, increase the target value by 10 + * and attempt to round the waveform again, until the value is at least + * 10 ns. Use a separate variable to represent the target in case the + * rounding is severe enough to keep putting the first few results under + * the minimum 10ns condition checked by the while loop. + */ + do { + cnv_wf.duty_length_ns =3D target; + ret =3D pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); + if (ret) + return ret; + target +=3D AD4030_TCNVH_NS; + } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS); + + if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX)) + return -EINVAL; + + offload_period_ns =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_hz); + + config->periodic.frequency_hz =3D DIV_ROUND_UP(HZ_PER_GHZ, offload_period= _ns); + + /* + * The hardware does the capture on zone 2 (when SPI trigger PWM + * is used). This means that the SPI trigger signal should happen at + * tsync + tquiet_con_delay being tsync the conversion signal period + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. + * + * The PWM waveform API only supports nanosecond resolution right now, + * so round this setting to the closest available value. + */ + offload_offset_ns =3D AD4030_TQUIET_CNV_DELAY_NS; + do { + config->periodic.offset_ns =3D offload_offset_ns; + ret =3D spi_offload_trigger_validate(st->offload_trigger, config); + if (ret) + return ret; + offload_offset_ns +=3D AD4030_TQUIET_CNV_DELAY_NS; + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); + + st->cnv_wf =3D cnv_wf; + + return 0; +} + +static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq_hz) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + if (!in_range(freq_hz, 1, st->chip->max_sample_rate_hz)) + return -EINVAL; + + return ad4030_update_conversion_rate(st, freq_hz, st->avg_log2); +} + static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int gain_int, @@ -516,11 +639,30 @@ static int ad4030_set_avg_frame_len(struct iio_dev *d= ev, int avg_val) struct ad4030_state *st =3D iio_priv(dev); unsigned int avg_log2 =3D ilog2(avg_val); unsigned int last_avg_idx =3D ARRAY_SIZE(ad4030_average_modes) - 1; + int freq_hz; int ret; =20 if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) return -EINVAL; =20 + if (st->offload_trigger) { + /* + * The sample averaging and sampling frequency configurations + * are mutually dependent on each other. That's because the + * effective data sample rate is fCNV / 2^N, where N is the + * number of samples being averaged. + * + * When SPI offload is supported and we have control over the + * sample rate, the conversion start signal (CNV) and the SPI + * offload trigger frequencies must be re-evaluated so data is + * fetched only after 'avg_val' conversions. + */ + ad4030_get_sampling_freq(st, &freq_hz); + ret =3D ad4030_update_conversion_rate(st, freq_hz, avg_log2); + if (ret) + return ret; + } + ret =3D regmap_write(st->regmap, AD4030_REG_AVG, AD4030_REG_AVG_MASK_AVG_SYNC | FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2)); @@ -773,6 +915,10 @@ static int ad4030_read_raw_dispatch(struct iio_dev *in= dio_dev, *val =3D BIT(st->avg_log2); return IIO_VAL_INT; =20 + case IIO_CHAN_INFO_SAMP_FREQ: + ad4030_get_sampling_freq(st, val); + return IIO_VAL_INT; + default: return -EINVAL; } @@ -813,6 +959,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *in= dio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: return ad4030_set_avg_frame_len(indio_dev, val); =20 + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4030_set_sampling_freq(indio_dev, val); + default: return -EINVAL; } @@ -902,6 +1051,86 @@ static const struct iio_buffer_setup_ops ad4030_buffe= r_setup_ops =3D { .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 +static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + u8 offload_bpw; + + if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) + offload_bpw =3D 32; + else + offload_bpw =3D st->chip->precision_bits; + + st->offload_xfer.bits_per_word =3D offload_bpw; + st->offload_xfer.len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); +} + +static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + unsigned int reg_modes; + int ret; + + /* + * When data from 2 analog input channels is output through a single + * bus line (interleaved mode (LANE_MD =3D=3D 0b11)) and gets pushed thro= ugh + * DMA, extra hardware is required to do the de-interleaving. While we + * don't support such hardware configurations, disallow interleaved mode + * when using SPI offload. + */ + ret =3D regmap_read(st->regmap, AD4030_REG_MODES, ®_modes); + if (ret) + return ret; + + if (st->chip->num_voltage_inputs > 1 && + FIELD_GET(AD4030_REG_MODES_MASK_LANE_MODE, reg_modes) =3D=3D AD4030_L= ANE_MD_INTERLEAVED) + return -EINVAL; + + ad4030_prepare_offload_msg(indio_dev); + st->offload_msg.offload =3D st->offload; + ret =3D spi_optimize_message(st->spi, &st->offload_msg); + if (ret) + return ret; + + ret =3D pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, false); + if (ret) + goto out_unoptimize; + + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &st->offload_trigger_config); + if (ret) + goto out_pwm_disable; + + return 0; + +out_pwm_disable: + pwm_disable(st->cnv_trigger); +out_unoptimize: + spi_unoptimize_message(&st->offload_msg); + + return ret; +} + +static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + pwm_disable(st->cnv_trigger); + + spi_unoptimize_message(&st->offload_msg); + + return 0; +} + +static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4030_offload_buffer_postenable, + .predisable =3D &ad4030_offload_buffer_predisable, +}; + static int ad4030_regulators_get(struct ad4030_state *st) { struct device *dev =3D &st->spi->dev; @@ -971,6 +1200,24 @@ static int ad4030_detect_chip_info(const struct ad403= 0_state *st) return 0; } =20 +static int ad4030_pwm_get(struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + + st->cnv_trigger =3D devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnv_trigger)) + return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), + "Failed to get CNV PWM\n"); + + /* + * Preemptively disable the PWM, since we only want to enable it with + * the buffer. + */ + pwm_disable(st->cnv_trigger); + + return 0; +} + static int ad4030_config(struct ad4030_state *st) { int ret; @@ -998,6 +1245,31 @@ static int ad4030_config(struct ad4030_state *st) return 0; } =20 +static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct dma_chan *rx_dma; + + indio_dev->setup_ops =3D &ad4030_offload_buffer_setup_ops; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + + st->offload_trigger_config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1049,24 +1321,58 @@ static int ad4030_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), "Failed to get cnv gpio\n"); =20 - /* - * One hardware channel is split in two software channels when using - * common byte mode. Add one more channel for the timestamp. - */ - indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; indio_dev->name =3D st->chip->name; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->info =3D &ad4030_iio_info; - indio_dev->channels =3D st->chip->channels; indio_dev->available_scan_masks =3D st->chip->available_masks; =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - ad4030_trigger_handler, - &ad4030_buffer_setup_ops); - if (ret) - return dev_err_probe(dev, ret, - "Failed to setup triggered buffer\n"); + st->offload =3D devm_spi_offload_get(dev, spi, &ad4030_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + /* Fall back to low speed usage when no SPI offload is available. */ + if (ret =3D=3D -ENODEV) { + /* + * One hardware channel is split in two software channels when + * using common byte mode. Add one more channel for the timestamp. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; + indio_dev->channels =3D st->chip->channels; + + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4030_trigger_handler, + &ad4030_buffer_setup_ops); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup triggered buffer\n"); + } else if (ret) { + return dev_err_probe(dev, ret, "failed to get offload\n"); + } else { + /* + * Offloaded SPI transfers can't support software timestamp so + * no additional timestamp channel is added. + */ + indio_dev->num_channels =3D st->chip->num_voltage_inputs; + indio_dev->channels =3D st->chip->offload_channels; + ret =3D ad4030_spi_offload_setup(indio_dev, st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup SPI offload\n"); + + ret =3D ad4030_pwm_get(st); + if (ret) + return dev_err_probe(dev, ret, "Failed to get PWM\n"); + + /* + * Start with a slower sampling rate so there is some room for + * adjusting the sample averaging and the sampling frequency + * without hitting the maximum conversion rate. + */ + ret =3D ad4030_update_conversion_rate(st, st->chip->max_sample_rate_hz >= > 4, + st->avg_log2); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set offload samp freq\n"); + } =20 return devm_iio_device_register(dev, indio_dev); } @@ -1104,6 +1410,23 @@ static const struct iio_scan_type ad4030_24_scan_typ= es[] =3D { }, }; =20 +static const struct iio_scan_type ad4030_24_offload_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 24, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, +}; + static const struct iio_scan_type ad4030_16_scan_types[] =3D { [AD4030_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', @@ -1121,6 +1444,23 @@ static const struct iio_scan_type ad4030_16_scan_typ= es[] =3D { } }; =20 +static const struct iio_scan_type ad4030_16_offload_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 16, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, +}; + static const struct ad4030_chip_info ad4030_24_chip_info =3D { .name =3D "ad4030-24", .available_masks =3D ad4030_channel_masks, @@ -1129,10 +1469,14 @@ static const struct ad4030_chip_info ad4030_24_chip= _info =3D { AD4030_CHAN_CMO(1, 0), IIO_CHAN_SOFT_TIMESTAMP(2), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 1, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4630_16_chip_info =3D { @@ -1145,10 +1489,15 @@ static const struct ad4030_chip_info ad4630_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4630_24_chip_info =3D { @@ -1161,10 +1510,15 @@ static const struct ad4030_chip_info ad4630_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4632_16_chip_info =3D { @@ -1177,10 +1531,15 @@ static const struct ad4030_chip_info ad4632_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 static const struct ad4030_chip_info ad4632_24_chip_info =3D { @@ -1193,10 +1552,15 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 static const struct spi_device_id ad4030_id_table[] =3D { @@ -1232,3 +1596,4 @@ module_spi_driver(ad4030_driver); MODULE_AUTHOR("Esteban Blanc "); MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A4B0346E4F; Fri, 6 Feb 2026 19:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404547; cv=none; b=StUU4SHS7TodU2xQspCXfJgFQ1H5ssyR01l26TBmOYB1S/xsyAVANSLsRNgeuAlOLiyMqELEZpAiSktEuSmQrgRhFHow803DhC3Ylj0D/b2NwK2bXb+3/7s6AjKsMGTcvUgpyvB0uOSs4SV1VRzbOoxBs7Wi3r2dpv853WJ4Cp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404547; c=relaxed/simple; bh=BmK4m5noK/7P1wHQI3ng4vADWwcW+ROJUWsbUVckmqY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pRnafeECYkIANRTGOhFifawnp3D4tdeBq7mOlP/iXjRIxtGIQJx3DOy83feLa95oYZDjHFz5lSX62FDMHyrQHogDIHDXj/r/MRBOz3Zl/kaVejWyluknMzRnzU1lJ8Toe15+hHSbAnaY62GlkMYQxBs+r8ELZboQS6OO9PFDXxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=yKy5ShUI; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="yKy5ShUI" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLPbO1622554; Fri, 6 Feb 2026 14:02:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=8wXes xOkEWwDd8oNdhUhd3QCfJS6RispYE6MIsEEOm4=; b=yKy5ShUIMJo0GqLDPUo4s lGwhmWcDlEupc2+hPd/pg4am09YYZWW4BzBeKV2FQKEJODfIgs66WziZ9SpTj9Kl /2ekmi78d/f9HIsu3tkbglbpFLbMa7uNgvKv8HrgtsvwzY3lWe0f283oNRDgw5vS ONvAb0MVFg2ynszWXgbrSzSK+kRNB6AfK1hyZljDRMMe2sywcz4IudjlXdgWRVvM l2kYf6OcnJtGshekbJk3tRi+Ei9a5dmLx9uWWM9Np5ey9Ycpc+yf2nj0Uoav5Lgz Fq0mN40gIPE375/j3H20Q34B5e50ZmaHDOVjxFtEEpIFxZ/Al8na0bttKQKmHH5Z g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4c5e32hrd3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:02:15 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J2Eqp012879 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:02:14 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:02:14 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:02:14 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J1uot009033; Fri, 6 Feb 2026 14:01:59 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Conor Dooley Subject: [PATCH v8 6/8] dt-bindings: iio: adc: adi,ad4030: Add ADAQ4216 and ADAQ4224 Date: Fri, 6 Feb 2026 16:01:56 -0300 Message-ID: <61719f774d7a372819642670591c03dfcd0dc107.1770403407.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: lEaZImLUhZXSRvv8O7rFVXVRES1faO6s X-Proofpoint-ORIG-GUID: lEaZImLUhZXSRvv8O7rFVXVRES1faO6s X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX76WRVOEvjq3h MLWRnbL3onoNpuXMgHfVBokgIG8LbkqPMEa/4CH9sRWPxd1quJyzavHaignnNNsowlJEUDqkFSx l/kOtVzbi4fXfX3BMw8Arp4pV8NbZnQ07GQ7W/JzpOWav5LEiLhO4sFkKL5fuI8Ik1X97C3Hg3f MeJ+PI585NzNzrq2ZlxWM9qDDx2nEfLi83Zbt7GOJuhHaGH8JIbjMG8vyn54mBNzVPlx6fBeskq 3HzfJBH6i9+QQRXOYe5gEDD1nI6kZQX8SblEOiyneLbT1NedOWrrMJikYt6iiYoQaliiB1ode/i 28eLspZRWFD/tnF5lq80rpFDtRnc8VjLNnpaseZiM84JCohl5+e6tomWplsrjgGc31ryGV6PaHm XUYVzz3yOtIUKDQWwvRAtTuo+ek2P5+GfbM6NEugrpEUxGLjWR3FZgk4drTjMrTNb7jEarPH1pZ JvkdelJJlOXj3AgvZcg== X-Authority-Analysis: v=2.4 cv=NPzYOk6g c=1 sm=1 tr=0 ts=69863ab7 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gAnH3GRIAAAA:8 a=XYAwZIGsAAAA:8 a=0GKIfBuVSP7uAb9je7gA:9 a=E8ToXWR_bxluHZ7gmE-Z:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Content-Type: text/plain; charset="utf-8" ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a PGA (programmable gain amplifier) that scales the input signal prior to it reaching the ADC inputs. The PGA is controlled through a couple of pins (A0 and A1) that set one of four possible signal gain configurations. Reviewed-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Change log v7 -> v8 - Fixed issues reported by dt_binding_check. .../bindings/iio/adc/adi,ad4030.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index a135c66142df..08b1f9d75f89 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -19,6 +19,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4030-24-4032-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4216.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4224.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -31,6 +33,8 @@ properties: - adi,ad4630-24 - adi,ad4632-16 - adi,ad4632-24 + - adi,adaq4216 + - adi,adaq4224 =20 reg: maxItems: 1 @@ -62,6 +66,14 @@ properties: description: Internal buffered Reference. Used when ref-supply is not connected. =20 + vddh-supply: + description: + PGIA Positive Power Supply. + + vdd-fda-supply: + description: + FDA Positive Power Supply. + cnv-gpios: description: The Convert Input (CNV). It initiates the sampling conversions. @@ -72,6 +84,13 @@ properties: The Reset Input (/RST). Used for asynchronous device reset. maxItems: 1 =20 + pga-gpios: + description: + A0 and A1 pins for gain selection. For devices that have PGA configu= ration + input pins, pga-gpios should be defined. + minItems: 2 + maxItems: 2 + pwms: description: PWM signal connected to the CNV pin. maxItems: 1 @@ -113,6 +132,22 @@ allOf: properties: spi-rx-bus-width: maxItems: 1 + # ADAQ devices require a gain property to indicate how hardware PGA is s= et + - if: + properties: + compatible: + contains: + pattern: ^adi,adaq + then: + required: + - vddh-supply + - vdd-fda-supply + - pga-gpios + properties: + ref-supply: false + else: + properties: + pga-gpios: false =20 examples: - | @@ -154,3 +189,26 @@ examples: reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,adaq4216"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + vdd-5v-supply =3D <&supply_5V>; + vdd-1v8-supply =3D <&supply_1_8V>; + vio-supply =3D <&supply_1_8V>; + refin-supply =3D <&refin_sup>; + vddh-supply =3D <&vddh>; + vdd-fda-supply =3D <&vdd_fda>; + cnv-gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + pga-gpios =3D <&gpio0 2 GPIO_ACTIVE_HIGH>, + <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + }; --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F972ECE9B; Fri, 6 Feb 2026 19:02:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404565; cv=none; b=NhuhH8hLdWBfD2BrdFRhXBvbQsyC2qOd5ECFiYsMuIegjNem+QOY81hitS69IwUEkWb+NeZLc1k8vIDPK8szSjYdJ/CCUdIxNXtIY7D8f2UXLHs/aMTzp2144mQN/EOVEoekQVFrw2s/fUSO0D/pQ6/FJQxRZhXulWLTkEdOr1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404565; c=relaxed/simple; bh=vL9vkegTiLfVuSfemZhCHrumg0DjIJpxvM5bkC3OAMs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VFr8PN7jk0p9RDbRin/dn14vsvEm/naH0M7WbLVTIiWRfJUErFp4vnYTVYiLKoq3HmZoLG5kk2Lf76spRi9A9UwUONOWFxo63uVS4xNY/RfqC76USU6GUyVSXPoHKjfyXWTwsT6NeG4PfhHqTz2cHMCSOloAygxAoSM4pMOYhNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=VZM2IRBE; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="VZM2IRBE" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLZqM1708574; Fri, 6 Feb 2026 14:02:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=NpY7s T3cqfbQwGfkHkXGO7qaPGEzJE2oO3hq/hNwbL0=; b=VZM2IRBE+aTGCKtfaELge kIz0mJX/MajIm1zfIxMi/R7Cdvy4bIg28zvzftOfl1JMsOI0+DL5jYD2Rkks5tIP SNxT0d9MXqpijCq0ipVvOVpYCi7KIukSO3ZQ/2TXOCJWjKSuBlS34dU3Txl0CsaX DbSTrT8biXcD5ZRJqfrk84ZuzLn4dh2InW73T+nS1rfhzZs0n03w0w/q7uMlbwea e4yGfDtQXj3EQuYGDu6fIo0aQJJXiY6u7xXM3fTrsMGAtAZzhUqtdr+2lbEVdUKr TTHlPectKxW/nnf/fn9CxUyz5e84jVLFxtvcd3T5vBnKUZu01GIAFfZ2UphWIiG0 w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c4q2fex71-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:02:35 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J2XNM012927 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:02:34 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:02:33 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:02:33 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:02:33 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J2JtO009038; Fri, 6 Feb 2026 14:02:22 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v8 7/8] iio: adc: ad4030: Add support for ADAQ4216 and ADAQ4224 Date: Fri, 6 Feb 2026 16:02:19 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: c6ajE8cgx21Cva3BP-GzHGYF4_fdxFRm X-Proofpoint-GUID: c6ajE8cgx21Cva3BP-GzHGYF4_fdxFRm X-Authority-Analysis: v=2.4 cv=MpVfKmae c=1 sm=1 tr=0 ts=69863acb cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gAnH3GRIAAAA:8 a=vBz0w1DY-RU6HqRekHsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX8ABxjV3Py7KH s7wKty9LecOGtOrPQ8OiOTZMobMKsRVi05RLuy4jn72iYo5l+CiwXit0vxkw59T8mXLFzW0rJOY Strwd4qTQeUqOm/uzRmWcppQe6L9BqRS/kRsjkDeHkvyzAVkz07pU9RqaJkGa6IVn+Dzzf8zMMs NHbt9rjJNWQ1Zs+Whzq1TGYXXkeG/yHkm9FMJ97ckTU7DyJvQvx/RHh1hE9JipmsSMiWfG7QW1j mvmi8JzWBN/q9mR6Caae7KjlHz0xsgcSPgBpotDv80Uu1KhM+A3qEpHdIuj8GdVLPzX+op8jBCH vM9ycgCEEKWoFPA4rkywA9y8b5poZig5HB4sowi1eIMffaDpeDXYFIw4cf0IZ55XXF6ogFcz+9p WqOkIJFdJHhxE8G2UTyY8WIWjAJ5vsEpvxpK2Em/br2gBC4Ld3dzoyCH6yD5PGFUgkzT3aKqe6/ V6eB1M+y6ZFx8CzUM6Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 ADAQ4216 and ADAQ4224 are similar to AD4030, but feature a PGA circuitry that scales the analog input signal prior to it reaching the ADC. The PGA is controlled through a pair of pins (A0 and A1) whose state define the gain that is applied to the input signal. Add support for ADAQ4216 and ADAQ4224. Provide a list of PGA options through the IIO device channel scale available interface and enable control of the PGA through the channel scale interface. Signed-off-by: Marcelo Schmitt --- Change log v7 -> v8 - Minor tidy up for macro consistency and fewer blank lines. drivers/iio/adc/ad4030.c | 200 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 197 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 8f14cf58f860..3e4eb7ce6185 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -48,6 +48,8 @@ #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 +#define AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE 0x1E +#define AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE 0x1C #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -125,6 +127,10 @@ /* Datasheet says 9.8ns, so use the closest integer value */ #define AD4030_TQUIET_CNV_DELAY_NS 10 =20 +/* HARDWARE_GAIN */ +#define ADAQ4616_PGA_PINS 2 +#define ADAQ4616_PGA_GAIN_MAX_NANO (NANO * 2 / 3) + enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, AD4030_OUT_DATA_MD_16_DIFF_8_COM, @@ -145,6 +151,23 @@ enum { AD4030_SCAN_TYPE_AVG, }; =20 +/* + * Gains computed as fractions of 1000 so they can be expressed by integer= s. + */ +static const int adaq4216_hw_gains_vpv[] =3D { + 1 * MILLI / 3, /* 333 */ + 5 * MILLI / 9, /* 555 */ + 20 * MILLI / 9, /* 2222 */ + 20 * MILLI / 3, /* 6666 */ +}; + +static const int adaq4216_hw_gains_frac[][2] =3D { + { 1, 3 }, /* 1/3 V/V gain */ + { 5, 9 }, /* 5/9 V/V gain */ + { 20, 9 }, /* 20/9 V/V gain */ + { 20, 3 }, /* 20/3 V/V gain */ +}; + struct ad4030_chip_info { const char *name; const unsigned long *available_masks; @@ -152,6 +175,7 @@ struct ad4030_chip_info { const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; + bool has_pga; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; @@ -175,7 +199,11 @@ struct ad4030_state { struct spi_offload_trigger *offload_trigger; struct spi_offload_trigger_config offload_trigger_config; struct pwm_device *cnv_trigger; + size_t scale_avail_size; struct pwm_waveform cnv_wf; + unsigned int scale_avail[ARRAY_SIZE(adaq4216_hw_gains_vpv)][2]; + struct gpio_descs *pga_gpios; + unsigned int pga_index; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -232,7 +260,7 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload, _pga) { \ .info_mask_shared_by_all =3D \ (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -243,6 +271,7 @@ struct ad4030_state { BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT(IIO_CHAN_INFO_RAW), \ .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + (_pga ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ BIT(IIO_CHAN_INFO_CALIBSCALE), \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -257,10 +286,16 @@ struct ad4030_state { } =20 #define AD4030_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 0) =20 #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 0) + +#define ADAQ4216_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 1) + +#define ADAQ4216_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 1) =20 /* * AD4030 can average over 2^N samples, where N =3D 1, 2, 3, ..., 16. @@ -418,6 +453,64 @@ static const struct regmap_config ad4030_regmap_config= =3D { .max_register =3D AD4030_REG_DIG_ERR, }; =20 +static void ad4030_fill_scale_avail(struct ad4030_state *st) +{ + unsigned int mag_bits, int_part, fract_part, i; + u64 range; + + /* + * The maximum precision of differential channels is retrieved from the + * chip properties. The output code of differential channels is in two's + * complement format (i.e. signed), so the MSB is the sign bit and only + * (precision_bits - 1) bits express voltage magnitude. + */ + mag_bits =3D st->chip->precision_bits - 1; + + for (i =3D 0; i < ARRAY_SIZE(adaq4216_hw_gains_frac); i++) { + range =3D mult_frac(st->vref_uv, adaq4216_hw_gains_frac[i][1], + adaq4216_hw_gains_frac[i][0]); + /* + * If range were in mV, we would multiply it by NANO below. + * Though, range is in =C2=B5V so multiply it by MICRO only so the + * result after right shift and division scales output codes to + * millivolts. + */ + int_part =3D div_u64_rem((range * MICRO) >> mag_bits, NANO, &fract_part); + st->scale_avail[i][0] =3D int_part; + st->scale_avail[i][1] =3D fract_part; + } +} + +static int ad4030_set_pga_gain(struct ad4030_state *st) +{ + DECLARE_BITMAP(bitmap, ADAQ4616_PGA_PINS) =3D { }; + + bitmap_write(bitmap, st->pga_index, 0, ADAQ4616_PGA_PINS); + + return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); +} + +static int ad4030_set_pga(struct iio_dev *indio_dev, int gain_int, int gai= n_fract) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + unsigned int mag_bits =3D st->chip->precision_bits - 1; + u64 gain_nano, tmp; + + if (!st->pga_gpios) + return -EINVAL; + + gain_nano =3D gain_int * NANO + gain_fract; + if (!in_range(gain_nano, 1, ADAQ4616_PGA_GAIN_MAX_NANO)) + return -EINVAL; + + tmp =3D DIV_ROUND_CLOSEST_ULL(gain_nano << mag_bits, NANO); + gain_nano =3D DIV_ROUND_CLOSEST_ULL(st->vref_uv, tmp); + st->pga_index =3D find_closest(gain_nano, adaq4216_hw_gains_vpv, + ARRAY_SIZE(adaq4216_hw_gains_vpv)); + + return ad4030_set_pga_gain(st); +} + static int ad4030_get_chan_scale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -430,6 +523,13 @@ static int ad4030_get_chan_scale(struct iio_dev *indio= _dev, if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 + /* The LSB of the 8-bit common-mode data is always vref/256. */ + if (st->chip->has_pga && scan_type->realbits !=3D 8) { + *val =3D st->scale_avail[st->pga_index][0]; + *val2 =3D st->scale_avail[st->pga_index][1]; + return IIO_VAL_INT_PLUS_NANO; + } + if (chan->differential) *val =3D (st->vref_uv * 2) / MILLI; else @@ -890,6 +990,15 @@ static int ad4030_read_avail(struct iio_dev *indio_dev, *length =3D ARRAY_SIZE(ad4030_average_modes); return IIO_AVAIL_LIST; =20 + case IIO_CHAN_INFO_SCALE: + if (st->scale_avail_size =3D=3D 1) + *vals =3D (int *)st->scale_avail[st->pga_index]; + else + *vals =3D (int *)st->scale_avail; + *length =3D st->scale_avail_size * 2; /* print int and nano part */ + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_LIST; + default: return -EINVAL; } @@ -962,6 +1071,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *i= ndio_dev, case IIO_CHAN_INFO_SAMP_FREQ: return ad4030_set_sampling_freq(indio_dev, val); =20 + case IIO_CHAN_INFO_SCALE: + return ad4030_set_pga(indio_dev, val, val2); + default: return -EINVAL; } @@ -983,6 +1095,17 @@ static int ad4030_write_raw(struct iio_dev *indio_dev, return ret; } =20 +static int ad4030_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } +} + static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { @@ -1029,6 +1152,7 @@ static const struct iio_info ad4030_iio_info =3D { .read_avail =3D ad4030_read_avail, .read_raw =3D ad4030_read_raw, .write_raw =3D ad4030_write_raw, + .write_raw_get_fmt =3D &ad4030_write_raw_get_fmt, .debugfs_reg_access =3D ad4030_reg_access, .read_label =3D ad4030_read_label, .get_current_scan_type =3D ad4030_get_current_scan_type, @@ -1270,6 +1394,26 @@ static int ad4030_spi_offload_setup(struct iio_dev *= indio_dev, IIO_BUFFER_DIRECTION_IN); } =20 +static int ad4030_setup_pga(struct device *dev, struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + /* Setup GPIOs for PGA control */ + st->pga_gpios =3D devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); + if (IS_ERR(st->pga_gpios)) + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), + "Failed to get PGA gpios.\n"); + + if (st->pga_gpios->ndescs !=3D ADAQ4616_PGA_PINS) + return dev_err_probe(dev, -EINVAL, + "Expected %d GPIOs for PGA control.\n", + ADAQ4616_PGA_PINS); + + st->scale_avail_size =3D ARRAY_SIZE(adaq4216_hw_gains_vpv); + st->pga_index =3D 0; + + return 0; +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1312,6 +1456,14 @@ static int ad4030_probe(struct spi_device *spi) if (ret) return ret; =20 + if (st->chip->has_pga) { + ret =3D ad4030_setup_pga(dev, indio_dev, st); + if (ret) + return ret; + + ad4030_fill_scale_avail(st); + } + ret =3D ad4030_config(st); if (ret) return ret; @@ -1563,12 +1715,52 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 +static const struct ad4030_chip_info adaq4216_chip_info =3D { + .name =3D "adaq4216", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, + .precision_bits =3D 16, + .has_pga =3D true, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, +}; + +static const struct ad4030_chip_info adaq4224_chip_info =3D { + .name =3D "adaq4224", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, + .precision_bits =3D 24, + .has_pga =3D true, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, +}; + static const struct spi_device_id ad4030_id_table[] =3D { { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, + { "adaq4216", (kernel_ulong_t)&adaq4216_chip_info }, + { "adaq4224", (kernel_ulong_t)&adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4030_id_table); @@ -1579,6 +1771,8 @@ static const struct of_device_id ad4030_of_match[] = =3D { { .compatible =3D "adi,ad4630-24", .data =3D &ad4630_24_chip_info }, { .compatible =3D "adi,ad4632-16", .data =3D &ad4632_16_chip_info }, { .compatible =3D "adi,ad4632-24", .data =3D &ad4632_24_chip_info }, + { .compatible =3D "adi,adaq4216", .data =3D &adaq4216_chip_info }, + { .compatible =3D "adi,adaq4224", .data =3D &adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4030_of_match); --=20 2.39.2 From nobody Sat Feb 7 08:42:45 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1545E2ECE9B; Fri, 6 Feb 2026 19:03:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404587; cv=none; b=UHaOhJSnR5nTq9W5smDuRkdZnmCahBpCvGXGGpR00oo3Y0isG157cyyPqImS7qIIvxoaVRW9LJzxTvyGCtuWw1Ihcpv+4scDucHvMOINDjJyScWE5nSYyODgInW2krDEXI3upLndPv3qYkUXj8seQyntQ+fJrZVly6ZmpDqD1ko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770404587; c=relaxed/simple; bh=Bqi5X3Fl96aSAe7WAZ+QKYpT0CAaBnsogGi3nqTHNcE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Bo0vkKJzx8r2aKL3awvU829E/skolQYhNdiEBzMTTp4s0CHJeeDl98kHWbit09d7J5u2GtD4YZuzrKnWYj/fHKLSHQBXULxWf5HfO1nDYzSYXtPwf7A+PAvN4LtpONS6gpj1JjIRec12rz2x8W4rCDHU9+8hYHkr4Wy0kzctgPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=Qxt0yCYi; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="Qxt0yCYi" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 616GLdRK1708603; Fri, 6 Feb 2026 14:02:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=5VfS+ xuMEAFCuweibrGSN/E/3cX1tZ3ZL3gV6TVDKxI=; b=Qxt0yCYiqtS/pMRcKFL/Z jxheDz0xFEoJlRhQsOR5slijLJsKTasIEYEI6hseyBRd7doGOkK0ObGU1us+AnIe ySiw9xLwjIGrDSFS12GkEEKDVxgdEIn1lpA2dIOu1tokIovOMbaOcMireNuQXSsc CM9Qvc8GpZTLMghwiCNH5uwcuf45KduZtIiCh2/m1G+vez6xwxb8DCTFUS1AuBG4 /Ia9XfKaDwL8mACTAXUUgOHBCd0VKmYkEKj6MZhRs56K9PXrrRrYK/G+9wN1xZdG 4/uDYymiDrgloi1l7pmcY1YHhtpqnTDD1igc+FZVrnB/GYAEgGinMHa77M4EBVJ7 g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c4q2fex8j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Feb 2026 14:02:59 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 616J2uVU012977 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Feb 2026 14:02:56 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:02:56 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 6 Feb 2026 14:02:56 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 6 Feb 2026 14:02:56 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 616J2hlm009044; Fri, 6 Feb 2026 14:02:45 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v8 8/8] iio: adc: ad4030: Support common-mode channels with SPI offloading Date: Fri, 6 Feb 2026 16:02:42 -0300 Message-ID: <1f05069e25e9ea28db2cef9fa3856456be3c2614.1770403407.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: vLfxdeRIQH6_FmjH6sQHTQkZfeFbo1b2 X-Proofpoint-GUID: vLfxdeRIQH6_FmjH6sQHTQkZfeFbo1b2 X-Authority-Analysis: v=2.4 cv=MpVfKmae c=1 sm=1 tr=0 ts=69863ae3 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gAnH3GRIAAAA:8 a=nLo5uX867Eh3Y58ELpAA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDE0MCBTYWx0ZWRfX81hwtO20lLzB qX/7/nHp2RIrr6/dSN1B7xj8oUCRwa5yVYwE332WnsULtt1QgzdNGcNH39FT5aNdcB2mjM3qmDI n3JSQHDKab9bxlP8j+GEc8Pgse2WmYpwWH6KQl4pa5UmxRjaqeeMoG7S4eM7C5mPwTKhQSqzrng 146YyHVDGgcnVeVwSzCbn6TJrjobnypHSbvQe6RAYc0rvbOaTep1uwaw8soTSaGGHf456RmZ3mr LcWtlmL8BJxK2HK2kkThFFjGDkXhQkVAvm4s/H43reDlKMBWYlDIHXd7mWYxR9fsFqj2G+PsO1a YdW7/R1dt8Lm01UER/cCmgy5R5x3uR/Y9UmJOMDBduSDUGPn5MUb5XmUEJkffHdripkehUF16yH KtqziqQkkRDBFsQ6dA9dEu+L2rEmHWFp9ozKNzNftKL61DcH2+uFVg9mH9H3wq4y52gqR6e33MV /1cp1GmiDDk7nNPYfJg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060140 Content-Type: text/plain; charset="utf-8" AD4030 and similar devices can read common-mode voltage together with ADC sample data. When enabled, common-mode voltage data is provided in a separate IIO channel since it measures something other than the primary ADC input signal and requires separate scaling to convert to voltage units. The initial SPI offload support patch for AD4030 only provided differential channels. Now, extend the AD4030 driver to also provide common-mode IIO channels when setup with SPI offloading capability. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4030.c | 49 ++++++++++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 3e4eb7ce6185..500a68944458 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -193,7 +193,7 @@ struct ad4030_state { unsigned int avg_log2; enum ad4030_out_mode mode; /* Offload sampling */ - struct spi_transfer offload_xfer; + struct spi_transfer offload_xfer[2]; struct spi_message offload_msg; struct spi_offload *offload; struct spi_offload_trigger *offload_trigger; @@ -238,7 +238,7 @@ struct ad4030_state { * - _idx - _ch * 2 + _ch gives the channel number for this specific commo= n-mode * channel */ -#define AD4030_CHAN_CMO(_idx, _ch) { \ +#define __AD4030_CHAN_CMO(_idx, _ch, _offload) { \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_SCALE), \ .type =3D IIO_VOLTAGE, \ @@ -248,12 +248,18 @@ struct ad4030_state { .scan_index =3D (_idx), \ .scan_type =3D { \ .sign =3D 'u', \ - .storagebits =3D 8, \ + .storagebits =3D (_offload ? 32 : 8), \ .realbits =3D 8, \ - .endianness =3D IIO_BE, \ + .endianness =3D (_offload ? IIO_CPU : IIO_BE), \ }, \ } =20 +#define AD4030_CHAN_CMO(_idx, _ch) \ + __AD4030_CHAN_CMO(_idx, _ch, 0) + +#define AD4030_OFFLOAD_CHAN_CMO(_idx, _ch) \ + __AD4030_CHAN_CMO(_idx, _ch, 1) + /* * For a chip with 2 hardware channel this will be used to create 2 differ= ential * channels: @@ -1178,6 +1184,7 @@ static const struct iio_buffer_setup_ops ad4030_buffe= r_setup_ops =3D { static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) { struct ad4030_state *st =3D iio_priv(indio_dev); + bool common_mode; u8 offload_bpw; =20 if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) @@ -1185,10 +1192,22 @@ static void ad4030_prepare_offload_msg(struct iio_d= ev *indio_dev) else offload_bpw =3D st->chip->precision_bits; =20 - st->offload_xfer.bits_per_word =3D offload_bpw; - st->offload_xfer.len =3D spi_bpw_to_bytes(offload_bpw); - st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; - spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); + st->offload_xfer[0].bits_per_word =3D offload_bpw; + st->offload_xfer[0].len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer[0].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + + common_mode =3D st->mode =3D=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM || + st->mode =3D=3D AD4030_OUT_DATA_MD_16_DIFF_8_COM; + + if (common_mode) { + offload_bpw =3D 8; + st->offload_xfer[1].bits_per_word =3D offload_bpw; + st->offload_xfer[1].len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer[1].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + } + + spi_message_init_with_transfers(&st->offload_msg, st->offload_xfer, + common_mode ? 2 : 1); } =20 static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) @@ -1253,6 +1272,7 @@ static int ad4030_offload_buffer_predisable(struct ii= o_dev *indio_dev) static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = =3D { .postenable =3D &ad4030_offload_buffer_postenable, .predisable =3D &ad4030_offload_buffer_predisable, + .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 static int ad4030_regulators_get(struct ad4030_state *st) @@ -1503,7 +1523,7 @@ static int ad4030_probe(struct spi_device *spi) * Offloaded SPI transfers can't support software timestamp so * no additional timestamp channel is added. */ - indio_dev->num_channels =3D st->chip->num_voltage_inputs; + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs; indio_dev->channels =3D st->chip->offload_channels; ret =3D ad4030_spi_offload_setup(indio_dev, st); if (ret) @@ -1623,6 +1643,7 @@ static const struct ad4030_chip_info ad4030_24_chip_i= nfo =3D { }, .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(1, 0), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, .precision_bits =3D 24, @@ -1644,6 +1665,8 @@ static const struct ad4030_chip_info ad4630_16_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, .precision_bits =3D 16, @@ -1665,6 +1688,8 @@ static const struct ad4030_chip_info ad4630_24_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, .precision_bits =3D 24, @@ -1686,6 +1711,8 @@ static const struct ad4030_chip_info ad4632_16_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, .precision_bits =3D 16, @@ -1707,6 +1734,8 @@ static const struct ad4030_chip_info ad4632_24_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, .precision_bits =3D 24, @@ -1725,6 +1754,7 @@ static const struct ad4030_chip_info adaq4216_chip_in= fo =3D { }, .offload_channels =3D { ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(1, 0), }, .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, .precision_bits =3D 16, @@ -1744,6 +1774,7 @@ static const struct ad4030_chip_info adaq4224_chip_in= fo =3D { }, .offload_channels =3D { ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(1, 0), }, .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, .precision_bits =3D 24, --=20 2.39.2