From nobody Sat Feb 7 20:39:53 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EC953E95BC; Thu, 5 Feb 2026 16:47:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310040; cv=none; b=FDg5Wzoacd7ySYvqhGatkcqzZyeVYSeB8hg+YKfmuzUNcpr14DRKqjBvRp+LK29EhVyJ6QGWz+aiF5zthXVoM5Rmju3kRJ/bMLluGuFzckGQphPcUligVCLF2SgoNyZEXaiihcMJbTkjoeD7KZ4HniH78mtnkQv460/x+lXGppE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310040; c=relaxed/simple; bh=CHtw49nNn29KPoNB5Ee4FqcgWWdoXC7gFsQ88iK7e30=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f2IeLJm/O8m/4ueep86HI8u4bVwQnZaY8BeWMALOZHCTH2Rw1OnGuaT7K6WMz9vlaOyCJWx2ZjnqsQ2aepc7j4NFHx5QHW/APmfxIFveoXZlhCxoauAdj9yf7ctzS4r3OPpJD82BklL4KlroN3zk2jKNenfP/AkdVRS1s/TJ56s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=sVoz0H6y; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="sVoz0H6y" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615AbjxZ431253; Thu, 5 Feb 2026 11:47:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=3krSA PfVzD02hbcHhuttBEOo3oAthslbALLfAPomR6Y=; b=sVoz0H6yUc277QPz/sAHY OFAb00r2G+aPLGLVBTbdpRemr06jDU+hp7TkBiibcdZWYR5o7xn7MV17GfwYoX+0 Zr33cs9QY+FnNXbw0KcHMrKJXmEkthbswddllM5F2TtxuZTbpN/Kuojgm4Q9c0Wk VKtxnVeWXrMqQI4XatK5FHvq10t9jOF66GozMaTljEt4EqiO2JUvxoVKx4CkND7d vZbiwI0xyGoYApllQ0qgu5NI2/fkYm+9t51wjL5TBM4fwvEghGVl3SVFV/fvfGeB t/DDCQOCw4M4rsp0LKdf61RZomdO9FcnvO/XSDTmR6t4E3RSRMAjJ8Au7h29pjQs Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vybg3jt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:47:15 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GlEeI045147 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:47:14 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:47:14 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:47:14 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615Gl0EY032757; Thu, 5 Feb 2026 11:47:03 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Conor Dooley Subject: [PATCH v7 1/8] dt-bindings: iio: adc: adi,ad4030: Reference spi-peripheral-props Date: Thu, 5 Feb 2026 13:47:00 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: a9RYwxXFklvM2HHee_iBPxEtrGsnIufi X-Authority-Analysis: v=2.4 cv=XLI9iAhE c=1 sm=1 tr=0 ts=6984c993 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=XYAwZIGsAAAA:8 a=EfQ9L3lKGMo9VN_2EekA:9 a=E8ToXWR_bxluHZ7gmE-Z:22 X-Proofpoint-ORIG-GUID: a9RYwxXFklvM2HHee_iBPxEtrGsnIufi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfXx7Wy2TKS2zTA NMqHzRHfHOnVJYgHpxw4Rr2xucfLV0M62ygOOAk2mi4zR5shGK6bFQEHuoUS9mAtspGSTKYaglK +77RjlYMkrcwkM6TEkzE/rZv6kZ4y3ptWySEBFVSP6eb7r8X8pWqRhKGnmT1Id87+wTC0e38y+x YXSmsZYRkzhdT+cXS3yzfFYQC/DoXPnPAf1dQvUfDYBtvxXewo7FEr7dan/LIW0xD4IoEoS6QZc tMwxewkM766n58g0frKQDSFfxcj6cYB8C2A1oYMIm1DPLdWNbX4ZdSl6LDXiUP32g2h5gs9jNb5 qniFbR8MBpI0o8ISFbzSyf7wcWDuZtZbU9Nvr6MFkHl4H93T5+IRWPshjFxF6sBAmfeu0vuy3js tPPZQSs3ro3rZOXfijupkg14jpItCEck2e0WRX3bGSt8tjurCD6mnhQXJeYbIYtqz6duzwbHv4Y 3Psmxg2AnwoUW5lR0Cg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 Content-Type: text/plain; charset="utf-8" AD4030 and similar devices all connect to the system as SPI peripherals. Reference spi-peripheral-props so common SPI peripheral can be used from ad4030 dt-binding. Acked-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - No changes. Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 54e7349317b7..a8fee4062d0e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -20,6 +20,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf =20 +$ref: /schemas/spi/spi-peripheral-props.yaml# + properties: compatible: enum: --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D657F2DE702; Thu, 5 Feb 2026 16:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310078; cv=none; b=t64bO88T7wqp9KgRs0hFqNgQiPHfwmyYJVstdD0H+7nT0KYyddH/CapUzPEm8rlrJd75a7KkNGnQBVh1EnUdVBBwajpRp63loEiNQzO4QR9xQpDEuubJI4ujb8pQl9rQGxjz2AGR9SY6t10GlecnVY0M41J8Io7pehcfBwMubsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310078; c=relaxed/simple; bh=99WaiGcsEkIiIjSbOEGNEFTX3nKaer9lP7FUpEVw66E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GFBf9viNOKZMeiXUJta6zaOMfVif34zeVAV52KJm+s89eDD/mdETckLQfshBxRtLxCjMbnZ0r0GgFX6LA/1DnybA5HLvfrh5SZ7Q72hnxPie3aEaZ/+cqRThs13+Q48pkmedDKBOMhME9v/bejtU/q6zx4w9CSvUYeqlJ4APJuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=uTLXsAh+; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="uTLXsAh+" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615AbPaj1300804; Thu, 5 Feb 2026 11:47:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=V2oSh DnSUuYFygxI7sitsXZbRghfjdx6Adg4qAE9pFo=; b=uTLXsAh+hWInZfYoBDV+I wyX03QWUvcFTdohijcep/VkqPKnIZbDl0aJIa1YF0I2/9he3x0XGu38I0zAsadAy eh6ZuK87racVX/M4Zcn2Y6OEsKu9RUwsob4fZT36LAj2/ifF4GWfShvoLAF58daH bO2ZgfPOiXt5MrvSnsMoTlAk2b7P5LAXS77WTVPbJSphBQ+zNNuvD4GrrDtm3lDd oyjzVvRE0hItcWxuaOd/gTZYAnx4D/yhJJZ1MZXZxMMRUFp3FbyxqJfUFDqJm/P9 IMaariT5Jvvdd44+2uDYlQGy45IZj+2+IU60sdJMmq7CraQMm6h+VMoBvciL2DdP w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vyp7yju-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:47:52 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GlpQa045211 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:47:51 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:47:51 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:47:51 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:47:51 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615Glb9t032765; Thu, 5 Feb 2026 11:47:40 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v7 2/8] Docs: iio: ad4030: Add double PWM SPI offload doc Date: Thu, 5 Feb 2026 13:47:32 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 9HcYHJVQtcsh2YLY2oSbdVMB2acurVy6 X-Authority-Analysis: v=2.4 cv=RujI7SmK c=1 sm=1 tr=0 ts=6984c9b8 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=wI1k2SEZAAAA:8 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=Z7BqY8bEq__jAXHbdh4A:9 a=qcg49hLlgF0N60+LroqrWnV/Vu4=:19 a=6HWbV-4b7c7AdzY24d_u:22 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfX2bHs1vpY0uH0 gJGrbw05+/5OVue78/xQ3/WeMjCOdQL4h1H7uDgGX0V1S/JVQr3I+l0dxNhgbL11uUiacFuewzd WPIiivOQXtyVIoApSlnm6y3IiYpBQaOU5kssgNzY3A7dMIFKEf9Ji/wuLbR/z4bdJiE6CC3e6D2 vzAHAgvuDvyywQiCd1wAx55SUjc+IyJsxOl4EwcQR7C1hMg8D4drGkkiKbuNYhuQxKgrfDxgmVt A8PILzaH1c52dp8NejzLT1YnWY3gGdWSp8YQLyWBZLQtQx8pBgscggTMf5iiETFtQ5XVRPDNeH3 cegtmjfLA5pjLkygvaKlJ4MT9DCrEW9+7krVXydfIeVNtk1pq15l/S9GEs6n/T1WeBk4v5YdLKQ a7lJh5ajvDABxKgzK0Myy40UjhdrbhS7XuzctTka/mvri1KUjQkz/+4VVXHNWtJnWCbGJFsFb7I j8Wx2phmpX/BOnov9gg== X-Proofpoint-GUID: 9HcYHJVQtcsh2YLY2oSbdVMB2acurVy6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 Content-Type: text/plain; charset="utf-8" Document double PWM setup SPI offload wiring schema. Reviewed-by: David Lechner Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - No changes. Documentation/iio/ad4030.rst | 39 ++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst index b57424b650a8..9caafa4148b0 100644 --- a/Documentation/iio/ad4030.rst +++ b/Documentation/iio/ad4030.rst @@ -92,6 +92,45 @@ Interleaved mode In this mode, both channels conversion results are bit interleaved one SDO= line. As such the wiring is the same as `One lane mode`_. =20 +SPI offload wiring +^^^^^^^^^^^^^^^^^^ + +.. code-block:: + + +-------------+ +-------------+ + | CNV |<-----+--| GPIO | + | | +--| PWM0 | + | | | | + | | +--| PWM1 | + | | | +-------------+ + | | +->| TRIGGER | + | CS |<--------| CS | + | | | | + | ADC | | SPI | + | | | | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | SCLK |<--------| SCLK | + +-------------+ +-------------+ + +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are require= d. +The ``pwms`` property specifies the PWM that is connected to the ADC CNV p= in. +The SPI offload will have a ``trigger-sources`` property to indicate the S= PI +offload (PWM) trigger source. For AD4030 and similar ADCs, there are two +possible data transfer zones for sample N. One of them (zone 1) starts aft= er the +data conversion for sample N is complete while the other one (zone 2) star= ts 9.8 +nanoseconds after the rising edge of CNV for sample N + 1. + +The configuration depicted in the above diagram is intended to perform data +transfer in zone 2. To achieve high sample rates while meeting ADC timing +requirements, an offset is added between the rising edges of PWM0 and PWM1= to +delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This +requires a specialized PWM controller that can provide such an offset. +The `AD4630-FMC HDL project`_, for example, can be configured to sample AD= 4030 +data during zone 2 data read window. + +.. _AD4630-FMC HDL project: https://analogdevicesinc.github.io/hdl/project= s/ad4630_fmc/index.html + SPI Clock mode -------------- =20 --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B81C3A1CD; Thu, 5 Feb 2026 16:48:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310101; cv=none; b=KM5HIhd+R9SGjw0E0q3MmQbj9DNPpmfKFzyRrvNPjGU5EW5xI3Hs9HcBVRyyHSA+Va7zsmfzUhkGtBEwiWS6xSMiKHIakS7/eSmWFgYweYmT1YBkig4F4wde/YBkxePJEvundlrOBvq4cOn7ZG3Dq66Tu73ggzBhw66S2b6vXq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310101; c=relaxed/simple; bh=IVpWq22j+OgqEi0paqV0/lqXWqcFnK/b9Wv90ZJarII=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eMqHWVCkoqng1LCHGktMDRBoRwvw456Xokqlo4n4nzeQk3Z8lbImfaj8APD3/ehx4xu7LDBBs29D+kkNAd2zlyFozvTGDp0Oq8K1xYXitwsLmgIu3a2+Kx0xChcsMdeLOHG7zlBg3d6OICNgoDeQQszf3BDUGR1DUthqqjYWPbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=gAPcoDMg; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="gAPcoDMg" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615Ad3tF2523875; Thu, 5 Feb 2026 11:48:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=Q1NWt rZFJZlXNO0o85gGJO8xJvR4gCO+TflmSlxLEBM=; b=gAPcoDMg5ATuxlrqUDBMy iCOuRYnZez90yQZa4akPv7N7co/d73LCjBIba/Vn5crmweGXIolNMbBDe36K6luX AVXAefGSudTWyhBUS54ahayvrmBgO9BM1qhEP13XgJR9RuGapnEmhYm7k6/XHg9z 1zL0LqdKTC55BPSqQ3cE0vBM7Cp4nOncXsppkHrszVT7T8Z483zOmSi98+vCZJMt aTBnmQUnZ1b9LtwfpvaksEhvaeM2XwmKfKySIJdJYPOTHjJM3xFNsZeInAnjBYy6 Z+xKuEn6xsp/tCQSHAawbbRWPtCzkRT6RnzAuwlLBmxAZkhGv1wJbg3kxa/ExbB5 w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c4q2f9sg1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:48:17 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GmGKs045241 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:48:16 -0500 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:48:16 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:48:15 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:48:15 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615Gm2AX000452; Thu, 5 Feb 2026 11:48:04 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Conor Dooley Subject: [PATCH v7 3/8] dt-bindings: iio: adc: adi,ad4030: Add PWM Date: Thu, 5 Feb 2026 13:48:02 -0300 Message-ID: <085f379d4025f110ff3002e0fff493793965c453.1770309522.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: uxcBTD5d0Qk79NSn220YCLv5bP5vCOC4 X-Proofpoint-GUID: uxcBTD5d0Qk79NSn220YCLv5bP5vCOC4 X-Authority-Analysis: v=2.4 cv=MpVfKmae c=1 sm=1 tr=0 ts=6984c9d1 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=IpJZQVW2AAAA:8 a=XYAwZIGsAAAA:8 a=gAnH3GRIAAAA:8 a=DUOLLnRY7vFq0fwDtzIA:9 a=IawgGOuG5U0WyFbmm1f5:22 a=E8ToXWR_bxluHZ7gmE-Z:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNSBTYWx0ZWRfXxAdIxt+Odyre OM15+GDtSyb6MIAvGYCMErGZ4oQxfFWzqSuLqr936ApZjXcuShHAnry/+UwP1sLoaW3RkZuxsmu 8scRDZGE3Im3MzmioYBVJbJqP+O5AHmvbsmIZZ2qkhGiGdGuzZoKUSFroUOyLelpYykgOxi2dtC 3PluH1g5viU6i9GpHssM6MTjIlMdDtkxyqWcog+P12q8gLCpFCeffz0i+5C3Mip4hZusby027UC 6aWvNMEKGytH4O829nSx98jJefI+2I67nE9xD03v9YNKBrydsjWd2hDg5JBWOmFW62Sz9LUC8G9 WNALCBcshqp2ZLAQZaq9ygZtucZ0OmRsnoEbr+C7wBMrni9xhk5e0CqTL/wOLWmQB71UENEtXo8 Vhqlyjp74dhcO4uaJdydUzIK4Ee7E72PFL/mh301hTiVDQ1482NlHevSLeQUXzVHqcYo4RVSIje bQJw+Ft8hmonRQjRADg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050125 Content-Type: text/plain; charset="utf-8" In setups designed for high speed data rate capture, a PWM is used to generate the CNV signal that issues data captures from the ADC. Document the use of a PWM for AD4030 and similar devices. Reviewed-by: David Lechner Acked-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - No changes. Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index a8fee4062d0e..564b6f67a96e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -64,6 +64,10 @@ properties: The Reset Input (/RST). Used for asynchronous device reset. maxItems: 1 =20 + pwms: + description: PWM signal connected to the CNV pin. + maxItems: 1 + interrupts: description: The BUSY pin is used to signal that the conversions results are avai= lable --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A2B425CC1; Thu, 5 Feb 2026 16:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310121; cv=none; b=Dn8ksHmlliZClW9y2rvMPuLi3e9MdJzJxe8mzKMbMLDiTFr2so5gkeiTYFfnT50Mb7pkIPqvqQc9pjE1pooIuYAE/v2msRWSrdVAkwSGNJ308tKCdH36nj6mvhqX0bAl2X3z2k3XtfKbGs+I4jGitkFQUS8tTT72vjLqJrwc7to= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310121; c=relaxed/simple; bh=V4yaKPsP9CSEAqqeAJfKX7rlN03RIpLVwOC7YfDS57E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QaMp5Fn8xayK+2+0jmMvcdQc2nYKI725pj/PlGjPz8WveRm2rxQJ0aGnmNvFM87+f15DhaFprwN4gwmZhMWBEWwgcYvLzMFZ9ciTLcc31NHnsNnZ5644lSzQO2mdkxtkA3abwOGuE32In3vyxFxV89K933UrjgaDmjlpUDZk36Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=nd4cm9Q9; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="nd4cm9Q9" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615GPlHP430772; Thu, 5 Feb 2026 11:48:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=mLq9p uK+wBQbesredddGLdinAXG4E90U5prWfm9eQWk=; b=nd4cm9Q9+glzaFc7vt3W0 2cEmMUIrQVG5SNuvRY3rN2nb9UkOdWxFcp51E6qGvocZpc8OeWgZilqWXOdN1o5q eI7XgQXvJq81IJcVopWQiU90LmvwFQOX8NERcSh6/pFCKXUt7lEruL8yL96Mw5+8 QpbCFc5En93OijWd8O/IF/+kJUlmi9VRw9plStsgsT/WTXuWTN45cgz0e0Hfzbtl HIFEGHgXHBGHVVWCx+4JnOaeg7DZk7ajfpTMdZPyZPRLvP35CB5AqQcVmC0T7qTk ZS34mb7MNobPMgJIq5C3dwS/oAqNc5DO4JCL22maWt2GWO6Y/sn7M3eHhRjxj/1h w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vybg3sg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:48:36 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GmZ3w045262 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:48:35 -0500 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:48:35 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:48:35 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:48:35 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615GmJPJ000465; Thu, 5 Feb 2026 11:48:22 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Andy Shevchenko Subject: [PATCH v7 4/8] iio: adc: ad4030: Use BIT macro to improve code readability Date: Thu, 5 Feb 2026 13:48:19 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: kLQY9TXIpo9i6v4LR-yplBdjVV7Qgp9A X-Authority-Analysis: v=2.4 cv=XLI9iAhE c=1 sm=1 tr=0 ts=6984c9e4 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=pGLkceISAAAA:8 a=gAnH3GRIAAAA:8 a=HwBGVG7bte8kWS4IyKsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=br55WurUj89AL1qEz8Q6:22 X-Proofpoint-ORIG-GUID: kLQY9TXIpo9i6v4LR-yplBdjVV7Qgp9A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfXxF9OlGf/OSH8 ZM1aYZOu9e5Oapuwgs3hksVssSn4Ur6LmVEtyd2MsP4k+oNg4WPAUpLsDxpBeaT8NTQ6Y46d4Da qqbTB7JqSw+6GtcVUAZ/XD8/uxFzRXa1P8xFgHr1LcAMYU9DQ+mHAUDM7UkBOcTZhVI3guxDO4Q OuGgQcrMsr9IKXbgHt2uX3xki2GrU3hWJo6LO2gGnFNmjRiEleyNyUbb0Uj2DBF2ZXqd0mzhp5q b1r61Brx/AxoQVLYafc5+OfiiYP7UTeAvTDcuwaxP7rwFXZ42MfQC08Lvr+npRlM8marXpeoQ1H Tjef4AFJGdxvh0I1N6AL21jRw+Zzs0myItWtpj3g0eJdsJMn1Y3mFpElNAaAAo7SKMgNWIkxpAl rIIgEnpGKrH07A1J8KecGMWJF+rKdiF90+LCN6vDOu/9c6SBC5zozxJ9PsGN+gsDDdTkqP0uyq4 gRSs5MayZyH9OJZIczQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 Use BIT macro to make the list of average modes more readable. Suggested-by: Andy Shevchenko Reviewed-by: Nuno S=C3=A1 Signed-off-by: Marcelo Schmitt Acked-by: Andy Shevchenko --- Change log v6 -> v7 - No changes. drivers/iio/adc/ad4030.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 68446db9bef1..d39da4884e1d 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -232,10 +232,16 @@ struct ad4030_state { .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +/* + * AD4030 can average over 2^N samples, where N =3D 1, 2, 3, ..., 16. + * We use N =3D 0 to mean no sample averaging. + */ static const int ad4030_average_modes[] =3D { - 1, 2, 4, 8, 16, 32, 64, 128, - 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, - 65536, + BIT(0), + BIT(1), BIT(2), BIT(3), BIT(4), + BIT(5), BIT(6), BIT(7), BIT(8), + BIT(9), BIT(10), BIT(11), BIT(12), + BIT(13), BIT(14), BIT(15), BIT(16), }; =20 static int ad4030_enter_config_mode(struct ad4030_state *st) --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06DEF436374; Thu, 5 Feb 2026 16:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310147; cv=none; b=c6To2HuJAjI/E4w0BC416NitV/8oUmlFtv4Bep94Lu0FPJ7wcInEzaJNiWZTPg22dLlrqC7xJfupsROARYgJEfphJs6eqa9b6RXZJ5OKreAnwW35Qx6akwDHTj9kDeDl+Jr1M0pbTd9yUasJiJiZToxknamL83p7OGaoNyvMBSI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310147; c=relaxed/simple; bh=c9no4ptFzuuc0+NjEzr94bti/0olxy0TkTXxJ2mQcnc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oli6Ye7ii2lacoMObTJtYuW8lohNzyBM+RUSIhyKfUYej9eSSu1gucXzMdrFQpkUq6olGOWDRyjFlRFYgqD9KVhDqwiefLfgeKVlj0w0VSfilhr4jFo7NCUCgsKEYgueqPnDuOl8DvcdT+POvA8ho9bg0OwnAPR3swPIzHLi+BY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=PD04aOYv; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="PD04aOYv" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615Abtqi2446906; Thu, 5 Feb 2026 11:48:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=walYF 1pPp0gr4Y4DPxsfzVw//9QN9cZh8raLKno1yAo=; b=PD04aOYvSiUbH3RutC+GN 2mnZlQMh7xwTaYKQnVMYHAFfwAsf14Y1okxSJwY+wNLJb84k8lql4kfrGheGD8e2 Hikw60LByvhRoFWi8MrJcUDH4P9pCfoX1EtEepTHvlf7YQw6DQKRlbvYGhdxc9lH 5l8sd3VPvMRKSYHol29sQLlEh4kamnjb56LiCsDdXbMjPh6hAEsTGl8edRssnZmZ nKy7xauoGsxQD//B5yWfp6Fy1ARWV2CRF1TgHcHSlDIG+M3lloKcuJC1gwzPcsKY Y1aVq+zikpq1Jr1NalukQrxvcaUWFpus2a0Dm57Jp//PC3HzhiJnBdihQlmSW3ny g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vxvg24c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:48:58 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GmudM045285 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:48:56 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:48:56 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:48:56 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:48:56 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615Gme3H000471; Thu, 5 Feb 2026 11:48:42 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Trevor Gamblin , Axel Haslam Subject: [PATCH v7 5/8] iio: adc: ad4030: Add SPI offload support Date: Thu, 5 Feb 2026 13:48:40 -0300 Message-ID: <21652a067efac362c05f628d56b4880d07c51457.1770309522.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: V2Xom44VCiDwF_RPHefhSVsZa5xluGL0 X-Proofpoint-ORIG-GUID: V2Xom44VCiDwF_RPHefhSVsZa5xluGL0 X-Authority-Analysis: v=2.4 cv=OrdCCi/t c=1 sm=1 tr=0 ts=6984c9fa cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=IvjRRIT8uyO-NJnUH0kA:9 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfXxtFVID6UCUpe p5lF6u4kzaqEXFNQoJxbq5s5P6iUECgsFEHgf25Wa41LH+uIEtitnQjejmpyhT46h7kcCbp5Z3e nP8olYJPfZnSzHrpkapjs4o7brZbVOctmeI+xpzzvcv+aqQnK3llheVMOxLt3r+B+VaiwrXxkzI ifma3OhcTXBFVaiHNQtvOBCqaGYSChLfbp9i3cpd96cgx2toEAgP+92bUNCt4+XEkM/OqN2bdhj UN3B/93fp6j2DbFUhAxpS9go7/XTrkd0mW83eo3oQQGR537UEuL0f2lTplgEU/GEPY4XQlan2/8 acB3MZalDTHg1hnHTWbDAf2J4ev4dTym2tMiYZZJFS1XZZOdmN8LmcuOvANjX7/IILZ435zZ0H/ iLHT3zRjts1X7VC3yZacEIZEisw5TnlPUMRdR4aTkv6Bz/mxwHbOQCncj9MeR6skfkGJ9sGSIJX Gqe5ZxN7tUSdspet8uA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 Content-Type: text/plain; charset="utf-8" AD4030 and similar ADCs can capture data at sample rates up to 2 mega samples per second (MSPS). Not all SPI controllers are able to achieve such high throughputs and even when the controller is fast enough to run transfers at the required speed, it may be costly to the CPU to handle transfer data at such high sample rates. Add SPI offload support for AD4030 and similar ADCs to enable data capture at maximum sample rates. Reviewed-by: David Lechner Co-developed-by: Trevor Gamblin Signed-off-by: Trevor Gamblin Co-developed-by: Axel Haslam Signed-off-by: Axel Haslam Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - Dropped unneeded enter/exit reg config mode, simplifying offload buffer s= etup procedures. drivers/iio/adc/Kconfig | 5 + drivers/iio/adc/ad4030.c | 396 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 387 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 60038ae8dfc4..c1e55bc70ff4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -60,9 +60,14 @@ config AD4030 tristate "Analog Devices AD4030 ADC Driver" depends on SPI depends on GPIOLIB + depends on PWM select REGMAP select IIO_BUFFER + select IIO_BUFFER_DMA + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER + select SPI_OFFLOAD + select SPI_OFFLOAD_TRIGGER_PWM help Say yes here to build support for Analog Devices AD4030 and AD4630 high= speed SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index d39da4884e1d..d759fb35b977 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -14,15 +14,25 @@ */ =20 #include +#include #include +#include +#include #include #include #include +#include +#include +#include +#include +#include #include #include +#include #include #include #include +#include =20 #define AD4030_REG_INTERFACE_CONFIG_A 0x00 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) @@ -111,6 +121,8 @@ #define AD4632_TCYC_NS 2000 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) #define AD4030_TRESET_COM_DELAY_MS 750 +/* Datasheet says 9.8ns, so use the closest integer value */ +#define AD4030_TQUIET_CNV_DELAY_NS 10 =20 enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, @@ -136,11 +148,13 @@ struct ad4030_chip_info { const char *name; const unsigned long *available_masks; const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; + const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; + unsigned int max_sample_rate_hz; }; =20 struct ad4030_state { @@ -153,6 +167,14 @@ struct ad4030_state { int offset_avail[3]; unsigned int avg_log2; enum ad4030_out_mode mode; + /* Offload sampling */ + struct spi_transfer offload_xfer; + struct spi_message offload_msg; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger_config offload_trigger_config; + struct pwm_device *cnv_trigger; + struct pwm_waveform cnv_wf; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -209,8 +231,9 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define AD4030_CHAN_DIFF(_idx, _scan_type) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ .info_mask_shared_by_all =3D \ + (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -232,6 +255,12 @@ struct ad4030_state { .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +#define AD4030_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + +#define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + /* * AD4030 can average over 2^N samples, where N =3D 1, 2, 3, ..., 16. * We use N =3D 0 to mean no sample averaging. @@ -244,6 +273,11 @@ static const int ad4030_average_modes[] =3D { BIT(13), BIT(14), BIT(15), BIT(16), }; =20 +static const struct spi_offload_config ad4030_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + static int ad4030_enter_config_mode(struct ad4030_state *st) { st->tx_data[0] =3D AD4030_REG_ACCESS; @@ -457,6 +491,96 @@ static int ad4030_get_chan_calibbias(struct iio_dev *i= ndio_dev, } } =20 +static void ad4030_get_sampling_freq(struct ad4030_state *st, int *freq) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + + /* + * Conversion data is fetched from the device when the offload transfer + * is triggered. Thus, provide the SPI offload trigger frequency as the + * sampling frequency. + */ + *freq =3D config->periodic.frequency_hz; +} + +static int ad4030_update_conversion_rate(struct ad4030_state *st, + unsigned int freq_hz, unsigned int avg_log2) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + struct pwm_waveform cnv_wf =3D { }; + u64 target =3D AD4030_TCNVH_NS; + unsigned int cnv_rate_hz; + u64 offload_period_ns; + u64 offload_offset_ns; + int ret; + + /* + * When averaging/oversampling over N samples, we fire the offload + * trigger once at every N pulses of the CNV signal. Conversely, the CNV + * signal needs to be N times faster than the offload trigger. Take that + * into account to correctly re-evaluate both the PWM waveform connected + * to CNV and the SPI offload trigger. + */ + cnv_rate_hz =3D freq_hz << avg_log2; + + cnv_wf.period_length_ns =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, cnv_rate_hz); + /* + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the + * rounded PWM's value is less than 10, increase the target value by 10 + * and attempt to round the waveform again, until the value is at least + * 10 ns. Use a separate variable to represent the target in case the + * rounding is severe enough to keep putting the first few results under + * the minimum 10ns condition checked by the while loop. + */ + do { + cnv_wf.duty_length_ns =3D target; + ret =3D pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); + if (ret) + return ret; + target +=3D AD4030_TCNVH_NS; + } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS); + + if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX)) + return -EINVAL; + + offload_period_ns =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_hz); + + config->periodic.frequency_hz =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, + offload_period_ns); + + /* + * The hardware does the capture on zone 2 (when SPI trigger PWM + * is used). This means that the SPI trigger signal should happen at + * tsync + tquiet_con_delay being tsync the conversion signal period + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. + * + * The PWM waveform API only supports nanosecond resolution right now, + * so round this setting to the closest available value. + */ + offload_offset_ns =3D AD4030_TQUIET_CNV_DELAY_NS; + do { + config->periodic.offset_ns =3D offload_offset_ns; + ret =3D spi_offload_trigger_validate(st->offload_trigger, config); + if (ret) + return ret; + offload_offset_ns +=3D AD4030_TQUIET_CNV_DELAY_NS; + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); + + st->cnv_wf =3D cnv_wf; + + return 0; +} + +static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq_hz) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + if (!in_range(freq_hz, 1, st->chip->max_sample_rate_hz)) + return -EINVAL; + + return ad4030_update_conversion_rate(st, freq_hz, st->avg_log2); +} + static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int gain_int, @@ -516,11 +640,30 @@ static int ad4030_set_avg_frame_len(struct iio_dev *d= ev, int avg_val) struct ad4030_state *st =3D iio_priv(dev); unsigned int avg_log2 =3D ilog2(avg_val); unsigned int last_avg_idx =3D ARRAY_SIZE(ad4030_average_modes) - 1; + int freq_hz; int ret; =20 if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) return -EINVAL; =20 + if (st->offload_trigger) { + /* + * The sample averaging and sampling frequency configurations + * are mutually dependent on each other. That's because the + * effective data sample rate is fCNV / 2^N, where N is the + * number of samples being averaged. + * + * When SPI offload is supported and we have control over the + * sample rate, the conversion start signal (CNV) and the SPI + * offload trigger frequencies must be re-evaluated so data is + * fetched only after 'avg_val' conversions. + */ + ad4030_get_sampling_freq(st, &freq_hz); + ret =3D ad4030_update_conversion_rate(st, freq_hz, avg_log2); + if (ret) + return ret; + } + ret =3D regmap_write(st->regmap, AD4030_REG_AVG, AD4030_REG_AVG_MASK_AVG_SYNC | FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2)); @@ -773,6 +916,10 @@ static int ad4030_read_raw_dispatch(struct iio_dev *in= dio_dev, *val =3D BIT(st->avg_log2); return IIO_VAL_INT; =20 + case IIO_CHAN_INFO_SAMP_FREQ: + ad4030_get_sampling_freq(st, val); + return IIO_VAL_INT; + default: return -EINVAL; } @@ -813,6 +960,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *in= dio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: return ad4030_set_avg_frame_len(indio_dev, val); =20 + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4030_set_sampling_freq(indio_dev, val); + default: return -EINVAL; } @@ -902,6 +1052,86 @@ static const struct iio_buffer_setup_ops ad4030_buffe= r_setup_ops =3D { .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 +static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + u8 offload_bpw; + + if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) + offload_bpw =3D 32; + else + offload_bpw =3D st->chip->precision_bits; + + st->offload_xfer.bits_per_word =3D offload_bpw; + st->offload_xfer.len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); +} + +static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + unsigned int reg_modes; + int ret; + + /* + * When data from 2 analog input channels is output through a single + * bus line (interleaved mode (LANE_MD =3D=3D 0b11)) and gets pushed thro= ugh + * DMA, extra hardware is required to do the de-interleaving. While we + * don't support such hardware configurations, disallow interleaved mode + * when using SPI offload. + */ + ret =3D regmap_read(st->regmap, AD4030_REG_MODES, ®_modes); + if (ret) + return ret; + + if (st->chip->num_voltage_inputs > 1 && + FIELD_GET(AD4030_REG_MODES_MASK_LANE_MODE, reg_modes) =3D=3D AD4030_L= ANE_MD_INTERLEAVED) + return -EINVAL; + + ad4030_prepare_offload_msg(indio_dev); + st->offload_msg.offload =3D st->offload; + ret =3D spi_optimize_message(st->spi, &st->offload_msg); + if (ret) + return ret; + + ret =3D pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, false); + if (ret) + goto out_unoptimize; + + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &st->offload_trigger_config); + if (ret) + goto out_pwm_disable; + + return 0; + +out_pwm_disable: + pwm_disable(st->cnv_trigger); +out_unoptimize: + spi_unoptimize_message(&st->offload_msg); + + return ret; +} + +static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + pwm_disable(st->cnv_trigger); + + spi_unoptimize_message(&st->offload_msg); + + return 0; +} + +static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4030_offload_buffer_postenable, + .predisable =3D &ad4030_offload_buffer_predisable, +}; + static int ad4030_regulators_get(struct ad4030_state *st) { struct device *dev =3D &st->spi->dev; @@ -971,6 +1201,24 @@ static int ad4030_detect_chip_info(const struct ad403= 0_state *st) return 0; } =20 +static int ad4030_pwm_get(struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + + st->cnv_trigger =3D devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnv_trigger)) + return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), + "Failed to get CNV PWM\n"); + + /* + * Preemptively disable the PWM, since we only want to enable it with + * the buffer. + */ + pwm_disable(st->cnv_trigger); + + return 0; +} + static int ad4030_config(struct ad4030_state *st) { int ret; @@ -998,6 +1246,31 @@ static int ad4030_config(struct ad4030_state *st) return 0; } =20 +static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct dma_chan *rx_dma; + + indio_dev->setup_ops =3D &ad4030_offload_buffer_setup_ops; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + + st->offload_trigger_config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1049,24 +1322,60 @@ static int ad4030_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), "Failed to get cnv gpio\n"); =20 - /* - * One hardware channel is split in two software channels when using - * common byte mode. Add one more channel for the timestamp. - */ - indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; indio_dev->name =3D st->chip->name; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->info =3D &ad4030_iio_info; - indio_dev->channels =3D st->chip->channels; indio_dev->available_scan_masks =3D st->chip->available_masks; =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - ad4030_trigger_handler, - &ad4030_buffer_setup_ops); - if (ret) - return dev_err_probe(dev, ret, - "Failed to setup triggered buffer\n"); + st->offload =3D devm_spi_offload_get(dev, spi, &ad4030_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "failed to get offload\n"); + + /* Fall back to low speed usage when no SPI offload is available. */ + if (ret =3D=3D -ENODEV) { + /* + * One hardware channel is split in two software channels when + * using common byte mode. Add one more channel for the timestamp. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; + indio_dev->channels =3D st->chip->channels; + + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4030_trigger_handler, + &ad4030_buffer_setup_ops); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup triggered buffer\n"); + } else { + /* + * Offloaded SPI transfers can't support software timestamp so + * no additional timestamp channel is added. + */ + indio_dev->num_channels =3D st->chip->num_voltage_inputs; + indio_dev->channels =3D st->chip->offload_channels; + ret =3D ad4030_spi_offload_setup(indio_dev, st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup SPI offload\n"); + + ret =3D ad4030_pwm_get(st); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to get PWM: %d\n", ret); + + /* + * Start with a slower sampling rate so there is some room for + * adjusting the sample averaging and the sampling frequency + * without hitting the maximum conversion rate. + */ + ret =3D ad4030_update_conversion_rate(st, st->chip->max_sample_rate_hz >= > 4, + st->avg_log2); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to set offload samp freq\n"); + } =20 return devm_iio_device_register(dev, indio_dev); } @@ -1104,6 +1413,23 @@ static const struct iio_scan_type ad4030_24_scan_typ= es[] =3D { }, }; =20 +static const struct iio_scan_type ad4030_24_offload_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 24, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, +}; + static const struct iio_scan_type ad4030_16_scan_types[] =3D { [AD4030_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', @@ -1121,6 +1447,23 @@ static const struct iio_scan_type ad4030_16_scan_typ= es[] =3D { } }; =20 +static const struct iio_scan_type ad4030_16_offload_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 16, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, +}; + static const struct ad4030_chip_info ad4030_24_chip_info =3D { .name =3D "ad4030-24", .available_masks =3D ad4030_channel_masks, @@ -1129,10 +1472,14 @@ static const struct ad4030_chip_info ad4030_24_chip= _info =3D { AD4030_CHAN_CMO(1, 0), IIO_CHAN_SOFT_TIMESTAMP(2), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 1, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4630_16_chip_info =3D { @@ -1145,10 +1492,15 @@ static const struct ad4030_chip_info ad4630_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4630_24_chip_info =3D { @@ -1161,10 +1513,15 @@ static const struct ad4030_chip_info ad4630_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4632_16_chip_info =3D { @@ -1177,10 +1534,15 @@ static const struct ad4030_chip_info ad4632_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 static const struct ad4030_chip_info ad4632_24_chip_info =3D { @@ -1193,10 +1555,15 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 static const struct spi_device_id ad4030_id_table[] =3D { @@ -1232,3 +1599,4 @@ module_spi_driver(ad4030_driver); MODULE_AUTHOR("Esteban Blanc "); MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FE172E8B97; Thu, 5 Feb 2026 16:49:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310158; cv=none; b=o3q+YvdS7CEol7pHNSNOmCYZrV/VxtJvnilGH1OKAcXTLLH/Mzt8iSKPeuTcpXotmzgADFnaAaITA03K+g5rJauaph8P9mSrY348Md1xKdUNtQpUFp2jLrw053UxYG4r2pgyXBVzP3rA5pNDXkzpog1TeBy8bTQnyO3wwCCDPuI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310158; c=relaxed/simple; bh=JKbY4Ot8EwdmxnXGQ1OMsim4olPBW19f3asZVi7jBcQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iVd15MT1Nhxm4s2+4Xa+qymzvrGSIX/D+TOvKonh22i/WPekex/E5yDB0hB4dDIHZ5JJVqMQh64gMBgrW0XSwiBJ4K9n2HWx8DMbc3XPJvnkFsT5mywlBq5SBGd9SHKZHJUVnl8UJ3eLxnoVf5tYMTIGPQlOTb79Bos97ke2eo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=ddol/KmS; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="ddol/KmS" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615AbOLg1300793; Thu, 5 Feb 2026 11:49:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=CwpX+ bmkqq7gY2+EH+WWvGDmKCPAqh1CBN56R9gJsQw=; b=ddol/KmS+FB4YZbkpXpe9 BproJI5uxl5xQaBN4ydtcSAZjynNptt6ZeimhnKaKMgzefVIC90P9it53ht102ig zl5yJw++JR2EmLaG9CP09BNvCxEmwggi+EKN511XFiBjA75gxCg6Qijh6W7UTCaC xcYWlbYXvWxqTwaJDGbQSRKDSMJZ/bSfNpVbxfmGT5EHjTnpT3UkiadbG3waQrwH K4laGgwiTi05ckuwa0ax77iSmOlsFyIOGo9OI/FugSjlaGSKacbCDuoCMewbSyb9 HTfdXDXnYkc2XbaCxoADRSzU1o3c2IyjLD686Wrm4Sg6mgUCUnmsneXXZ2dhm3SJ A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vyp7yqt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:49:13 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GnC15045303 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:49:12 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:49:12 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:49:12 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615GmujL000475; Thu, 5 Feb 2026 11:48:58 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , Conor Dooley Subject: [PATCH v7 6/8] dt-bindings: iio: adc: adi,ad4030: Add ADAQ4216 and ADAQ4224 Date: Thu, 5 Feb 2026 13:48:55 -0300 Message-ID: <4b879f53450e87739afc0dbd832dab5a3f83efb1.1770309522.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: XYl6-tyI8XX8bd1GxuNmBjeEp13_lmgn X-Authority-Analysis: v=2.4 cv=RujI7SmK c=1 sm=1 tr=0 ts=6984ca09 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=XYAwZIGsAAAA:8 a=0GKIfBuVSP7uAb9je7gA:9 a=E8ToXWR_bxluHZ7gmE-Z:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfX5U52/mIlvy+T BcX26LTvMV7+X3Btq4HyOiS4Liq00XPh0EObU4us5Lpdk5Lyi5dnJMRwVUTlkiL5oit7D/9zv9X cNoWOavBUDZuFzTqd0kfwpn7FjcwvGODiDDfZR6mk/NCXgOPFfPuREX5AOCJMDTYAhMusHyY7fz fsFZe9/ltqS77u+3Cikn0eZTIZY2DjPWSHCL9RxANfJh/cZl7c/LWGW5gYRYzPKNnYvaPti0viN 3H5M/gu4ai77yRbZ6A1MjDYJYyy7/xanNXWr29amUX5ciUckqXzTj9iBjek+C2fAzXysD8BTjBQ 6+dKD4Tp1u+C2ve3GEm92IZWNXi9rhHoJmUuIX4l5Zm5NZSvLWRj6oz12nWpqaw4wyITD2sQvPn mPEROADN57SNDtX3sadM9+QWMPtBr0IS7FqKCkBBv2uUP4vfiC2sSYHoMo3UC1HbaxbbXYoh6Bd yPfTsvb/p7goquztK9Q== X-Proofpoint-GUID: XYl6-tyI8XX8bd1GxuNmBjeEp13_lmgn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 Content-Type: text/plain; charset="utf-8" ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a PGA (programmable gain amplifier) that scales the input signal prior to it reaching the ADC inputs. The PGA is controlled through a couple of pins (A0 and A1) that set one of four possible signal gain configurations. Reviewed-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - No changes. .../bindings/iio/adc/adi,ad4030.yaml | 70 +++++++++++++++++-- 1 file changed, 65 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 564b6f67a96e..3890cd4ba93e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -19,6 +19,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4030-24-4032-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4216.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4224.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -31,6 +33,8 @@ properties: - adi,ad4630-24 - adi,ad4632-16 - adi,ad4632-24 + - adi,adaq4216 + - adi,adaq4224 =20 reg: maxItems: 1 @@ -54,6 +58,14 @@ properties: description: Internal buffered Reference. Used when ref-supply is not connected. =20 + vddh-supply: + description: + PGIA Positive Power Supply. + + vdd-fda-supply: + description: + FDA Positive Power Supply. + cnv-gpios: description: The Convert Input (CNV). It initiates the sampling conversions. @@ -64,6 +76,13 @@ properties: The Reset Input (/RST). Used for asynchronous device reset. maxItems: 1 =20 + pga-gpios: + description: + A0 and A1 pins for gain selection. For devices that have PGA configu= ration + input pins, pga-gpios should be defined. + minItems: 2 + maxItems: 2 + pwms: description: PWM signal connected to the CNV pin. maxItems: 1 @@ -86,11 +105,29 @@ required: - vio-supply - cnv-gpios =20 -oneOf: - - required: - - ref-supply - - required: - - refin-supply +allOf: + - oneOf: + - required: + - ref-supply + - required: + - refin-supply + # ADAQ devices require a gain property to indicate how hardware PGA is s= et + - if: + properties: + compatible: + contains: + pattern: ^adi,adaq + then: + required: + - vddh-supply + - vdd-fda-supply + - pga-gpios + properties: + ref-supply: false + else: + properties: + pga-gpios: false + =20 unevaluatedProperties: false =20 @@ -114,3 +151,26 @@ examples: reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,adaq4216"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + vdd-5v-supply =3D <&supply_5V>; + vdd-1v8-supply =3D <&supply_1_8V>; + vio-supply =3D <&supply_1_8V>; + refin-supply =3D <&refin_sup>; + vddh-supply =3D <&vddh>; + vdd-fda-supply =3D <&vdd_fda>; + cnv-gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + pga-gpios =3D <&gpio0 2 GPIO_ACTIVE_HIGH>, + <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + }; +... --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74A8B43C042; Thu, 5 Feb 2026 16:49:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310181; cv=none; b=e9RvWtJngnE5Cj+N7PERJyvt7y8dCR+suU62K0Ns3TWiQPllGnEXO1KAZZKT7MJiXmRSZ30GbTsJM3oYgKVQdP44owHCC61QuXEB2aMTFuisTJYjQdlAgSl+CSsn4cBMN01FemjwXYyuZGJunwGlYytO1X9FrydscNfB4cvpnmo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310181; c=relaxed/simple; bh=MDnZ6+BU5ks1nIgKOiCHubdsXuxaY4uhwv1KoprDnDE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WmdBnYBKBAi+eXV9yHHl4fKDxfKRsQhb7PU70eU0e+4ya7NzO+yoQqj3pb/cqW7MAPl+pWtO3OFPCurmGToW1rAltzcINk5iJw5epU6DyTGaEXDuH1dXPf5Jlk3tI9L4Dam9q6MmqlL0pNGTuln6JMrj6CglB6kyQcEn/TuhyHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=Kk39zYQd; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="Kk39zYQd" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615GT6ha2446426; Thu, 5 Feb 2026 11:49:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=YvxOR hBvsgk/kLoQUyaITC4GDcI0PUDlmrQXHv7K3LU=; b=Kk39zYQdfQTN5kfNz1ddi +qOTFOJRLRkE55yfkdCimHCiIVAObDO6BUeZ57nE0mm9KUCYC9+4WELQiJLvYTiG o//SNyvnrYQYNU8GmopqG0H0ds9QW7rwpNGazw+gthIIeZYRu8xuOVhYe/3oCpUs 3Kz0DRFuyuFcI+0IbiroXuAuvqZoeHRWdl6MfcUHQUUJvRlkCDqKr8ryp5YEslSu PUaXAzWK7pd9Fh2HTel6dgu8qYAEs/yMApanSb/djE1uIiMPofjR6D0HntIoBc2w PaCfWqBcg0angDDEEoWAik/O/aZk4vPdvdHl8GafRc22sHsoJs/Fobz/9yb30rux Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vxvg27k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:49:36 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GnZWu045344 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:49:35 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:49:35 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:49:35 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:49:35 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615GnKIW000481; Thu, 5 Feb 2026 11:49:22 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v7 7/8] iio: adc: ad4030: Add support for ADAQ4216 and ADAQ4224 Date: Thu, 5 Feb 2026 13:49:19 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: OlYwJEvTriwMQUWVMO687hSVyL41ctgk X-Proofpoint-ORIG-GUID: OlYwJEvTriwMQUWVMO687hSVyL41ctgk X-Authority-Analysis: v=2.4 cv=OrdCCi/t c=1 sm=1 tr=0 ts=6984ca20 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=vBz0w1DY-RU6HqRekHsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfXw2vUPoOUTkB0 DM8T8Ht/509sFHZkDfej4ZyxgyPnH9KUpoOnS9EBLKWxiQxdssygilrfD4TWD9Uc1fDEXXPkPvm 7XL0hTUSm78QPqzHCD5NCBUNu6l71DLi5uUSK4d78QlixBUrFz+KsW3sEIXJa1+VyCzUbSmBW54 CaOlRbaqajiWAJ4c3kpnkRhUZv9vfIcgkFFhYo14H28WLFqiFid1gw+YlWpCL//M7d9j/9j1cTE 0g89mnGo1IuUjYRZxwIt5ZZQ+kIJjyUrkadJ8rQAN8Uclrt66a3wUDrdKnk1MNXEudY5aaH9uYy EfYnTvu37XuWuU6q8VCC+o4WBubs4A/jfh6yUA5ewzV/yLFAfXtkZSlF2nZ0jtMvKqC2YNgriK3 nO6Bqfjh515PlwesrMTYRErOIoyJEOTTf4gfE5mP2KcK7rYdlkXkQqm/nPYRnwMgaA+PVA1YqUs AZwIU6x6bzesfgVvpHQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 ADAQ4216 and ADAQ4224 are similar to AD4030, but feature a PGA circuitry that scales the analog input signal prior to it reaching the ADC. The PGA is controlled through a pair of pins (A0 and A1) whose state define the gain that is applied to the input signal. Add support for ADAQ4216 and ADAQ4224. Provide a list of PGA options through the IIO device channel scale available interface and enable control of the PGA through the channel scale interface. Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - No changes. drivers/iio/adc/ad4030.c | 201 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 198 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index d759fb35b977..4f521fe787d9 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -47,6 +47,8 @@ #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 +#define AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE 0x1E +#define AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE 0x1C #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -124,6 +126,10 @@ /* Datasheet says 9.8ns, so use the closest integer value */ #define AD4030_TQUIET_CNV_DELAY_NS 10 =20 +/* HARDWARE_GAIN */ +#define ADAQ4616_PGA_PINS 2 +#define ADAQ4616_PGA_GAIN_MAX_NANO (NANO * 2 / 3) + enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, AD4030_OUT_DATA_MD_16_DIFF_8_COM, @@ -144,6 +150,23 @@ enum { AD4030_SCAN_TYPE_AVG, }; =20 +/* + * Gains computed as fractions of 1000 so they can be expressed by integer= s. + */ +static const int adaq4216_hw_gains_vpv[] =3D { + MILLI / 3, /* 333 */ + 5 * MILLI / 9, /* 555 */ + 20 * MILLI / 9, /* 2222 */ + 20 * MILLI / 3, /* 6666 */ +}; + +static const int adaq4216_hw_gains_frac[][2] =3D { + { 1, 3 }, /* 1/3 V/V gain */ + { 5, 9 }, /* 5/9 V/V gain */ + { 20, 9 }, /* 20/9 V/V gain */ + { 20, 3 }, /* 20/3 V/V gain */ +}; + struct ad4030_chip_info { const char *name; const unsigned long *available_masks; @@ -151,6 +174,7 @@ struct ad4030_chip_info { const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; + bool has_pga; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; @@ -174,7 +198,11 @@ struct ad4030_state { struct spi_offload_trigger *offload_trigger; struct spi_offload_trigger_config offload_trigger_config; struct pwm_device *cnv_trigger; + size_t scale_avail_size; struct pwm_waveform cnv_wf; + unsigned int scale_avail[ARRAY_SIZE(adaq4216_hw_gains_vpv)][2]; + struct gpio_descs *pga_gpios; + unsigned int pga_index; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -231,7 +259,7 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload, _pga) { \ .info_mask_shared_by_all =3D \ (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -242,6 +270,7 @@ struct ad4030_state { BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT(IIO_CHAN_INFO_RAW), \ .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + (_pga ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ BIT(IIO_CHAN_INFO_CALIBSCALE), \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -256,10 +285,16 @@ struct ad4030_state { } =20 #define AD4030_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 0) =20 #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 0) + +#define ADAQ4216_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 1) + +#define ADAQ4216_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 1) =20 /* * AD4030 can average over 2^N samples, where N =3D 1, 2, 3, ..., 16. @@ -417,6 +452,65 @@ static const struct regmap_config ad4030_regmap_config= =3D { .max_register =3D AD4030_REG_DIG_ERR, }; =20 +static void ad4030_fill_scale_avail(struct ad4030_state *st) +{ + unsigned int mag_bits, int_part, fract_part, i; + u64 range; + + /* + * The maximum precision of differential channels is retrieved from the + * chip properties. The output code of differential channels is in two's + * complement format (i.e. signed), so the MSB is the sign bit and only + * (precision_bits - 1) bits express voltage magnitude. + */ + mag_bits =3D st->chip->precision_bits - 1; + + for (i =3D 0; i < ARRAY_SIZE(adaq4216_hw_gains_frac); i++) { + range =3D mult_frac(st->vref_uv, adaq4216_hw_gains_frac[i][1], + adaq4216_hw_gains_frac[i][0]); + /* + * If range were in mV, we would multiply it by NANO below. + * Though, range is in =C2=B5V so multiply it by MICRO only so the + * result after right shift and division scales output codes to + * millivolts. + */ + int_part =3D div_u64_rem((range * MICRO) >> mag_bits, NANO, &fract_part); + st->scale_avail[i][0] =3D int_part; + st->scale_avail[i][1] =3D fract_part; + } +} + +static int ad4030_set_pga_gain(struct ad4030_state *st) +{ + DECLARE_BITMAP(bitmap, ADAQ4616_PGA_PINS) =3D { }; + + bitmap_write(bitmap, st->pga_index, 0, ADAQ4616_PGA_PINS); + + return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); +} + +static int ad4030_set_pga(struct iio_dev *indio_dev, int gain_int, int gai= n_fract) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + unsigned int mag_bits =3D st->chip->precision_bits - 1; + u64 gain_nano, tmp; + + if (!st->pga_gpios) + return -EINVAL; + + gain_nano =3D gain_int * NANO + gain_fract; + + if (!in_range(gain_nano, 1, ADAQ4616_PGA_GAIN_MAX_NANO)) + return -EINVAL; + + tmp =3D DIV_ROUND_CLOSEST_ULL(gain_nano << mag_bits, NANO); + gain_nano =3D DIV_ROUND_CLOSEST_ULL(st->vref_uv, tmp); + st->pga_index =3D find_closest(gain_nano, adaq4216_hw_gains_vpv, + ARRAY_SIZE(adaq4216_hw_gains_vpv)); + + return ad4030_set_pga_gain(st); +} + static int ad4030_get_chan_scale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -429,6 +523,13 @@ static int ad4030_get_chan_scale(struct iio_dev *indio= _dev, if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 + /* The LSB of the 8-bit common-mode data is always vref/256. */ + if (st->chip->has_pga && scan_type->realbits !=3D 8) { + *val =3D st->scale_avail[st->pga_index][0]; + *val2 =3D st->scale_avail[st->pga_index][1]; + return IIO_VAL_INT_PLUS_NANO; + } + if (chan->differential) *val =3D (st->vref_uv * 2) / MILLI; else @@ -891,6 +992,15 @@ static int ad4030_read_avail(struct iio_dev *indio_dev, *length =3D ARRAY_SIZE(ad4030_average_modes); return IIO_AVAIL_LIST; =20 + case IIO_CHAN_INFO_SCALE: + if (st->scale_avail_size =3D=3D 1) + *vals =3D (int *)st->scale_avail[st->pga_index]; + else + *vals =3D (int *)st->scale_avail; + *length =3D st->scale_avail_size * 2; /* print int and nano part */ + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_LIST; + default: return -EINVAL; } @@ -963,6 +1073,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *i= ndio_dev, case IIO_CHAN_INFO_SAMP_FREQ: return ad4030_set_sampling_freq(indio_dev, val); =20 + case IIO_CHAN_INFO_SCALE: + return ad4030_set_pga(indio_dev, val, val2); + default: return -EINVAL; } @@ -984,6 +1097,17 @@ static int ad4030_write_raw(struct iio_dev *indio_dev, return ret; } =20 +static int ad4030_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } +} + static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { @@ -1030,6 +1154,7 @@ static const struct iio_info ad4030_iio_info =3D { .read_avail =3D ad4030_read_avail, .read_raw =3D ad4030_read_raw, .write_raw =3D ad4030_write_raw, + .write_raw_get_fmt =3D &ad4030_write_raw_get_fmt, .debugfs_reg_access =3D ad4030_reg_access, .read_label =3D ad4030_read_label, .get_current_scan_type =3D ad4030_get_current_scan_type, @@ -1271,6 +1396,26 @@ static int ad4030_spi_offload_setup(struct iio_dev *= indio_dev, IIO_BUFFER_DIRECTION_IN); } =20 +static int ad4030_setup_pga(struct device *dev, struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + /* Setup GPIOs for PGA control */ + st->pga_gpios =3D devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); + if (IS_ERR(st->pga_gpios)) + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), + "Failed to get PGA gpios.\n"); + + if (st->pga_gpios->ndescs !=3D ADAQ4616_PGA_PINS) + return dev_err_probe(dev, -EINVAL, + "Expected %d GPIOs for PGA control.\n", + ADAQ4616_PGA_PINS); + + st->scale_avail_size =3D ARRAY_SIZE(adaq4216_hw_gains_vpv); + st->pga_index =3D 0; + + return 0; +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1313,6 +1458,14 @@ static int ad4030_probe(struct spi_device *spi) if (ret) return ret; =20 + if (st->chip->has_pga) { + ret =3D ad4030_setup_pga(dev, indio_dev, st); + if (ret) + return ret; + + ad4030_fill_scale_avail(st); + } + ret =3D ad4030_config(st); if (ret) return ret; @@ -1566,12 +1719,52 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 +static const struct ad4030_chip_info adaq4216_chip_info =3D { + .name =3D "adaq4216", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, + .precision_bits =3D 16, + .has_pga =3D true, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, +}; + +static const struct ad4030_chip_info adaq4224_chip_info =3D { + .name =3D "adaq4224", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, + .precision_bits =3D 24, + .has_pga =3D true, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, +}; + static const struct spi_device_id ad4030_id_table[] =3D { { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, + { "adaq4216", (kernel_ulong_t)&adaq4216_chip_info }, + { "adaq4224", (kernel_ulong_t)&adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4030_id_table); @@ -1582,6 +1775,8 @@ static const struct of_device_id ad4030_of_match[] = =3D { { .compatible =3D "adi,ad4630-24", .data =3D &ad4630_24_chip_info }, { .compatible =3D "adi,ad4632-16", .data =3D &ad4632_16_chip_info }, { .compatible =3D "adi,ad4632-24", .data =3D &ad4632_24_chip_info }, + { .compatible =3D "adi,adaq4216", .data =3D &adaq4216_chip_info }, + { .compatible =3D "adi,adaq4224", .data =3D &adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4030_of_match); --=20 2.39.2 From nobody Sat Feb 7 20:39:53 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A98B436367; Thu, 5 Feb 2026 16:50:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310200; cv=none; b=oVprpx0uH+HNiG3jzgOM177OZWkZbMGEWguQP4cFKwke/lIvSKRp4LBCrnx0gTJlhtGvHuvV0NX5kRlvNxw3OmFqQn9PNOG6+Z9GC9Y7QfWghBJfkG02TPUB7imnvQdGiPwHIjtTbT2mWMaOLOfMfsoB8rc64WDuieTr4T+z2GE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770310200; c=relaxed/simple; bh=6JY1hWiIyRtTtgtlpMcVcHNMD468KAGhdf4TxR8y6Rc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qQY7c/9yVZolouCisdwVYqilE79ulDsSCUMPulAg/c5z06ImT3DB192Cp/GaaE7n+0r6AqQPrDU5Asg56fsqXIWou5/w1p0Jd1rn/LlRMM2KZ7BZNrUMnkGroVbPnYZ4oNV8OI0HLQ4I+CoO730ZC3Jg2XAyrWIhvzKrx3r5e2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=WEUmgsqH; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="WEUmgsqH" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 615AbPnu2446434; Thu, 5 Feb 2026 11:49:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=0y3y6 eFts47OTUNFONixEBorw01ZVvvr6fN9U5y+P98=; b=WEUmgsqHZkf2ouFSKwv9m wGhE+xwwbPYzilVUDyWpM1u1K3LiGwTAkMY3KO0Ogbj12ckwmSojDNjFQu8AbDEZ OIJAm0St2BUEwBDhNR1YLj2z0htMgxgDtqOFOMo85CisbrfI8u+JpW/PPl9DG5BB 85e+1AzZTOYwkY8qnZrkcfs26cVU8RWIjaCQ1oTl6crl3Octi05KUPlt0COlggQN XlXFl/kpUY4Han8RG7PQJBC2yfLPO+T403agVHs+E2HXGnd9K7uPuwdnj33v+1x9 8q4BuurN+MIQnE48zOPNFfExfPbxlN4eVkZANMLASFV+FFTfAlta9/SJZSj6DZ+z w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4c3vxvg287-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Feb 2026 11:49:54 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 615GnrqS045362 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Feb 2026 11:49:53 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:49:53 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 5 Feb 2026 11:49:53 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 5 Feb 2026 11:49:53 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 615GnbHK000489; Thu, 5 Feb 2026 11:49:40 -0500 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , Subject: [PATCH v7 8/8] iio: adc: ad4030: Support common-mode channels with SPI offloading Date: Thu, 5 Feb 2026 13:49:37 -0300 Message-ID: <027a198b8dea771601d7dcfa9827e7204e873741.1770309522.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: g8bSlcw99eF1lbslK9MH6Z6kwTOE6Bzp X-Proofpoint-ORIG-GUID: g8bSlcw99eF1lbslK9MH6Z6kwTOE6Bzp X-Authority-Analysis: v=2.4 cv=OrdCCi/t c=1 sm=1 tr=0 ts=6984ca32 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=nLo5uX867Eh3Y58ELpAA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDEyNyBTYWx0ZWRfXz+pS+yHjiE5D WQUxrzIQZLr/JtvLjAUKbU4HVNvOk2MZ1i/oOypig4Z9vRLHYTLhm/LM7bxr0bDlAGRxk5XCglL bwWmexzqUjKC9fGSF3380OuS6sThYt4+6QymbhmeaRMn/RYj93iBLkoDV3+pYX0wGnkM2mX985i 3qiNy2ndc658eV4eme2YJ0dI9i0qRgaJ/kBc6gh3CDkbv0qLGZdync6UoLTYcVMxGK9jr/7fZGh Son0Ytg9m0rTHzG8NANHgEgcMdfLL33D4werNAbpYzk7GULH9fqB0l/YVFL1I93CKedvzRzs0FU 3IUW3cvT+ZK7fN/qT807Q99f2gC7eJXxY/ErR5X6R9PT1zqgfxN0h3OaNjIuUjbIgAuoJ42j/JI odUOxCw1e5CTTOp7K6IcwAchE7gsweSHn+DPJlDYHwIqD6vejTpIlY2sK6xelVOpDSNPwHDM/k6 BFDalIUEYIfMoGNK7Bw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_04,2026-02-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050127 Content-Type: text/plain; charset="utf-8" AD4030 and similar devices can read common-mode voltage together with ADC sample data. When enabled, common-mode voltage data is provided in a separate IIO channel since it measures something other than the primary ADC input signal and requires separate scaling to convert to voltage units. The initial SPI offload support patch for AD4030 only provided differential channels. Now, extend the AD4030 driver to also provide common-mode IIO channels when setup with SPI offloading capability. Signed-off-by: Marcelo Schmitt --- Change log v6 -> v7 - No changes. drivers/iio/adc/ad4030.c | 49 ++++++++++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 4f521fe787d9..b2b3cd8ff38a 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -192,7 +192,7 @@ struct ad4030_state { unsigned int avg_log2; enum ad4030_out_mode mode; /* Offload sampling */ - struct spi_transfer offload_xfer; + struct spi_transfer offload_xfer[2]; struct spi_message offload_msg; struct spi_offload *offload; struct spi_offload_trigger *offload_trigger; @@ -237,7 +237,7 @@ struct ad4030_state { * - _idx - _ch * 2 + _ch gives the channel number for this specific commo= n-mode * channel */ -#define AD4030_CHAN_CMO(_idx, _ch) { \ +#define __AD4030_CHAN_CMO(_idx, _ch, _offload) { \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_SCALE), \ .type =3D IIO_VOLTAGE, \ @@ -247,12 +247,18 @@ struct ad4030_state { .scan_index =3D (_idx), \ .scan_type =3D { \ .sign =3D 'u', \ - .storagebits =3D 8, \ + .storagebits =3D (_offload ? 32 : 8), \ .realbits =3D 8, \ - .endianness =3D IIO_BE, \ + .endianness =3D (_offload ? IIO_CPU : IIO_BE), \ }, \ } =20 +#define AD4030_CHAN_CMO(_idx, _ch) \ + __AD4030_CHAN_CMO(_idx, _ch, 0) + +#define AD4030_OFFLOAD_CHAN_CMO(_idx, _ch) \ + __AD4030_CHAN_CMO(_idx, _ch, 1) + /* * For a chip with 2 hardware channel this will be used to create 2 differ= ential * channels: @@ -1180,6 +1186,7 @@ static const struct iio_buffer_setup_ops ad4030_buffe= r_setup_ops =3D { static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) { struct ad4030_state *st =3D iio_priv(indio_dev); + bool common_mode; u8 offload_bpw; =20 if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) @@ -1187,10 +1194,22 @@ static void ad4030_prepare_offload_msg(struct iio_d= ev *indio_dev) else offload_bpw =3D st->chip->precision_bits; =20 - st->offload_xfer.bits_per_word =3D offload_bpw; - st->offload_xfer.len =3D spi_bpw_to_bytes(offload_bpw); - st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; - spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); + st->offload_xfer[0].bits_per_word =3D offload_bpw; + st->offload_xfer[0].len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer[0].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + + common_mode =3D st->mode =3D=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM || + st->mode =3D=3D AD4030_OUT_DATA_MD_16_DIFF_8_COM; + + if (common_mode) { + offload_bpw =3D 8; + st->offload_xfer[1].bits_per_word =3D offload_bpw; + st->offload_xfer[1].len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer[1].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + } + + spi_message_init_with_transfers(&st->offload_msg, st->offload_xfer, + common_mode ? 2 : 1); } =20 static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) @@ -1255,6 +1274,7 @@ static int ad4030_offload_buffer_predisable(struct ii= o_dev *indio_dev) static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = =3D { .postenable =3D &ad4030_offload_buffer_postenable, .predisable =3D &ad4030_offload_buffer_predisable, + .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 static int ad4030_regulators_get(struct ad4030_state *st) @@ -1506,7 +1526,7 @@ static int ad4030_probe(struct spi_device *spi) * Offloaded SPI transfers can't support software timestamp so * no additional timestamp channel is added. */ - indio_dev->num_channels =3D st->chip->num_voltage_inputs; + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs; indio_dev->channels =3D st->chip->offload_channels; ret =3D ad4030_spi_offload_setup(indio_dev, st); if (ret) @@ -1627,6 +1647,7 @@ static const struct ad4030_chip_info ad4030_24_chip_i= nfo =3D { }, .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(1, 0), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, .precision_bits =3D 24, @@ -1648,6 +1669,8 @@ static const struct ad4030_chip_info ad4630_16_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, .precision_bits =3D 16, @@ -1669,6 +1692,8 @@ static const struct ad4030_chip_info ad4630_24_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, .precision_bits =3D 24, @@ -1690,6 +1715,8 @@ static const struct ad4030_chip_info ad4632_16_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, .precision_bits =3D 16, @@ -1711,6 +1738,8 @@ static const struct ad4030_chip_info ad4632_24_chip_i= nfo =3D { .offload_channels =3D { AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(2, 0), + AD4030_OFFLOAD_CHAN_CMO(3, 1), }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, .precision_bits =3D 24, @@ -1729,6 +1758,7 @@ static const struct ad4030_chip_info adaq4216_chip_in= fo =3D { }, .offload_channels =3D { ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(1, 0), }, .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, .precision_bits =3D 16, @@ -1748,6 +1778,7 @@ static const struct ad4030_chip_info adaq4224_chip_in= fo =3D { }, .offload_channels =3D { ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_CMO(1, 0), }, .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, .precision_bits =3D 24, --=20 2.39.2