From nobody Sun Feb 8 11:43:51 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82A5F279336; Sun, 1 Feb 2026 03:41:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769917320; cv=none; b=BPnV64TdvELrFOjeZMBP5s5ShyDU51A6p5j6d/5vL5933lKHWE/WMIRKKstwFWczTROpSM6SVnezqbB2uFhiCtYg/LV39ME1gaDBs3EJTnhbUpBjt7s4KLZ2DzLvaZiT0WvnnpXkiTAB1ntv/Dy92TPDAU3Bl59byglO3Bg8TVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769917320; c=relaxed/simple; bh=P9AVHS0bC1kwDKh5P3VUYJNMDUlwRspeNzrhrgPJWTM=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=uid4t7WBhOas7YZMrqXaC+SZpeOTXSdtG381WvlC2S2Kzx0WomxmBiwT4h1KdExJrbDLPA8EA+v7NgxqwaApBgD1STVK3uGFbQtSQQh9B3gC9GpgDoe1Ao9TEIRmdxplI/D4nRvQTwy9HA7RSZjK7LLSCzGJPX+Kv6gpeX5mNJ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vmOLU-000000002Wb-0tM7; Sun, 01 Feb 2026 03:41:56 +0000 Date: Sun, 1 Feb 2026 03:41:53 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v3 1/3] dt-bindings: net: dsa: lantiq,gswip: reference common PHY properties Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reference the common PHY properties so RX and TX SerDes lane polarity of the SGMII/1000Base-X/2500Base-X port can be configured. Signed-off-by: Daniel Golle Reviewed-by: Vladimir Oltean --- v3: commit message: clarify that the intention is to configure polarity at port level, as opposed to the internal polarity of the PCS component v2: use allOf to include PHY common properties, add example use --- Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/= Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml index f601e5f9fa6a..b4a31cde4322 100644 --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml @@ -105,6 +105,8 @@ patternProperties: patternProperties: "^(ethernet-)?port@[0-6]$": $ref: dsa-port.yaml# + allOf: + - $ref: /schemas/phy/phy-common-props.yaml# unevaluatedProperties: false =20 properties: @@ -288,6 +290,7 @@ examples: =20 - | #include + #include =20 mdio { #address-cells =3D <1>; @@ -320,6 +323,7 @@ examples: label =3D "wan"; phy-mode =3D "1000base-x"; managed =3D "in-band-status"; + tx-polarity =3D ; }; =20 port@5 { --=20 2.52.0 From nobody Sun Feb 8 11:43:51 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3A1123A9A8; Sun, 1 Feb 2026 03:42:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769917328; cv=none; b=jGZk9XgV2YDuQ7rHvlosKR6nvIy3TSRbJES0SvKT+DLTFPa1az3aJHIjLbpw9yu+2TXzdk0B3EdkNpIMLNwy2xMscfZR5PYkHZKU375cwZYzcNySXrfYxM1eAqA53luOiLq86CUvCC5u1rYYUdeI/gslXL2wRZztwPibpqxESJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769917328; c=relaxed/simple; bh=q1yqherTZ1VwTP5irNF4KDqWVxAHd1f324KoOIjrlh8=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=dZRsiiIqCgyxpg43jDvhv7s9IMSdmHOw617JhroyoS8D2sw2LdRg9i5d7gWAxShnB1PF1D55fiCdCpHAnVHnSN/MSzU/A5Q50DsxZudmQs3tBdtumw0O5iKdNH9p7sbaMtmX+M6WQA+QAbzGj9lm6g/9LxjQyNf7PSsRXL9tnxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vmOLb-000000002Wu-1HSD; Sun, 01 Feb 2026 03:42:03 +0000 Date: Sun, 1 Feb 2026 03:42:00 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v3 2/3] net: dsa: mxl-gsw1xx: configure SerDes port polarities Message-ID: <8bf79b3476e23673fceffbe2bc9d6abc13d132e5.1769916962.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Configure SerDes (port 4) RX and TX polarities using the newly introduced generic properties. The polarities are described at the port level which equals the polarities of the external pins of the chip. Note that the RX lane is inverted internally and the vendor driver simply always sets bit GSW1XX_SGMII_PHY_RX0_CFG2_INVERT unconditionally to end up with the correct (ie. as documented in datasheets) polarity at the external pins. In this sense, PHY_POLARITY_NORMAL denotes normal polarity for pins as documented for the MRQFN 105-pin package (GSW120, GSW125, GSW140, GSW141 and GSW145 all use the same package and have identical pin layouts except for TP port 2 and 3 being N/C on GSW12x): pin B18 (TX0_P) positive signal of the differential SGMII data output pair pin B19 (TX0_M) negative signal of the differential SGMII data output pair pin B20 (RX0_P) positive signal of the differential SGMII data input pair pin B21 (RX0_M) negative signal of the differential SGMII data input pair Signed-off-by: Daniel Golle Reviewed-by: Vladimir Oltean --- v3: be clear about describing polarity at external pins v2: use phy_get_manual_rx_polarity and phy_get_manual_tx_polarity --- drivers/net/dsa/lantiq/Kconfig | 1 + drivers/net/dsa/lantiq/mxl-gsw1xx.c | 39 +++++++++++++++++++++-------- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/net/dsa/lantiq/Kconfig b/drivers/net/dsa/lantiq/Kconfig index bad13817af25..98efeef2661b 100644 --- a/drivers/net/dsa/lantiq/Kconfig +++ b/drivers/net/dsa/lantiq/Kconfig @@ -15,6 +15,7 @@ config NET_DSA_MXL_GSW1XX tristate "MaxLinear GSW1xx Ethernet switch support" select NET_DSA_TAG_MXL_GSW1XX select NET_DSA_LANTIQ_COMMON + select PHY_COMMON_PROPS help This enables support for the Intel/MaxLinear GSW1xx family of 1GE switches. diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index 79cf72cc77be..61220b5fe5af 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include #include @@ -229,11 +231,17 @@ static int gsw1xx_pcs_phy_xaui_write(struct gsw1xx_pr= iv *priv, u16 addr, 1000, 100000); } =20 -static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) +static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv, phy_interface_t inte= rface) { + struct dsa_port *sgmii_port; + unsigned int pol; int ret; u16 val; =20 + sgmii_port =3D dsa_to_port(priv->gswip.ds, GSW1XX_SGMII_PORT); + if (!sgmii_port) + return -EINVAL; + /* Assert and deassert SGMII shell reset */ ret =3D regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, GSW1XX_RST_REQ_SGMII_SHELL); @@ -260,15 +268,20 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT, GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF); =20 + ret =3D phy_get_manual_rx_polarity(of_fwnode_handle(sgmii_port->dn), + phy_modes(interface), &pol); + if (ret) + return ret; + /* RX lane seems to be inverted internally, so bit * GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal - * (ie. non-inverted) operation. - * - * TODO: Take care of inverted RX pair once generic property is - * available + * (ie. non-inverted) operation matching the chips external pins as + * described in datasheets dated 2023-11-08, ie. pin B20 (RX0_P) being + * the positive signal and pin B21 (RX0_M) being the negative signal of + * the differential input pair. */ - - val |=3D GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; + if (pol =3D=3D PHY_POL_NORMAL) + val |=3D GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; =20 ret =3D regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val); if (ret < 0) @@ -277,9 +290,13 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) val =3D FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL, GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF); =20 - /* TODO: Take care of inverted TX pair once generic property is - * available - */ + ret =3D phy_get_manual_tx_polarity(of_fwnode_handle(sgmii_port->dn), + phy_modes(interface), &pol); + if (ret) + return ret; + + if (pol =3D=3D PHY_POL_INVERT) + val |=3D GSW1XX_SGMII_PHY_TX0_CFG3_INVERT; =20 ret =3D regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val); if (ret < 0) @@ -336,7 +353,7 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, u= nsigned int neg_mode, priv->tbi_interface =3D PHY_INTERFACE_MODE_NA; =20 if (!reconf) - ret =3D gsw1xx_pcs_reset(priv); + ret =3D gsw1xx_pcs_reset(priv, interface); =20 if (ret) return ret; --=20 2.52.0 From nobody Sun Feb 8 11:43:51 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE2C8214A97; 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dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vmOLt-000000002XJ-2EXk; Sun, 01 Feb 2026 03:42:21 +0000 Date: Sun, 1 Feb 2026 03:42:18 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v3 3/3] net: dsa: mxl-gsw1xx: validate chip ID Message-ID: <3194d3d3bb0b51f08755d392e1fdf7bb6dc49608.1769916962.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No check for actually present hardware is being performed in the probe function of the mxl-gsw1xx switch driver. So even if the switch isn't present at the configured MDIO bus address the driver wrongly tells the user that a "GSWIP version 0 mod 0" was found, outputting errors about PHY capabilities not matching. Read and validate the chip MANU_ID and PNUM_ID registers and output information while probing, but return an error and abort probing in case the hardware is not actually present. Signed-off-by: Daniel Golle Reviewed-by: Vladimir Oltean --- v3: no changes v2: no changes drivers/net/dsa/lantiq/mxl-gsw1xx.c | 27 ++++++++++++++++++++++++++- drivers/net/dsa/lantiq/mxl-gsw1xx.h | 9 +++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index 61220b5fe5af..a1104b2f92a9 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -688,7 +688,9 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) { struct device *dev =3D &mdiodev->dev; struct gsw1xx_priv *priv; - u32 version; + u32 version, val; + u8 shellver; + u16 pnum; int ret; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -736,6 +738,27 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) if (IS_ERR(priv->shell)) return PTR_ERR(priv->shell); =20 + ret =3D regmap_read(priv->shell, GSW1XX_SHELL_MANU_ID, &val); + if (ret < 0) + return ret; + + /* validate chip ID */ + if (FIELD_GET(GSW1XX_SHELL_MANU_ID_FIX1, val) !=3D 1) + return -ENODEV; + + if (FIELD_GET(GSW1XX_SHELL_MANU_ID_MANID, val) !=3D + GSW1XX_SHELL_MANU_ID_MANID_VAL) + return -ENODEV; + + pnum =3D FIELD_GET(GSW1XX_SHELL_MANU_ID_PNUML, val); + + ret =3D regmap_read(priv->shell, GSW1XX_SHELL_PNUM_ID, &val); + if (ret < 0) + return ret; + + pnum |=3D FIELD_GET(GSW1XX_SHELL_PNUM_ID_PNUMM, val) << 4; + shellver =3D FIELD_GET(GSW1XX_SHELL_PNUM_ID_VER, val); + ret =3D gsw1xx_serdes_pcs_init(priv); if (ret < 0) return ret; @@ -756,6 +779,8 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) if (ret) return ret; =20 + dev_info(dev, "standalone switch part number 0x%x v1.%u\n", pnum, shellve= r); + dev_set_drvdata(dev, &priv->gswip); =20 return 0; diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.h b/drivers/net/dsa/lantiq/m= xl-gsw1xx.h index d1fded56e967..caa8f1008587 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.h +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.h @@ -110,6 +110,15 @@ #define GSW1XX_SHELL_BASE 0xfa00 #define GSW1XX_SHELL_RST_REQ 0x01 #define GSW1XX_RST_REQ_SGMII_SHELL BIT(5) +#define GSW1XX_SHELL_MANU_ID 0x10 +#define GSW1XX_SHELL_MANU_ID_PNUML GENMASK(15, 12) +#define GSW1XX_SHELL_MANU_ID_MANID GENMASK(11, 1) +#define GSW1XX_SHELL_MANU_ID_MANID_VAL 0x389 +#define GSW1XX_SHELL_MANU_ID_FIX1 BIT(0) +#define GSW1XX_SHELL_PNUM_ID 0x11 +#define GSW1XX_SHELL_PNUM_ID_VER GENMASK(15, 12) +#define GSW1XX_SHELL_PNUM_ID_PNUMM GENMASK(11, 0) + /* RGMII PAD Slew Control Register */ #define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78 #define RGMII_SLEW_CFG_DRV_TXC BIT(2) --=20 2.52.0