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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org, imx@lists.linux.dev Subject: [PATCH v6 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the s32 chipsets the GMAC_0_CTRL_STS register is in GPR region. Originally, accessing this register was done in a sort of ad-hoc way, but we want to use the syscon interface to do it. This is a little bit ugly because we have to maintain backwards compatibility to the old device trees so we have to support both ways to access this register. Signed-off-by: Dan Carpenter Reviewed-by: Jan Petrous (OSS) --- v6: Add Jan's R-b tag v5: Return an error if regmap_write() fails v4: no change v3: no change v2: Fix forward porting bug. s/PHY_INTF_SEL_RGMII/S32_PHY_INTF_SEL_RGMII/ .../net/ethernet/stmicro/stmmac/dwmac-s32.c | 28 +++++++++++++++---- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index 5a485ee98fa7..af594a096676 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include =20 #include "stmmac_platform.h" @@ -32,6 +34,8 @@ struct s32_priv_data { void __iomem *ioaddr; void __iomem *ctrl_sts; + struct regmap *sts_regmap; + unsigned int sts_offset; struct device *dev; phy_interface_t *intf_mode; struct clk *tx_clk; @@ -40,11 +44,17 @@ struct s32_priv_data { =20 static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) { - writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + int ret =3D 0; + + if (gmac->ctrl_sts) + writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + else + ret =3D regmap_write(gmac->sts_regmap, gmac->sts_offset, + S32_PHY_INTF_SEL_RGMII); =20 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); =20 - return 0; + return ret; } =20 static int s32_gmac_init(struct device *dev, void *priv) @@ -125,10 +135,16 @@ static int s32_dwmac_probe(struct platform_device *pd= ev) "dt configuration failed\n"); =20 /* PHY interface mode control reg */ - gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(gmac->ctrl_sts)) - return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), - "S32CC config region is missing\n"); + gmac->sts_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "nxp,phy-sel", 1, &gmac->sts_offset); + if (gmac->sts_regmap =3D=3D ERR_PTR(-EPROBE_DEFER)) + return PTR_ERR(gmac->sts_regmap); + if (IS_ERR(gmac->sts_regmap)) { + gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(gmac->ctrl_sts)) + return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), + "S32CC config region is missing\n"); + } =20 /* tx clock */ gmac->tx_clk =3D devm_clk_get(&pdev->dev, "tx"); --=20 2.51.0 From nobody Sat Feb 7 08:43:26 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9509A29346F for ; Fri, 30 Jan 2026 13:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769779194; cv=none; b=Dz+yiJPwKlULxAzVw7pUkbskgQ2WfY32pfdofJ15o2gWnaTKP4BbwGVHD3DMiOJgNTQCJLSiHGpy9lK1S0s6kb6+cKl5sMW0SNnAXdWKoZnR/TUlAtx/TKFQ7Z7/wITVElEre+aWiyUhcBNAbSSJvwlTnd8zRdv4AzLbj4Zzsrg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769779194; c=relaxed/simple; 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Fri, 30 Jan 2026 05:19:50 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c37420sm281408035e9.9.2026.01.30.05.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 05:19:50 -0800 (PST) Date: Fri, 30 Jan 2026 16:19:47 +0300 From: Dan Carpenter To: Jan Petrous Cc: s32@nxp.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org, imx@lists.linux.dev Subject: [PATCH v6 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Message-ID: <3b75e950b2f8faecd1a9fa757e7eb7b42ace838f.1769764941.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The S32 chipsets have a GPR region which has a miscellaneous registers including the GMAC_0_CTRL_STS register. Originally, this code accessed that register in a sort of ad-hoc way, but it's cleaner to use a syscon interface to access these registers. We still need to maintain the old method of accessing the GMAC register but using a syscon will let us access other registers more cleanly. Signed-off-by: Dan Carpenter --- v6: Fix O vs 0 typo in GMAC_0 v5: Add Rob's R-b tag v4: Fix the formatting issue Rob pointed out v3: Better documentation about what GMAC_0_CTRL_STS register does. v2: Add the vendor prefix to the phandle Fix the documentation .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..1b2934f3c87c 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -32,6 +32,18 @@ properties: - description: Main GMAC registers - description: GMAC PHY mode control register =20 + nxp,phy-sel: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the GPR syscon node + - description: offset of PHY selection register + description: + This phandle points to the GMAC_0_CTRL_STS register which controls t= he + GMAC_0 configuration options. The register lets you select the PHY + interface and the PHY mode. It also controls if the FTM_0 or FTM_1 + FlexTimer Modules connect to GMAC_0. + interrupts: maxItems: 1 =20 @@ -74,6 +86,7 @@ examples: compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0 From nobody Sat Feb 7 08:43:26 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0EC6296BA5 for ; Fri, 30 Jan 2026 13:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769779200; cv=none; b=WLk+3SVrHNjy3Ev7dResDjPZwAsW0Sy+DHgPkVvl8oUFbuBT5n/9CWUfuE8nGlse/a3V27xxH4vGlTVqZ7X7OxU6dyu9fOfw92w6GWiFU7f9BxmJFdkicbaCDt7t/NLfg0+TCS5h+/PeQMcvalounKruRw2U9ANeodKaGe4cg94= ARC-Message-Signature: i=1; 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charset="utf-8" Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter --- v6: no change v5: no change v4: no change v3: no change v2: Remove #address-cells and #size-cells arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..b954952d962b 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,11 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32g2-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -731,6 +736,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index e314f3c7d61d..be03db737384 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,11 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32g3-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -808,6 +813,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0