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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:47.1393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac97e69b-0651-451f-bb22-08de595507de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5798 Content-Type: text/plain; charset="utf-8" So far, an IOTLB tag (ASID or VMID) has been stored in the arm_smmu_domain structure. Its lifecycle is aligned with the smmu_domain. However, an IOTLB tag (ASID/VMID) will not be used: 1) Before being installed to CD/STE during a device attachment 2) After being removed from CD/STE during a device detachment Both (1) and (2) exactly align with the lifecycle of smmu_domain->invs. The bigger problem is that storing the IOTLB tag in struct arm_smmu_domain makes it difficult to share across SMMU instances, a common use case for a nesting parent domain. Store the IOTLB tags (old domain's and new domain's) in the state. This'll be forwarded to CD and STE entries, to replace the references of cd->asid and s2_cfg->vmid from the smmu_domain. Add a new arm_smmu_domain_get_iotlb_tag() helper provisionally copying the existing IOTLB tags from smmu_domain to fill arm_smmu_master_build_invs(). Later it will retrieve an IOTLB tag from the smmu_domain->invs or allocate a new one for the lifecycle issue. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 78 ++++++++++++++------- 2 files changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4f104c1baa67..73cb59c7d4b1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1111,11 +1111,13 @@ static inline bool arm_smmu_master_canwbs(struct ar= m_smmu_master *master) * @new_invs: for new domain, this is the new invs array to update domain-= >invs; * for old domain, this is the master->build_invs to pass in as= the * to_unref argument to an arm_smmu_invs_unref() call + * @tag: IOTLB cache tag (INV_TYPE_S1_ASID or INV_TYPE_S2_VMID) */ struct arm_smmu_inv_state { struct arm_smmu_invs __rcu **invs_ptr; struct arm_smmu_invs *old_invs; struct arm_smmu_invs *new_invs; + struct arm_smmu_inv tag; }; =20 struct arm_smmu_attach_state { @@ -1132,6 +1134,10 @@ struct arm_smmu_attach_state { bool ats_enabled; }; =20 +int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, + struct arm_smmu_inv *tag); + int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, struct iommu_domain *new_domain); void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9912262a0e3b..325eabb51c81 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3117,6 +3117,33 @@ static void arm_smmu_disable_iopf(struct arm_smmu_ma= ster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, + struct arm_smmu_inv *tag) +{ + /* Decide the type of the iotlb cache tag */ + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_SVA: + case ARM_SMMU_DOMAIN_S1: + tag->type =3D INV_TYPE_S1_ASID; + break; + case ARM_SMMU_DOMAIN_S2: + tag->type =3D INV_TYPE_S2_VMID; + break; + default: + return -EINVAL; + } + + tag->smmu =3D smmu; + + if (tag->type =3D=3D INV_TYPE_S1_ASID) + tag->id =3D smmu_domain->cd.asid; + else + tag->id =3D smmu_domain->s2_cfg.vmid; + + return 0; +} + static struct arm_smmu_inv * arm_smmu_master_build_inv(struct arm_smmu_master *master, enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, @@ -3176,7 +3203,8 @@ arm_smmu_master_build_inv(struct arm_smmu_master *mas= ter, */ static struct arm_smmu_invs * arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enable= d, - ioasid_t ssid, struct arm_smmu_domain *smmu_domain) + ioasid_t ssid, struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag) { const bool nesting =3D smmu_domain->nest_parent; size_t pgsize =3D 0, i; @@ -3189,30 +3217,15 @@ arm_smmu_master_build_invs(struct arm_smmu_master *= master, bool ats_enabled, if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); =20 - switch (smmu_domain->stage) { - case ARM_SMMU_DOMAIN_SVA: - case ARM_SMMU_DOMAIN_S1: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, - smmu_domain->cd.asid, - IOMMU_NO_PASID, pgsize)) - return NULL; - break; - case ARM_SMMU_DOMAIN_S2: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, - smmu_domain->s2_cfg.vmid, - IOMMU_NO_PASID, pgsize)) - return NULL; - break; - default: - WARN_ON(true); + if (!arm_smmu_master_build_inv(master, tag->type, tag->id, + IOMMU_NO_PASID, pgsize)) return NULL; - } =20 /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ if (nesting) { - if (!arm_smmu_master_build_inv( - master, INV_TYPE_S2_VMID_S1_CLEAR, - smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + if (!arm_smmu_master_build_inv(master, + INV_TYPE_S2_VMID_S1_CLEAR, + tag->id, IOMMU_NO_PASID, 0)) return NULL; } =20 @@ -3280,7 +3293,9 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, struct arm_smmu_domain *old_smmu_domain =3D to_smmu_domain_devices(state->old_domain); struct arm_smmu_master *master =3D state->master; + struct arm_smmu_device *smmu =3D master->smmu; ioasid_t ssid =3D state->ssid; + int ret; =20 /* * At this point a NULL domain indicates the domain doesn't use the @@ -3294,8 +3309,16 @@ static int arm_smmu_attach_prepare_invs(struct arm_s= mmu_attach_state *state, invst->old_invs =3D rcu_dereference_protected( new_smmu_domain->invs, lockdep_is_held(&arm_smmu_asid_lock)); - build_invs =3D arm_smmu_master_build_invs( - master, state->ats_enabled, ssid, new_smmu_domain); + + ret =3D arm_smmu_domain_get_iotlb_tag(new_smmu_domain, smmu, + &invst->tag); + if (ret) + return ret; + + build_invs =3D arm_smmu_master_build_invs(master, + state->ats_enabled, + ssid, new_smmu_domain, + &invst->tag); if (!build_invs) return -EINVAL; =20 @@ -3316,9 +3339,16 @@ static int arm_smmu_attach_prepare_invs(struct arm_s= mmu_attach_state *state, invst->old_invs =3D rcu_dereference_protected( old_smmu_domain->invs, lockdep_is_held(&arm_smmu_asid_lock)); + + ret =3D arm_smmu_domain_get_iotlb_tag(old_smmu_domain, smmu, + &invst->tag); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:46.7648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4b64db0-ee0c-48a0-19f5-08de595507ab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6437 Content-Type: text/plain; charset="utf-8" Now, struct arm_smmu_attach_state has the IOTLB cache tags copied from the cd->asid or s2_cfg->vmid of an smmu_domain. Pass it down to arm_smmu_make_s1_cd() and arm_smmu_make_s2_domain_ste() to set in the CD and STE, removing the references of smmu_domain for its asid or vmid. Note the two set_dev_pasid callbacks finalize CDs in arm_smmu_set_pasid(). So, it is safe for arm_smmu_make_sva_cd() and arm_smmu_make_s1_cd() to use a dummy iotlb tag (asid=3D0) because arm_smmu_set_pasid() will fix it. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +-- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 26 ++++++++++------ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 22 ++++++++++--- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 12 +++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 31 +++++++++++-------- 5 files changed, 65 insertions(+), 31 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 73cb59c7d4b1..11879148dad0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1005,7 +1005,7 @@ void arm_smmu_make_abort_ste(struct arm_smmu_ste *tar= get); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, - bool ats_enabled); + struct arm_smmu_inv *tag, bool ats_enabled); =20 #if IS_ENABLED(CONFIG_KUNIT) void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); @@ -1070,7 +1070,8 @@ struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_sm= mu_master *master, u32 ssid); void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain); + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag); void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, struct arm_smmu_cd *cdptr, const struct arm_smmu_cd *target); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 93fdadd07431..34c7bd4cfd84 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -39,12 +39,15 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, return info; } =20 -static void arm_smmu_make_nested_cd_table_ste( - struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) +static void +arm_smmu_make_nested_cd_table_ste(struct arm_smmu_ste *target, + struct arm_smmu_master *master, + struct arm_smmu_nested_domain *nested_domain, + struct arm_smmu_inv *tag, bool ats_enabled) { - arm_smmu_make_s2_domain_ste( - target, master, nested_domain->vsmmu->s2_parent, ats_enabled); + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, tag, + ats_enabled); =20 target->data[0] =3D cpu_to_le64(STRTAB_STE_0_V | FIELD_PREP(STRTAB_STE_0_CFG, @@ -64,9 +67,11 @@ static void arm_smmu_make_nested_cd_table_ste( * - Bypass STE (install the S2, no CD table) * - CD table STE (install the S2 and the userspace CD table) */ -static void arm_smmu_make_nested_domain_ste( - struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) +static void +arm_smmu_make_nested_domain_ste(struct arm_smmu_ste *target, + struct arm_smmu_master *master, + struct arm_smmu_nested_domain *nested_domain, + struct arm_smmu_inv *tag, bool ats_enabled) { unsigned int cfg =3D FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(nested_domain->ste[0])); @@ -82,12 +87,12 @@ static void arm_smmu_make_nested_domain_ste( switch (cfg) { case STRTAB_STE_0_CFG_S1_TRANS: arm_smmu_make_nested_cd_table_ste(target, master, nested_domain, - ats_enabled); + tag, ats_enabled); break; case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste(target, master, nested_domain->vsmmu->s2_parent, - ats_enabled); + tag, ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: default: @@ -185,6 +190,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_doma= in *domain, } =20 arm_smmu_make_nested_domain_ste(&ste, master, nested_domain, + &state.new_domain_invst.tag, state.ats_enabled); arm_smmu_install_ste_for_dev(master, &ste); arm_smmu_attach_commit(&state); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index f1f8e01a7e91..dff494584008 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -24,12 +24,18 @@ arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_doma= in *smmu_domain) list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) { struct arm_smmu_master *master =3D master_domain->master; struct arm_smmu_cd *cdptr; + struct arm_smmu_inv tag; =20 cdptr =3D arm_smmu_get_cd_ptr(master, master_domain->ssid); if (WARN_ON(!cdptr)) continue; =20 - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + if (WARN_ON(arm_smmu_domain_get_iotlb_tag(smmu_domain, + master->smmu, &tag))) + continue; + if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) + continue; + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, &tag); arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, &target_cd); } @@ -158,12 +164,18 @@ static void arm_smmu_mm_release(struct mmu_notifier *= mn, struct mm_struct *mm) struct arm_smmu_master *master =3D master_domain->master; struct arm_smmu_cd target; struct arm_smmu_cd *cdptr; + struct arm_smmu_inv tag; =20 cdptr =3D arm_smmu_get_cd_ptr(master, master_domain->ssid); if (WARN_ON(!cdptr)) continue; - arm_smmu_make_sva_cd(&target, master, NULL, - smmu_domain->cd.asid); + + if (WARN_ON(arm_smmu_domain_get_iotlb_tag(smmu_domain, + master->smmu, &tag))) + continue; + if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) + continue; + arm_smmu_make_sva_cd(&target, master, NULL, tag.id); arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, &target); } @@ -262,10 +274,12 @@ static int arm_smmu_sva_set_dev_pasid(struct iommu_do= main *domain, return -EINVAL; =20 /* + * Use a dummy asid and fix it in arm_smmu_set_pasid(). + * * This does not need the arm_smmu_asid_lock because SVA domains never * get reassigned */ - arm_smmu_make_sva_cd(&target, master, domain->mm, smmu_domain->cd.asid); + arm_smmu_make_sva_cd(&target, master, domain->mm, 0); ret =3D arm_smmu_set_pasid(master, smmu_domain, id, &target, old); =20 mmput(domain->mm); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 238bfd328b5b..81551fad727b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -306,6 +306,9 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, struct arm_smmu_domain smmu_domain =3D { .pgtbl_ops =3D &io_pgtable.ops, }; + struct arm_smmu_inv tag =3D { + .type =3D INV_TYPE_S2_VMID, + }; =20 io_pgtable.cfg.arm_lpae_s2_cfg.vttbr =3D 0xdaedbeefdeadbeefULL; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.ps =3D 1; @@ -316,7 +319,8 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.sl =3D 3; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.tsz =3D 4; =20 - arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, ats_enabled); + arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, &tag, + ats_enabled); } =20 static void arm_smmu_v3_write_ste_test_s2_to_abort(struct kunit *test) @@ -461,6 +465,10 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_c= d *cd, unsigned int asid) .asid =3D asid, }, }; + struct arm_smmu_inv tag =3D { + .type =3D INV_TYPE_S1_ASID, + .id =3D asid, + }; =20 io_pgtable.cfg.arm_lpae_s1_cfg.ttbr =3D 0xdaedbeefdeadbeefULL; io_pgtable.cfg.arm_lpae_s1_cfg.tcr.ips =3D 1; @@ -471,7 +479,7 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd= *cd, unsigned int asid) io_pgtable.cfg.arm_lpae_s1_cfg.tcr.tsz =3D 4; io_pgtable.cfg.arm_lpae_s1_cfg.mair =3D 0xabcdef012345678ULL; =20 - arm_smmu_make_s1_cd(cd, &master, &smmu_domain); + arm_smmu_make_s1_cd(cd, &master, &smmu_domain, &tag); } =20 static void arm_smmu_v3_write_cd_test_s1_clear(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 325eabb51c81..cf0543f276f3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1613,14 +1613,16 @@ void arm_smmu_write_cd_entry(struct arm_smmu_master= *master, int ssid, =20 void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain) + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag) { - struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_cfg.tcr; =20 + WARN_ON(tag->type !=3D INV_TYPE_S1_ASID); + memset(target, 0, sizeof(*target)); =20 target->data[0] =3D cpu_to_le64( @@ -1640,7 +1642,7 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET | - FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) + FIELD_PREP(CTXDESC_CD_0_ASID, tag->id) ); =20 /* To enable dirty flag update, set both Access flag and dirty state upda= te */ @@ -1897,9 +1899,8 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, - bool ats_enabled) + struct arm_smmu_inv *tag, bool ats_enabled) { - struct arm_smmu_s2_cfg *s2_cfg =3D &smmu_domain->s2_cfg; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =3D @@ -1907,6 +1908,8 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, u64 vtcr_val; struct arm_smmu_device *smmu =3D master->smmu; =20 + WARN_ON(tag->type !=3D INV_TYPE_S2_VMID); + memset(target, 0, sizeof(*target)); target->data[0] =3D cpu_to_le64( STRTAB_STE_0_V | @@ -1930,7 +1933,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] =3D cpu_to_le64( - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | + FIELD_PREP(STRTAB_STE_2_S2VMID, tag->id) | FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN @@ -3671,7 +3674,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, case ARM_SMMU_DOMAIN_S1: { struct arm_smmu_cd target_cd; =20 - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, + &state.new_domain_invst.tag); arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, cdptr, &target_cd); arm_smmu_make_cdtable_ste(&target, master, state.ats_enabled, @@ -3681,6 +3685,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, } case ARM_SMMU_DOMAIN_S2: arm_smmu_make_s2_domain_ste(&target, master, smmu_domain, + &state.new_domain_invst.tag, state.ats_enabled); arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); @@ -3702,6 +3707,9 @@ static int arm_smmu_s1_set_dev_pasid(struct iommu_dom= ain *domain, struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_device *smmu =3D master->smmu; + struct arm_smmu_inv tag =3D { + .type =3D INV_TYPE_S1_ASID, + }; struct arm_smmu_cd target_cd; =20 if (smmu_domain->smmu !=3D smmu) @@ -3710,11 +3718,8 @@ static int arm_smmu_s1_set_dev_pasid(struct iommu_do= main *domain, if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_S1) return -EINVAL; =20 - /* - * We can read cd.asid outside the lock because arm_smmu_set_pasid() - * will fix it - */ - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + /* Use a dummy asid and fix it in arm_smmu_set_pasid() */ + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, &tag); return arm_smmu_set_pasid(master, to_smmu_domain(domain), id, &target_cd, old); } @@ -3782,7 +3787,7 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, */ cd->data[0] &=3D ~cpu_to_le64(CTXDESC_CD_0_ASID); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:50.8654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9789593-e257-4ae7-f13c-08de59550a1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9514 Content-Type: text/plain; charset="utf-8" Once arm_smmu_attach_prepare() installs an iotlb tag to smmu_domain->invs, arm_smmu_domain_get_iotlb_tag() callers should get the tag from the array. Only the arm_smmu_domain_get_iotlb_tag() caller for new_smmu_domain in the arm_smmu_attach_prepare_invs() will be allowed to allocate a new tag. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 8 ++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 +++++++++++++++++-- 3 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 11879148dad0..812314aaaa6a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1137,7 +1137,7 @@ struct arm_smmu_attach_state { =20 int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, - struct arm_smmu_inv *tag); + struct arm_smmu_inv *tag, bool alloc); =20 int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, struct iommu_domain *new_domain); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index dff494584008..5c8960d31a9b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -30,8 +30,8 @@ arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_domain= *smmu_domain) if (WARN_ON(!cdptr)) continue; =20 - if (WARN_ON(arm_smmu_domain_get_iotlb_tag(smmu_domain, - master->smmu, &tag))) + if (WARN_ON(arm_smmu_domain_get_iotlb_tag( + smmu_domain, master->smmu, &tag, false))) continue; if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) continue; @@ -170,8 +170,8 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) if (WARN_ON(!cdptr)) continue; =20 - if (WARN_ON(arm_smmu_domain_get_iotlb_tag(smmu_domain, - master->smmu, &tag))) + if (WARN_ON(arm_smmu_domain_get_iotlb_tag( + smmu_domain, master->smmu, &tag, false))) continue; if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) continue; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index cf0543f276f3..1927eb794db9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3120,10 +3120,31 @@ static void arm_smmu_disable_iopf(struct arm_smmu_m= aster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +static int __arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_do= main, + struct arm_smmu_inv *tag) +{ + struct arm_smmu_invs *invs =3D rcu_dereference_protected( + smmu_domain->invs, lockdep_is_held(&arm_smmu_asid_lock)); + size_t i; + + for (i =3D 0; i !=3D invs->num_invs; i++) { + if (invs->inv[i].type =3D=3D tag->type && + invs->inv[i].smmu =3D=3D tag->smmu && + refcount_read(&invs->inv[i].users)) { + *tag =3D invs->inv[i]; + return 0; + } + } + + return -ENOENT; +} + int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, - struct arm_smmu_inv *tag) + struct arm_smmu_inv *tag, bool alloc) { + int ret; + /* Decide the type of the iotlb cache tag */ switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_SVA: @@ -3139,6 +3160,11 @@ int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_do= main *smmu_domain, =20 tag->smmu =3D smmu; =20 + /* Re-use an existing IOTLB cache tag in invs (users counter !=3D 0) */ + ret =3D __arm_smmu_domain_get_iotlb_tag(smmu_domain, tag); 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Wed, 21 Jan 2026 17:24:41 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 17:24:40 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 21 Jan 2026 17:24:40 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v2 04/10] iommu/arm-smmu-v3: Allocate IOTLB cache tag if no id to reuse Date: Wed, 21 Jan 2026 17:24:22 -0800 Message-ID: <85f3361fa07ca6884500ccc917da6f6b84e13a6c.1769044718.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|MN2PR12MB4456:EE_ X-MS-Office365-Filtering-Correlation-Id: 86293824-1614-4077-9851-08de59550a9d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:51.6931 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86293824-1614-4077-9851-08de59550a9d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4456 Content-Type: text/plain; charset="utf-8" An IOTLB tag now is forwarded from arm_smmu_domain_get_iotlb_tag() to its final destination (a CD or STE entry). Thus, arm_smmu_domain_get_iotlb_tag() can safely delink its references to the cd->asid and s2_cfg->vmid in the smmu_domain. Instead, allocate a new IOTLB cache tag from the xarray/ida. The old asid and vmid in the smmu_domain will be deprecated, once VMID is decoupled from the vSMMU use case. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 38 ++++++++++++++++++--- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1927eb794db9..d10593823353 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1210,6 +1210,8 @@ void arm_smmu_invs_unref(struct arm_smmu_invs *invs, /* KUNIT test doesn't pass in a free_fn */ if (free_fn) free_fn(&invs->inv[i]); + /* Notify the caller to free the iotlb tag */ + refcount_set(&to_unref->inv[j].users, 0); invs->num_trashes++; } else { /* item in to_unref is not in invs or already a trash */ @@ -3165,12 +3167,31 @@ int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_d= omain *smmu_domain, if (!ret || !alloc) return ret; =20 - if (tag->type =3D=3D INV_TYPE_S1_ASID) - tag->id =3D smmu_domain->cd.asid; - else - tag->id =3D smmu_domain->s2_cfg.vmid; + /* Allocate a new IOTLB cache tag (users counter =3D=3D 0) */ + lockdep_assert_held(&arm_smmu_asid_lock); =20 - return 0; + if (tag->type =3D=3D INV_TYPE_S1_ASID) { + ret =3D xa_alloc(&arm_smmu_asid_xa, &tag->id, smmu_domain, + XA_LIMIT(1, (1 << smmu->asid_bits) - 1), + GFP_KERNEL); + } else { + ret =3D ida_alloc_range(&smmu->vmid_map, 1, + (1 << smmu->vmid_bits) - 1, GFP_KERNEL); + if (ret > 0) { + tag->id =3D ret; /* int is good for 16-bit VMID */ + ret =3D 0; + } + } + + return ret; +} + +static void arm_smmu_iotlb_tag_free(struct arm_smmu_inv *tag) +{ + if (tag->type =3D=3D INV_TYPE_S1_ASID) + xa_erase(&arm_smmu_asid_xa, tag->id); + else if (tag->type =3D=3D INV_TYPE_S2_VMID) + ida_free(&tag->smmu->vmid_map, tag->id); } =20 static struct arm_smmu_inv * @@ -3220,6 +3241,9 @@ arm_smmu_master_build_inv(struct arm_smmu_master *mas= ter, break; } =20 + /* Set a default users counter */ + refcount_set(&cur->users, 1); + return cur; } =20 @@ -3453,6 +3477,8 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_atta= ch_state *state) =20 arm_smmu_invs_unref(old_invs, invst->new_invs, arm_smmu_inv_flush_iotlb_tag); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:54.3026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef8e67fc-85ab-4eda-a1db-08de59550c2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8814 Content-Type: text/plain; charset="utf-8" If the IOTLB cache tag is no longer used by any device, flush the entries tagged with the ASID/VMID, before the tag gets free-ed. Drop the free_fn callback accordingly since it's the same thing. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 6 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 46 +++++-------------- 3 files changed, 16 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 812314aaaa6a..696ebb89ffa3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1024,8 +1024,7 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, struct arm_smmu_invs *arm_smmu_invs_merge(struct arm_smmu_invs *invs, struct arm_smmu_invs *to_merge); void arm_smmu_invs_unref(struct arm_smmu_invs *invs, - struct arm_smmu_invs *to_unref, - void (*free_fn)(struct arm_smmu_inv *inv)); + struct arm_smmu_invs *to_unref); struct arm_smmu_invs *arm_smmu_invs_purge(struct arm_smmu_invs *invs); #endif =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 81551fad727b..d66931b56b46 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -635,7 +635,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) results2[0], results2[1]); =20 /* Test3: unref invs2 (same array) */ - arm_smmu_invs_unref(test_a, &invs2, NULL); + arm_smmu_invs_unref(test_a, &invs2); arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results3[0]), results3[0], results3[1]); KUNIT_EXPECT_EQ(test, test_a->num_trashes, 0); @@ -647,7 +647,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) results4[0], results4[1]); =20 /* Test5: unref invs1 (same array) */ - arm_smmu_invs_unref(test_b, &invs1, NULL); + arm_smmu_invs_unref(test_b, &invs1); arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results5[0]), results5[0], results5[1]); KUNIT_EXPECT_EQ(test, test_b->num_trashes, 2); @@ -659,7 +659,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) results6[0], results6[1]); =20 /* Test7: unref invs3 (same array) */ - arm_smmu_invs_unref(test_a, &invs3, NULL); + arm_smmu_invs_unref(test_a, &invs3); KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); KUNIT_EXPECT_EQ(test, test_a->num_trashes, 0); =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d10593823353..5a7032081553 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1168,8 +1168,6 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge); * the user counts without deletions * @invs: the base invalidation array * @to_unref: an array of invlidations to decrease their user counts - * @free_fn: A callback function to invoke, when an entry's user count red= uces - * to 0 * * Return: the number of trash entries in the array, for arm_smmu_invs_pur= ge() * @@ -1188,8 +1186,7 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge); */ VISIBLE_IF_KUNIT void arm_smmu_invs_unref(struct arm_smmu_invs *invs, - struct arm_smmu_invs *to_unref, - void (*free_fn)(struct arm_smmu_inv *inv)) + struct arm_smmu_invs *to_unref) { unsigned long flags; size_t num_invs =3D 0; @@ -1207,9 +1204,6 @@ void arm_smmu_invs_unref(struct arm_smmu_invs *invs, continue; } =20 - /* KUNIT test doesn't pass in a free_fn */ - if (free_fn) - free_fn(&invs->inv[i]); /* Notify the caller to free the iotlb tag */ refcount_set(&to_unref->inv[j].users, 0); invs->num_trashes++; @@ -3188,6 +3182,16 @@ int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_do= main *smmu_domain, =20 static void arm_smmu_iotlb_tag_free(struct arm_smmu_inv *tag) { + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D tag->nsize_opcode, + }; + + if (tag->type =3D=3D INV_TYPE_S1_ASID) + cmd.tlbi.asid =3D tag->id; + else + cmd.tlbi.vmid =3D tag->id; + arm_smmu_cmdq_issue_cmd_with_sync(tag->smmu, &cmd); + if (tag->type =3D=3D INV_TYPE_S1_ASID) xa_erase(&arm_smmu_asid_xa, tag->id); else if (tag->type =3D=3D INV_TYPE_S2_VMID) @@ -3437,31 +3441,6 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_att= ach_state *state) kfree_rcu(invst->old_invs, rcu); } =20 -/* - * When an array entry's users count reaches zero, it means the ASID/VMID = is no - * longer being invalidated by map/unmap and must be cleaned. The rule is = that - * all ASIDs/VMIDs not in an invalidation array are left cleared in the IO= TLB. - */ -static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv) -{ - struct arm_smmu_cmdq_ent cmd =3D {}; - - switch (inv->type) { - case INV_TYPE_S1_ASID: - cmd.tlbi.asid =3D inv->id; - break; - case INV_TYPE_S2_VMID: - /* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */ - cmd.tlbi.vmid =3D inv->id; - break; - default: - return; - } - - cmd.opcode =3D inv->nsize_opcode; - arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); -} - /* Should be installed after arm_smmu_install_ste_for_dev() */ static void arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) @@ -3475,8 +3454,7 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_atta= ch_state *state) if (!invst->invs_ptr) return; =20 - arm_smmu_invs_unref(old_invs, invst->new_invs, - arm_smmu_inv_flush_iotlb_tag); + arm_smmu_invs_unref(old_invs, invst->new_invs); if (!refcount_read(&invst->new_invs->inv[0].users)) arm_smmu_iotlb_tag_free(&invst->tag); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:55.5447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53b9cce4-a82c-4f1a-a344-08de59550ce7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9789 Content-Type: text/plain; charset="utf-8" VMID owned by a vSMMU should be allocated in the viommu_init callback, as HW like tegra241-cmdqv needs to setup VINTF with the VMID. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 21 +++++++++++++++++-- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 1 + 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 696ebb89ffa3..8aecdbceb974 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1190,6 +1190,7 @@ size_t arm_smmu_get_viommu_size(struct device *dev, int arm_vsmmu_init(struct iommufd_viommu *viommu, struct iommu_domain *parent_domain, const struct iommu_user_data *user_data); +void arm_vsmmu_destroy(struct iommufd_viommu *viommu); int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, struct arm_smmu_nested_domain *nested_domain); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 34c7bd4cfd84..9998871f69a0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -404,7 +404,17 @@ int arm_vsmmu_cache_invalidate(struct iommufd_viommu *= viommu, return ret; } =20 +void arm_vsmmu_destroy(struct iommufd_viommu *viommu) +{ + struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); + + mutex_lock(&arm_smmu_asid_lock); + ida_free(&vsmmu->smmu->vmid_map, vsmmu->vmid); + mutex_unlock(&arm_smmu_asid_lock); +} + static const struct iommufd_viommu_ops arm_vsmmu_ops =3D { + .destroy =3D arm_vsmmu_destroy, .alloc_domain_nested =3D arm_vsmmu_alloc_domain_nested, .cache_invalidate =3D arm_vsmmu_cache_invalidate, }; @@ -454,14 +464,21 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, struct arm_smmu_device *smmu =3D container_of(viommu->iommu_dev, struct arm_smmu_device, iommu); struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent_domain); + int id; =20 if (s2_parent->smmu !=3D smmu) return -EINVAL; =20 + mutex_lock(&arm_smmu_asid_lock); + id =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, + GFP_KERNEL); + mutex_unlock(&arm_smmu_asid_lock); + if (id < 0) + return id; + + vsmmu->vmid =3D id; vsmmu->smmu =3D smmu; vsmmu->s2_parent =3D s2_parent; - /* FIXME Move VMID allocation from the S2 domain allocation to here */ - vsmmu->vmid =3D s2_parent->s2_cfg.vmid; =20 if (viommu->type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) { viommu->ops =3D &arm_vsmmu_ops; diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu= /arm/arm-smmu-v3/tegra241-cmdqv.c index 378104cd395e..67e72115d43a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -1209,6 +1209,7 @@ static void tegra241_cmdqv_destroy_vintf_user(struct = iommufd_viommu *viommu) iommufd_viommu_destroy_mmap(&vintf->vsmmu.core, vintf->mmap_offset); tegra241_cmdqv_remove_vintf(vintf->cmdqv, vintf->idx); + arm_vsmmu_destroy(viommu); } =20 static void tegra241_vintf_destroy_vsid(struct iommufd_vdevice *vdev) --=20 2.43.0 From nobody Sat Feb 7 22:07:18 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011055.outbound.protection.outlook.com [52.101.62.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CD4D350A16 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:52.7215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 486c61cc-5836-46cb-0ca9-08de59550b38 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6248 Content-Type: text/plain; charset="utf-8" When a device attaches to a nested domain, VMID is held by its associated vSMMU instance. So arm_smmu_domain_get_iotlb_tag() should return the VMID from the vSMMU instance rather than allocating a new one. Pass in a vsmmu pointer to arm_smmu_domain_get_iotlb_tag(), to prepare for this. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 +++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 4 ++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++-- 4 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 8aecdbceb974..386ac75879c0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1124,6 +1124,7 @@ struct arm_smmu_attach_state { /* Inputs */ struct iommu_domain *old_domain; struct arm_smmu_master *master; + struct arm_vsmmu *vsmmu; bool cd_needs_ats; bool disable_ats; ioasid_t ssid; @@ -1136,6 +1137,7 @@ struct arm_smmu_attach_state { =20 int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, + struct arm_vsmmu *vsmmu, struct arm_smmu_inv *tag, bool alloc); =20 int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, @@ -1182,6 +1184,13 @@ struct arm_vsmmu { u16 vmid; }; =20 +static inline struct arm_vsmmu *to_vsmmu(struct iommu_domain *domain) +{ + if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) + return to_smmu_nested_domain(domain)->vsmmu; + return NULL; +} + #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, enum iommu_hw_info_type *type); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 9998871f69a0..33b336d494c3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -162,6 +162,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_doma= in *domain, struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_attach_state state =3D { .master =3D master, + .vsmmu =3D nested_domain->vsmmu, .old_domain =3D old_domain, .ssid =3D IOMMU_NO_PASID, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 5c8960d31a9b..461ccf4bdb03 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -31,7 +31,7 @@ arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_domain= *smmu_domain) continue; =20 if (WARN_ON(arm_smmu_domain_get_iotlb_tag( - smmu_domain, master->smmu, &tag, false))) + smmu_domain, master->smmu, NULL, &tag, false))) continue; if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) continue; @@ -171,7 +171,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) continue; =20 if (WARN_ON(arm_smmu_domain_get_iotlb_tag( - smmu_domain, master->smmu, &tag, false))) + smmu_domain, master->smmu, NULL, &tag, false))) continue; if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) continue; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5a7032081553..8323f74c8923 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3137,6 +3137,7 @@ static int __arm_smmu_domain_get_iotlb_tag(struct arm= _smmu_domain *smmu_domain, =20 int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, + struct arm_vsmmu *vsmmu, struct arm_smmu_inv *tag, bool alloc) { int ret; @@ -3360,6 +3361,7 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, */ if (new_smmu_domain) { struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + struct arm_vsmmu *vsmmu =3D state->vsmmu; struct arm_smmu_invs *build_invs; =20 invst->invs_ptr =3D &new_smmu_domain->invs; @@ -3368,7 +3370,7 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, lockdep_is_held(&arm_smmu_asid_lock)); =20 ret =3D arm_smmu_domain_get_iotlb_tag(new_smmu_domain, smmu, - &invst->tag, true); + vsmmu, &invst->tag, true); if (ret) return ret; =20 @@ -3387,6 +3389,7 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, =20 if (old_smmu_domain) { struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + struct arm_vsmmu *vsmmu =3D to_vsmmu(state->old_domain); =20 invst->invs_ptr =3D &old_smmu_domain->invs; /* A re-attach case might have a different ats_enabled state */ @@ -3398,7 +3401,7 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, lockdep_is_held(&arm_smmu_asid_lock)); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:53.3902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a2bf0d1-3f62-4077-304f-08de59550b9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF711010B62 Content-Type: text/plain; charset="utf-8" A VMID held by a vSMMU is required to setup hardware (e.g. tegra241-cmdqv) during its initialization. So, it should be allocated in the ->viommu_init callback. This makes the VMID lifecycle unique than a VMID allocated for a naked S2 attachment. Introduce an INV_TYPE_S2_VMID_VSMMU to accommodate this case. Note that a second device attaching to a nested domain associated with the same vSMMU instance will have an INV_TYPE_S2_VMID_VSMMU and reuse the VMID held by the vSMMU. Devices attaching directly to the nesting parent domain will have an INV_TYPE_S2_VMID and shouldn't resue the VMID from the vSMMU. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 +++++++++++++++--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 386ac75879c0..8365660282d5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -656,6 +656,7 @@ struct arm_smmu_cmdq_batch { enum arm_smmu_inv_type { INV_TYPE_S1_ASID, INV_TYPE_S2_VMID, + INV_TYPE_S2_VMID_VSMMU, INV_TYPE_S2_VMID_S1_CLEAR, INV_TYPE_ATS, INV_TYPE_ATS_FULL, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8323f74c8923..6d3da3f82ec8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1904,7 +1904,8 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, u64 vtcr_val; struct arm_smmu_device *smmu =3D master->smmu; =20 - WARN_ON(tag->type !=3D INV_TYPE_S2_VMID); + WARN_ON(tag->type !=3D INV_TYPE_S2_VMID && + tag->type !=3D INV_TYPE_S2_VMID_VSMMU); =20 memset(target, 0, sizeof(*target)); target->data[0] =3D cpu_to_le64( @@ -2592,6 +2593,7 @@ static void __arm_smmu_domain_inv_range(struct arm_sm= mu_invs *invs, granule); break; case INV_TYPE_S2_VMID: + case INV_TYPE_S2_VMID_VSMMU: cmd.tlbi.vmid =3D cur->id; cmd.tlbi.leaf =3D leaf; arm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size, @@ -3149,7 +3151,10 @@ int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_do= main *smmu_domain, tag->type =3D INV_TYPE_S1_ASID; break; case ARM_SMMU_DOMAIN_S2: - tag->type =3D INV_TYPE_S2_VMID; + if (vsmmu) + tag->type =3D INV_TYPE_S2_VMID_VSMMU; + else + tag->type =3D INV_TYPE_S2_VMID; break; default: return -EINVAL; @@ -3163,6 +3168,12 @@ int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_do= main *smmu_domain, return ret; =20 /* Allocate a new IOTLB cache tag (users counter =3D=3D 0) */ + if (tag->type =3D=3D INV_TYPE_S2_VMID_VSMMU) { + /* Use the pre-allocated VMID from vSMMU */ + tag->id =3D vsmmu->vmid; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:54.7140 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba50f75d-921b-4ec6-9f56-08de59550c67 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6618 Content-Type: text/plain; charset="utf-8" Now ASID/VMID are stored in the arm_smmu_master. These are dead code now. Remove all. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 20 +------ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 3 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 58 ------------------- 4 files changed, 1 insertion(+), 88 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 8365660282d5..c7b054eb062a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -784,10 +784,6 @@ static inline bool arm_smmu_ssids_in_use(struct arm_sm= mu_ctx_desc_cfg *cd_table) return cd_table->used_ssids; } =20 -struct arm_smmu_s2_cfg { - u16 vmid; -}; - struct arm_smmu_strtab_cfg { union { struct { @@ -964,10 +960,6 @@ struct arm_smmu_domain { atomic_t nr_ats_masters; =20 enum arm_smmu_domain_stage stage; - union { - struct arm_smmu_ctx_desc cd; - struct arm_smmu_s2_cfg s2_cfg; - }; =20 struct iommu_domain domain; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 461ccf4bdb03..7f7f147327bd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -295,14 +295,6 @@ static void arm_smmu_sva_domain_free(struct iommu_doma= in *domain) */ arm_smmu_domain_inv(smmu_domain); =20 - /* - * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can - * still be called/running at this point. We allow the ASID to be - * reused, and if there is a race then it just suffers harmless - * unnecessary invalidation. - */ - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); - /* * Actual free is defered to the SRCU callback * arm_smmu_mmu_notifier_free() @@ -321,7 +313,6 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_domain *smmu_domain; - u32 asid; int ret; =20 if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) @@ -340,22 +331,13 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct= device *dev, smmu_domain->domain.pgsize_bitmap =3D PAGE_SIZE; smmu_domain->stage =3D ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu =3D smmu; - - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - if (ret) - goto err_free; - - smmu_domain->cd.asid =3D asid; smmu_domain->mmu_notifier.ops =3D &arm_smmu_mmu_notifier_ops; ret =3D mmu_notifier_register(&smmu_domain->mmu_notifier, mm); if (ret) - goto err_asid; + goto err_free; =20 return &smmu_domain->domain; =20 -err_asid: - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); err_free: arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d66931b56b46..4ad26046fab6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -461,9 +461,6 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd= *cd, unsigned int asid) struct io_pgtable io_pgtable =3D {}; struct arm_smmu_domain smmu_domain =3D { .pgtbl_ops =3D &io_pgtable.ops, - .cd =3D { - .asid =3D asid, - }, }; struct arm_smmu_inv tag =3D { .type =3D INV_TYPE_S1_ASID, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 6d3da3f82ec8..19437ee6f4e1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2784,66 +2784,17 @@ struct arm_smmu_domain *arm_smmu_domain_alloc(void) static void arm_smmu_domain_free_paging(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct arm_smmu_device *smmu =3D smmu_domain->smmu; =20 free_io_pgtable_ops(smmu_domain->pgtbl_ops); - - /* Free the ASID or VMID */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - /* Prevent SVA from touching the CD while we're freeing it */ - mutex_lock(&arm_smmu_asid_lock); - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); - mutex_unlock(&arm_smmu_asid_lock); - } else { - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - if (cfg->vmid) - ida_free(&smmu->vmid_map, cfg->vmid); - } - arm_smmu_domain_free(smmu_domain); } =20 -static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain) -{ - int ret; - u32 asid =3D 0; - struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; - - /* Prevent SVA from modifying the ASID until it is written to the CD */ - mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - cd->asid =3D (u16)asid; - mutex_unlock(&arm_smmu_asid_lock); - return ret; -} - -static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain) -{ - int vmid; - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - - /* Reserve VMID 0 for stage-2 bypass STEs */ - vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, - GFP_KERNEL); - if (vmid < 0) - return vmid; - - cfg->vmid =3D (u16)vmid; - return 0; -} - static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, u32 flags) { - int ret; enum io_pgtable_fmt fmt; struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; - int (*finalise_stage_fn)(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain); bool enable_dirty =3D flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; =20 pgtbl_cfg =3D (struct io_pgtable_cfg) { @@ -2863,7 +2814,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_d= omain *smmu_domain, if (enable_dirty) pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_HD; fmt =3D ARM_64_LPAE_S1; - finalise_stage_fn =3D arm_smmu_domain_finalise_s1; break; } case ARM_SMMU_DOMAIN_S2: @@ -2872,7 +2822,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_d= omain *smmu_domain, pgtbl_cfg.ias =3D smmu->ias; pgtbl_cfg.oas =3D smmu->oas; fmt =3D ARM_64_LPAE_S2; - finalise_stage_fn =3D arm_smmu_domain_finalise_s2; if ((smmu->features & ARM_SMMU_FEAT_S2FWB) && (flags & IOMMU_HWPT_ALLOC_NEST_PARENT)) pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_S2FWB; @@ -2890,13 +2839,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_= domain *smmu_domain, smmu_domain->domain.geometry.force_aperture =3D true; if (enable_dirty && smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) smmu_domain->domain.dirty_ops =3D &arm_smmu_dirty_ops; - - ret =3D finalise_stage_fn(smmu, smmu_domain); - if (ret < 0) { - free_io_pgtable_ops(pgtbl_ops); - return ret; - } - smmu_domain->pgtbl_ops =3D pgtbl_ops; smmu_domain->smmu =3D smmu; return 0; --=20 2.43.0 From nobody Sat Feb 7 22:07:18 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010033.outbound.protection.outlook.com [52.101.61.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B38AF34DCD6 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:58.9017 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed9fb169-55ff-4343-1fac-08de59550ee9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000147.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6873 Content-Type: text/plain; charset="utf-8" VMM needs a domain holding the mappings between gPA to hPA. It can be an S1 domain or an S2 nesting parent domain, depending on whether the VM is built with a vSMMU or not. Given that the IOAS for this gPA mapping is the same across SMMU instances, this domain can be shared across devices even if they sit behind different SMMUs, so long as the underlying page table is compatible between the SMMU instances. There is no direct information about the page table from the master device, but a comparison can be done between the physical SMMU that the domain was allocated for and the physical SMMU that the device is behind. Replace the smmu test in arm_smmu_attach_dev() and arm_vsmmu_init() with a compatibility test for the S1 and S2 cases respectively. The compatibility test goes through the physical SMMU parameters that were used to decide the page table formats. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 20 +++++++++++++++++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c7b054eb062a..c4bea9f7f4f1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -982,6 +982,26 @@ struct arm_smmu_nested_domain { __le64 ste[2]; }; =20 +static inline bool +arm_smmu_domain_can_share(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *new_smmu) +{ + struct arm_smmu_device *base_smmu =3D smmu_domain->smmu; + + if (base_smmu =3D=3D new_smmu) + return true; + /* Only support identical SMMUs for now */ + if (base_smmu->features !=3D new_smmu->features) + return false; + if (base_smmu->iommu.ops !=3D new_smmu->iommu.ops) + return false; + if (base_smmu->pgsize_bitmap !=3D new_smmu->pgsize_bitmap) + return false; + if (base_smmu->ias > new_smmu->ias || base_smmu->oas > new_smmu->oas) + return false; + return true; +} + /* The following are exposed for testing purposes. */ struct arm_smmu_entry_writer_ops; struct arm_smmu_entry_writer { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 33b336d494c3..6ecf98ca3bb8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -467,7 +467,7 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent_domain); int id; =20 - if (s2_parent->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(s2_parent, smmu)) return -EINVAL; =20 mutex_lock(&arm_smmu_asid_lock); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 19437ee6f4e1..4252418fc0a9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3635,7 +3635,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, state.master =3D master =3D dev_iommu_priv_get(dev); smmu =3D master->smmu; =20 - if (smmu_domain->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(smmu_domain, smmu)) return -EINVAL; =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { --=20 2.43.0