From nobody Sun Feb 8 11:43:47 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38C081F0995; Thu, 15 Jan 2026 00:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438610; cv=none; b=rs6BaBdde86qxsvpuvniEfNfhypDSicrwG1vp27ZO/0hBqIJpfXLD9wCOdiM7D/huLXm1wPZ4mK55y4phMFmMSmNH4HzKBU2s07yo6qQGoyX6PBV67QG1i9IpobBj8I05hZnTg5WwArha2km5K9o3Oq4abKirS4ogKgak5CSi5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438610; c=relaxed/simple; bh=N6YDEJuLVuowyOYXj01PWUfuKnkaZl5gKTEzGDsQ5Rc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=QRnLzvgVMEA05HI50/OmJTgZ4teX9hJtFYkHPC/9nkhU2i+WTlYYmNwYSmVOyDAhCayeiy40r+peQ5Su+eyGuqKJza+sGSWmKHrTVY/dGYEAHcwJLUg91AWUp+k7HofUShzQsWGrJpmONBI/HCXETZ6QZKu2kHQ5rxY0AMMXl7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vgBfF-0000000021v-3LZi; Thu, 15 Jan 2026 00:56:41 +0000 Date: Thu, 15 Jan 2026 00:56:39 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chen Minqiang , Xinfa Deng Subject: [PATCH net-next v2 1/6] dt-bindings: net: dsa: lantiq,gswip: use correct node name Message-ID: <83c6aa2578c6fa7b832a6146ef74b9f7aee0941d.1768438019.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ethernet PHYs should use nodes named 'ethernet-phy@'. Rename the Ethernet PHY nodes in the example to comply. Signed-off-by: Daniel Golle Reviewed-by: Rob Herring (Arm) --- v2: new patch Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/= Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml index 205b683849a53..9c0de536bae97 100644 --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml @@ -316,7 +316,7 @@ examples: #address-cells =3D <1>; #size-cells =3D <0>; =20 - switchphy0: switchphy@0 { + switchphy0: ethernet-phy@0 { reg =3D <0>; =20 leds { @@ -331,7 +331,7 @@ examples: }; }; =20 - switchphy1: switchphy@1 { + switchphy1: ethernet-phy@1 { reg =3D <1>; =20 leds { --=20 2.52.0 From nobody Sun Feb 8 11:43:47 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 601421CDFCA; Thu, 15 Jan 2026 00:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438622; cv=none; b=MQU1XTvHy5f7tLu9+IPff+AT98s3lne2zjv5Eqi3pWmBjf9cNxgwVp4oZYtT64t8QcF8DEV05Nesev1eEG/r3O9yZPDltspcL/1Vli88hn/Wg7l2nQTjWNZRoykbV3PSoXh12vplE3FcKgpgCKh0KWxWElt/xePdpnljWs1DG6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438622; c=relaxed/simple; bh=3+eC1JtO/mmuCAkNXbLPYZhWz1BhLg2cr3IBFwcz434=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UHdDfR48egxGGnEn7ZnfEaX4kBqfbk+NOQWV7GLZRMyC53gr21oQgbw5P/hWp43m1WrIFyn8JTgE8/Ym1fuSQvrNXr1axxzSNj52QK1bXuixzmdYTJwZGQ1PyD4Ew6QroZ0umIRFPOymZwYvJajwVB0gwZ+w/FnJL8JiRoucumg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vgBfU-0000000022G-1AgL; Thu, 15 Jan 2026 00:56:56 +0000 Date: Thu, 15 Jan 2026 00:56:53 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chen Minqiang , Xinfa Deng Subject: [PATCH net-next v2 2/6] dt-bindings: net: dsa: lantiq,gswip: add Intel GSW150 Message-ID: <10fdede364239ac04ef768983e5a18dbb37b4c55.1768438019.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible strings for the Intel GSW150 which is apparently identical or at least compatible with the Lantiq PEB7084 Ethernet switch IC. Signed-off-by: Daniel Golle Reviewed-by: Rob Herring (Arm) --- v2: no changes Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/= Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml index 9c0de536bae97..97842523772f4 100644 --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml @@ -19,6 +19,8 @@ maintainers: properties: compatible: enum: + - intel,gsw150 + - lantiq,peb7084 - lantiq,xrx200-gswip - lantiq,xrx300-gswip - lantiq,xrx330-gswip --=20 2.52.0 From nobody Sun Feb 8 11:43:47 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B1EB1E5207; Thu, 15 Jan 2026 00:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438636; cv=none; b=kQhYT5EEj5H4wbsFT9ej7GYz28V+i8JAdHNnQ3UTQvUbN4y/OiZn/8PKKSxXsmxWHO01Yn/+Be5AKMU2dRjrsDgLJqNEZlTZPepG80y5A1/EomLWQgjJdxmNTKYoOB9GnjvOcjt+iMPJiGECUbEXf+1XF9sBkl4KU0EPP3Vxkck= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438636; c=relaxed/simple; bh=J1vdRoroP5VlP7kmSmVqn8Ti/rHj0tfN8+QTbU4+dIE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=p3GkVAJvGfz/PZOhAA5LVzYWWajhEbzmKUhej+ekj9Rt5TLOjXfXIJaZtssSp6DKt5GwxXhXoEXLqrZEpVF1bZIYltMwd/qDbUZy6RwkTiL/K8c3FlzItiR+M7yfSgdO4JdH/Bxp856FqBDD86oWD77Ub1esbXjDVxo42MNZwSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vgBfi-0000000022s-0arS; Thu, 15 Jan 2026 00:57:10 +0000 Date: Thu, 15 Jan 2026 00:57:07 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chen Minqiang , Xinfa Deng Subject: [PATCH net-next v2 3/6] net: dsa: lantiq: allow arbitrary MII registers Message-ID: <572c7d91f8eb97bd72584018f9b5941dbfb2e46e.1768438019.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Lantiq GSWIP and MaxLinear GSW1xx drivers are currently relying on a hard-coded mapping of MII ports to their respective MII_CFG and MII_PCDU registers and only allow applying an offset to the port index. While this is sufficient for the currently supported hardware, the very similar Intel GSW150 (aka. Lantiq PEB7084) cannot be described using this arrangement. Introduce two arrays to specify the MII_CFG and MII_PCDU registers for each port, replacing the current bitmap used to safeguard MII ports as well as the port index offset. Signed-off-by: Daniel Golle --- v2: * introduce GSWIP_MAX_PORTS macro drivers/net/dsa/lantiq/lantiq_gswip.c | 30 ++++++++++++++++---- drivers/net/dsa/lantiq/lantiq_gswip.h | 6 ++-- drivers/net/dsa/lantiq/lantiq_gswip_common.c | 27 +++--------------- drivers/net/dsa/lantiq/mxl-gsw1xx.c | 30 ++++++++++++++++---- 4 files changed, 56 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index b094001a7c805..4a1be6a1df6fe 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -463,10 +463,20 @@ static void gswip_shutdown(struct platform_device *pd= ev) } =20 static const struct gswip_hw_info gswip_xrx200 =3D { - .max_ports =3D 7, + .max_ports =3D GSWIP_MAX_PORTS, .allowed_cpu_ports =3D BIT(6), - .mii_ports =3D BIT(0) | BIT(1) | BIT(5), - .mii_port_reg_offset =3D 0, + .mii_cfg =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [0] =3D GSWIP_MII_CFGp(0), + [1] =3D GSWIP_MII_CFGp(1), + [5] =3D GSWIP_MII_CFGp(5), + }, + .mii_pcdu =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [0] =3D GSWIP_MII_PCDU0, + [1] =3D GSWIP_MII_PCDU1, + [5] =3D GSWIP_MII_PCDU5, + }, .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, .pce_microcode =3D &gswip_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gswip_pce_microcode), @@ -474,10 +484,18 @@ static const struct gswip_hw_info gswip_xrx200 =3D { }; =20 static const struct gswip_hw_info gswip_xrx300 =3D { - .max_ports =3D 7, + .max_ports =3D GSWIP_MAX_PORTS, .allowed_cpu_ports =3D BIT(6), - .mii_ports =3D BIT(0) | BIT(5), - .mii_port_reg_offset =3D 0, + .mii_cfg =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [0] =3D GSWIP_MII_CFGp(0), + [5] =3D GSWIP_MII_CFGp(5), + }, + .mii_pcdu =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [0] =3D GSWIP_MII_PCDU0, + [5] =3D GSWIP_MII_PCDU5, + }, .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, .pce_microcode =3D &gswip_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gswip_pce_microcode), diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq= /lantiq_gswip.h index 2e0f2afbadbbc..524289db7c213 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -243,6 +243,8 @@ =20 #define GSWIP_VLAN_UNAWARE_PVID 0 =20 +#define GSWIP_MAX_PORTS 7 + struct gswip_pce_microcode { u16 val_3; u16 val_2; @@ -253,8 +255,8 @@ struct gswip_pce_microcode { struct gswip_hw_info { int max_ports; unsigned int allowed_cpu_ports; - unsigned int mii_ports; - int mii_port_reg_offset; + s16 mii_cfg[GSWIP_MAX_PORTS]; + s16 mii_pcdu[GSWIP_MAX_PORTS]; bool supports_2500m; const struct gswip_pce_microcode (*pce_microcode)[]; size_t pce_microcode_size; diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa= /lantiq/lantiq_gswip_common.c index e790f2ef75884..05b28b540661a 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c @@ -118,15 +118,11 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *= priv, u32 offset, static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set, int port) { - int reg_port; - /* MII_CFG register only exists for MII ports */ - if (!(priv->hw_info->mii_ports & BIT(port))) + if (priv->hw_info->mii_cfg[port] =3D=3D -1) return; =20 - reg_port =3D port + priv->hw_info->mii_port_reg_offset; - - regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask, + regmap_write_bits(priv->mii, priv->hw_info->mii_cfg[port], mask, set); } =20 @@ -604,28 +600,13 @@ static void gswip_mii_delay_setup(struct gswip_priv *= priv, struct dsa_port *dp, u32 tx_delay =3D GSWIP_MII_PCDU_TXDLY_DEFAULT; u32 rx_delay =3D GSWIP_MII_PCDU_RXDLY_DEFAULT; struct device_node *port_dn =3D dp->dn; - u16 mii_pcdu_reg; =20 /* As MII_PCDU registers only exist for MII ports, silently return * unless the port is an MII port */ - if (!(priv->hw_info->mii_ports & BIT(dp->index))) + if (priv->hw_info->mii_pcdu[dp->index] =3D=3D -1) return; =20 - switch (dp->index + priv->hw_info->mii_port_reg_offset) { - case 0: - mii_pcdu_reg =3D GSWIP_MII_PCDU0; - break; - case 1: - mii_pcdu_reg =3D GSWIP_MII_PCDU1; - break; - case 5: - mii_pcdu_reg =3D GSWIP_MII_PCDU5; - break; - default: - return; - } - /* legacy code to set default delays according to the interface mode */ switch (interface) { case PHY_INTERFACE_MODE_RGMII_ID: @@ -646,7 +627,7 @@ static void gswip_mii_delay_setup(struct gswip_priv *pr= iv, struct dsa_port *dp, of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); =20 - regmap_write_bits(priv->mii, mii_pcdu_reg, + regmap_write_bits(priv->mii, priv->hw_info->mii_pcdu[dp->index], GSWIP_MII_PCDU_TXDLY_MASK | GSWIP_MII_PCDU_RXDLY_MASK, GSWIP_MII_PCDU_TXDLY(tx_delay) | diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index f8ff8a604bf53..b74edb85e6d8e 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -702,8 +702,14 @@ static void gsw1xx_shutdown(struct mdio_device *mdiode= v) static const struct gswip_hw_info gsw12x_data =3D { .max_ports =3D GSW1XX_PORTS, .allowed_cpu_ports =3D BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT), - .mii_ports =3D BIT(GSW1XX_MII_PORT), - .mii_port_reg_offset =3D -GSW1XX_MII_PORT, + .mii_cfg =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [GSW1XX_MII_PORT] =3D GSWIP_MII_CFGp(0), + }, + .mii_pcdu =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [GSW1XX_MII_PORT] =3D GSWIP_MII_PCDU0, + }, .mac_select_pcs =3D gsw1xx_phylink_mac_select_pcs, .phylink_get_caps =3D &gsw1xx_phylink_get_caps, .supports_2500m =3D true, @@ -715,8 +721,14 @@ static const struct gswip_hw_info gsw12x_data =3D { static const struct gswip_hw_info gsw140_data =3D { .max_ports =3D GSW1XX_PORTS, .allowed_cpu_ports =3D BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT), - .mii_ports =3D BIT(GSW1XX_MII_PORT), - .mii_port_reg_offset =3D -GSW1XX_MII_PORT, + .mii_cfg =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [GSW1XX_MII_PORT] =3D GSWIP_MII_CFGp(0), + }, + .mii_pcdu =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [GSW1XX_MII_PORT] =3D GSWIP_MII_PCDU0, + }, .mac_select_pcs =3D gsw1xx_phylink_mac_select_pcs, .phylink_get_caps =3D &gsw1xx_phylink_get_caps, .supports_2500m =3D true, @@ -728,8 +740,14 @@ static const struct gswip_hw_info gsw140_data =3D { static const struct gswip_hw_info gsw141_data =3D { .max_ports =3D GSW1XX_PORTS, .allowed_cpu_ports =3D BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT), - .mii_ports =3D BIT(GSW1XX_MII_PORT), - .mii_port_reg_offset =3D -GSW1XX_MII_PORT, + .mii_cfg =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [GSW1XX_MII_PORT] =3D GSWIP_MII_CFGp(0), + }, + .mii_pcdu =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [GSW1XX_MII_PORT] =3D GSWIP_MII_PCDU0, + }, .mac_select_pcs =3D gsw1xx_phylink_mac_select_pcs, .phylink_get_caps =3D gsw1xx_phylink_get_caps, .pce_microcode =3D &gsw1xx_pce_microcode, --=20 2.52.0 From nobody Sun Feb 8 11:43:47 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B831B1D6DB5; Thu, 15 Jan 2026 00:57:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438674; cv=none; b=RtdyAfShL+15weyA99zRlU3bkum4Q9CfZ7qBur2YDEwFkBPYnlRREhxHJ2hNi3I6gt5YbU/T6CKbJBEnTykjD3gmLXOyjhfFLdQ5Ebs5PKQKoWu5TujODyrgIfDyfrzWcKngt/EJ3NB7FOYsTyB76so6sFemKBwglXWQ0RFXVkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438674; c=relaxed/simple; bh=2LqJIdefRaNXJiIQo+30IbBciuqMp20axNcumVRmTtg=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FLMREUYkv5VZRrX+ec3cCmGG8T6z+rX9ks56sAB7bHjgVFR0VEs3o3zmUs1MzKn+oA2ektFV9nInkLE3X7K8ETyqoWwzUyBc80FV/UvB99/3avQDBt91vuVXINo0y34ARGl94xNkmKTBh3W5au5mTCxZG+IHcbVjgEWTMtGpkEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vgBgK-00000000237-2JHx; Thu, 15 Jan 2026 00:57:48 +0000 Date: Thu, 15 Jan 2026 00:57:45 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 4/6] net: dsa: lantiq: clean up phylink_get_caps switch statement Message-ID: <898d542a0adee121ae779c0baa464fe8cee0166f.1768438019.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use case ranges for phylink_get_caps and remove the redundant "port N:" from the comments. Suggested-by: Vladimir Oltean Signed-off-by: Daniel Golle --- v2: new patch drivers/net/dsa/lantiq/lantiq_gswip.c | 12 +++--------- drivers/net/dsa/lantiq/mxl-gsw1xx.c | 11 +++++------ 2 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index 4a1be6a1df6fe..8d42758e5d2ba 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -33,8 +33,7 @@ static void gswip_xrx200_phylink_get_caps(struct dsa_swit= ch *ds, int port, struct phylink_config *config) { switch (port) { - case 0: - case 1: + case 0 ... 1: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -44,9 +43,7 @@ static void gswip_xrx200_phylink_get_caps(struct dsa_swit= ch *ds, int port, config->supported_interfaces); break; =20 - case 2: - case 3: - case 4: + case 2 ... 4: case 6: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); @@ -75,10 +72,7 @@ static void gswip_xrx300_phylink_get_caps(struct dsa_swi= tch *ds, int port, config->supported_interfaces); break; =20 - case 1: - case 2: - case 3: - case 4: + case 1 ... 4: case 6: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index b74edb85e6d8e..718837bf1c1ef 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -511,14 +511,12 @@ static void gsw1xx_phylink_get_caps(struct dsa_switch= *ds, int port, MAC_10 | MAC_100 | MAC_1000; =20 switch (port) { - case 0: - case 1: - case 2: - case 3: + case 0 ... 3: /* built-in PHYs */ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; - case 4: /* port 4: SGMII */ + + case 4: /* SGMII */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -529,7 +527,8 @@ static void gsw1xx_phylink_get_caps(struct dsa_switch *= ds, int port, config->mac_capabilities |=3D MAC_2500FD; } return; /* no support for EEE on SGMII port */ - case 5: /* port 5: RGMII or RMII */ + + case 5: /* RGMII or RMII */ __set_bit(PHY_INTERFACE_MODE_RMII, config->supported_interfaces); phy_interface_set_rgmii(config->supported_interfaces); --=20 2.52.0 From nobody Sun Feb 8 11:43:47 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EAC61E9B12; Thu, 15 Jan 2026 00:58:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438686; cv=none; b=bDpUW1CHmFg0Y9xcjwV+JFK2TSU1SqG3cNtJmy1Y0Jo3c0+qA7v6FTVkUClSzX7unlqcGjG6vdO+1js30yz7LCjj0YkRHPKU9XiCUqmXhpH9XxlTRS6GW/YzdOcYidAzCq7WVN/ZkcBtkh4BaaMvIR1cxSkL/F00tWlDqd5qEYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438686; c=relaxed/simple; bh=pLaOUcg94Uzgqfmz6axjNmS+FGc3hszC6CinRdR05JE=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=o48/zcyQJCImkftWl6D0+YFciqIWVri13zq277o4Gf4cX7Hj8rTjGJdojISfk2KMxV8gM5J3WKs5y5gu8mELWIia0aq3l0BtXNjD1oGRlJBjonInSUBQhwyGUfTEImwwKnrUidGvEFJ8zwFXxDkSinAngIW01RTgak58c7yMy3c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vgBgX-0000000023I-0ISG; Thu, 15 Jan 2026 00:58:01 +0000 Date: Thu, 15 Jan 2026 00:57:58 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 5/6] net: dsa: mxl-gsw1xx: only setup SerDes PCS if it exists Message-ID: <6adf5849d2f2f5c123e001aab8fd6bbbde1a6b4e.1768438019.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Older Intel GSW150 chip doesn't have a SGMII/1000Base-X/2500Base-X PCS. Prepare for supporting Intel GSW150 by skipping PCS reset and initialization in case no .mac_select_pcs operation is defined. Signed-off-by: Daniel Golle --- v2: new patch drivers/net/dsa/lantiq/mxl-gsw1xx.c | 37 ++++++++++++++++++----------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index 718837bf1c1ef..d6258fe3afb8e 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -578,6 +578,28 @@ static struct regmap *gsw1xx_regmap_init(struct gsw1xx= _priv *priv, priv, &config); } =20 +static int gsw1xx_serdes_pcs_init(struct gsw1xx_priv *priv) +{ + /* do nothing if the chip doesn't have a SerDes PCS */ + if (!priv->gswip.hw_info->mac_select_pcs) + return 0; + + priv->pcs.ops =3D &gsw1xx_pcs_ops; + priv->pcs.poll =3D true; + __set_bit(PHY_INTERFACE_MODE_SGMII, + priv->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + priv->pcs.supported_interfaces); + if (priv->gswip.hw_info->supports_2500m) + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + priv->pcs.supported_interfaces); + priv->tbi_interface =3D PHY_INTERFACE_MODE_NA; + + /* assert SGMII reset to power down SGMII unit */ + return regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, + GSW1XX_RST_REQ_SGMII_SHELL); +} + static int gsw1xx_probe(struct mdio_device *mdiodev) { struct device *dev =3D &mdiodev->dev; @@ -630,20 +652,7 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) if (IS_ERR(priv->shell)) return PTR_ERR(priv->shell); =20 - priv->pcs.ops =3D &gsw1xx_pcs_ops; - priv->pcs.poll =3D true; - __set_bit(PHY_INTERFACE_MODE_SGMII, - priv->pcs.supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_1000BASEX, - priv->pcs.supported_interfaces); - if (priv->gswip.hw_info->supports_2500m) - __set_bit(PHY_INTERFACE_MODE_2500BASEX, - priv->pcs.supported_interfaces); - priv->tbi_interface =3D PHY_INTERFACE_MODE_NA; - - /* assert SGMII reset to power down SGMII unit */ - ret =3D regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, - GSW1XX_RST_REQ_SGMII_SHELL); + ret =3D gsw1xx_serdes_pcs_init(priv); if (ret < 0) return ret; =20 --=20 2.52.0 From nobody Sun Feb 8 11:43:47 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF3D41E9B3F; Thu, 15 Jan 2026 00:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438698; cv=none; b=VBiBk5va1kVn6/Sd8/C/0a3kgcrJsPhGNtryJiyOOIydL2/9Pxae7VPhyaq75ix0c3Qn4Q5oB+enGmLhath+6HKluXgKNr2L4SDBUEnnr3dt7ZH584s9hI3O1lWEkruR0J8UIqciQcvgRFgaEZya3V9i4+1Cx3x3M2OdVDs5T5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768438698; c=relaxed/simple; bh=Jq5fayYZSIno13tZ3ohP2Nj/cABYxi3lKIkTx+Wr4GY=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=PAqENyhh+waKkwSO1YYTGgyyylPB6VeHK06YlqW86rZIYbdG6suBxVpWlj5gkHGBriRB6yhnyjHKFA0/knas2lfcM8EjT5xvsmJz1Kzl0GXmGAWpyG09+U9d+6OY11uDhbJ8V7hCiSKyz9FUy3ugGXl4du5XMP1/6nyQJy9suLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vgBgi-0000000023U-20is; Thu, 15 Jan 2026 00:58:12 +0000 Date: Thu, 15 Jan 2026 00:58:09 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 6/6] net: dsa: mxl-gsw1xx: add support for Intel GSW150 Message-ID: <03e4cd6bcd469d261b1916b2135437b0403a7455.1768438019.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the Intel GSW150 (aka. Lantiq PEB7084) switch IC to the mxl-gsw1xx driver. This switch comes with 5 Gigabit Ethernet copper ports (Intel XWAY PHY11G (xRX v1.2 integrated) PHYs) as well as one GMII/RGMII and one RGMII port. Signed-off-by: Daniel Golle --- v2: clean-up phylink_get_caps drivers/net/dsa/lantiq/mxl-gsw1xx.c | 61 ++++++++++++++++++++++++++--- drivers/net/dsa/lantiq/mxl-gsw1xx.h | 2 + 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index d6258fe3afb8e..508f960524686 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -502,6 +502,14 @@ static const struct phylink_pcs_ops gsw1xx_pcs_ops =3D= { .pcs_link_up =3D gsw1xx_pcs_link_up, }; =20 +static void gsw1xx_phylink_get_lpi_caps(struct phylink_config *config) +{ + config->lpi_capabilities =3D MAC_100FD | MAC_1000FD; + config->lpi_timer_default =3D 20; + memcpy(config->lpi_interfaces, config->supported_interfaces, + sizeof(config->lpi_interfaces)); +} + static void gsw1xx_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -535,10 +543,32 @@ static void gsw1xx_phylink_get_caps(struct dsa_switch= *ds, int port, break; } =20 - config->lpi_capabilities =3D MAC_100FD | MAC_1000FD; - config->lpi_timer_default =3D 20; - memcpy(config->lpi_interfaces, config->supported_interfaces, - sizeof(config->lpi_interfaces)); + gsw1xx_phylink_get_lpi_caps(config); +} + +static void gsw150_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000; + + switch (port) { + case 0 ... 4: /* built-in PHYs */ + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; + + case 5: /* GMII or RGMII */ + __set_bit(PHY_INTERFACE_MODE_GMII, + config->supported_interfaces); + fallthrough; + + case 6: /* RGMII */ + phy_interface_set_rgmii(config->supported_interfaces); + break; + } + + gsw1xx_phylink_get_lpi_caps(config); } =20 static struct phylink_pcs *gsw1xx_phylink_mac_select_pcs(struct phylink_co= nfig *config, @@ -763,11 +793,32 @@ static const struct gswip_hw_info gsw141_data =3D { .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, }; =20 +static const struct gswip_hw_info gsw150_data =3D { + .max_ports =3D GSW150_PORTS, + .allowed_cpu_ports =3D BIT(5) | BIT(6), + .mii_cfg =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [5] =3D 0, + [6] =3D 10, + }, + .mii_pcdu =3D { + [0 ... GSWIP_MAX_PORTS - 1] =3D -1, + [5] =3D 1, + [6] =3D 11, + }, + .phylink_get_caps =3D gsw150_phylink_get_caps, + .pce_microcode =3D &gsw1xx_pce_microcode, + .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), + .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, +}; + /* * GSW125 is the industrial temperature version of GSW120. * GSW145 is the industrial temperature version of GSW140. */ static const struct of_device_id gsw1xx_of_match[] =3D { + { .compatible =3D "intel,gsw150", .data =3D &gsw150_data }, + { .compatible =3D "lantiq,peb7084", .data =3D &gsw150_data }, { .compatible =3D "maxlinear,gsw120", .data =3D &gsw12x_data }, { .compatible =3D "maxlinear,gsw125", .data =3D &gsw12x_data }, { .compatible =3D "maxlinear,gsw140", .data =3D &gsw140_data }, @@ -791,5 +842,5 @@ static struct mdio_driver gsw1xx_driver =3D { mdio_module_driver(gsw1xx_driver); =20 MODULE_AUTHOR("Daniel Golle "); -MODULE_DESCRIPTION("Driver for MaxLinear GSW1xx ethernet switch"); +MODULE_DESCRIPTION("Driver for Intel/MaxLinear GSW1xx Ethernet switch"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.h b/drivers/net/dsa/lantiq/m= xl-gsw1xx.h index 38e03c048a26c..087587f62e5e1 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.h +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.h @@ -10,6 +10,8 @@ #include =20 #define GSW1XX_PORTS 6 +#define GSW150_PORTS 7 + /* Port used for RGMII or optional RMII */ #define GSW1XX_MII_PORT 5 /* Port used for SGMII */ --=20 2.52.0