From nobody Sun Feb 8 05:41:38 2026 Received: from mg.richtek.com (mg.richtek.com [220.130.44.152]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 90BC0219A86; Fri, 19 Dec 2025 06:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.130.44.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766126410; cv=none; b=U6HWt1iv4+0xQAgTb/FHVuQrmGMVOWa7PjlevK5iY1Ir2cdMECe46ctNEYMNGrWhP8gnw4DEO7Ry+SLjlvYyTrTqgU9x1k32NpT6ZwUV5vbY0CZIYf1cbVsXOTB+Z72qmB4fFsGx3mLM5K17IhWAiz6A3CunNcqp1SUPK81lLKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766126410; c=relaxed/simple; bh=1wx2gJqC+SBVYT7bzbnx0MXl4kI7SgA47eW8RiEvZno=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Hl5CxS9Uy7iuc6QcCrOcRpWPK8WEsw5vzTHYSijK3FE9mGj/OG64m6qCm286s4d83e6J3yrerBOhlSnJrlVQNFeR5XTkw4YbvUUiJXusGdp9EZ2ojTfUH5lr7qNrLOmwLRwI4e+Z++pxHw7Tnz4aAkJF+8A5kAqTO+jEk9L095A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=richtek.com; spf=pass smtp.mailfrom=richtek.com; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b=Eb3RmaxH; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b=5bCgV8Sg; arc=none smtp.client-ip=220.130.44.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=richtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=richtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b="Eb3RmaxH"; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b="5bCgV8Sg" X-MailGates: (SIP:2,PASS,NONE)(compute_score:DELIVER,40,3) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=richtek.com; s=richtek; t=1766126405; bh=2SzYWE3T4k80Utboszj2Ocei6ZisLjR74Q2ygnLnRz4=; l=1156; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Eb3RmaxHqD0E9SPvnuLvfaZalpslcRcxr62qYwsjIAQG4PpAoSKg/oZj4UN88giwp g2UVJu39k7k9Pm10VVTWcEC56RMxBEwDtbPiu4jSGAFisK8sPKTuzZOiCDcx+yjtxp g0dQcIpFoIXpGb0izzPqoyKRa7gVfmS4V7X56dGxrkKmxBVjO6dy3HSu5ETFjkMFXR 4UzEI4HlbK100mvSayB+Ls+jRUzHNRozR/J29rNP3EN7eQLFccelbGPnydhezQbeZi TSTMkR4eoV7Wsbw9aX/FLzTgNvsDvpW3SsfrBzCsSVKA9eq1+M2N/H9LpBVlZi6ZMb gLA1TciwAFFbw== Received: from 192.168.8.21 by mg.richtek.com with MailGates ESMTP Server V3.0(1128086:0:AUTH_RELAY) (envelope-from ); Fri, 19 Dec 2025 14:40:03 +0800 (CST) X-MailGates: (compute_score:DELIVER,40,3) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=richtek.com; s=richtek; t=1766126403; bh=2SzYWE3T4k80Utboszj2Ocei6ZisLjR74Q2ygnLnRz4=; l=1156; h=From:To:Subject:Date:Message-ID:MIME-Version; b=5bCgV8SgxMTIdVy3On5b1sOgOCnS6+eRc0zMNBwpurXQpuKm2pUm9mSH2dAz/+kXs PnnoqjpWirxdBESr4AHtfUnp4sHlGJleLAxDFktYojYwy/+PdG13HG0Mq/eM4KRZCz 4CEtGjXYp/ruFF0YX7E2AQKHdGv75VGepZ3LKZR2wlTu6+cNhiHXVgNcuKBbZWdXSf kAcwHnMdc+DaqfKdfRhJCgfBa5CschUi4xWGglAbhpNE6pvTrlK+bgqyPMhojvD7tu qJrdlushd9r23M+t6pFK8606GSqaqE4Utm7ftjfxJxwkZiR4A7h2gQcd6rd9CXlbYu o5dnjsN/t/s1A== Received: from 192.168.10.46 by mg.richtek.com with MailGates ESMTPS Server V6.0(2572462:0:AUTH_RELAY) (envelope-from ) (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256/256); Fri, 19 Dec 2025 14:36:24 +0800 (CST) Received: from ex3.rt.l (192.168.10.46) by ex3.rt.l (192.168.10.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Fri, 19 Dec 2025 14:36:24 +0800 Received: from git-send.richtek.com (192.168.10.154) by ex3.rt.l (192.168.10.45) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Fri, 19 Dec 2025 14:36:24 +0800 From: To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Liam Girdwood , ChiYuan Huang , Alan Lan , , Subject: [PATCH 1/2] dt-bindings: regulator: rt5739: Add compatible for rt8092 Date: Fri, 19 Dec 2025 14:36:19 +0800 Message-ID: <9b67b2d2b4268d356f41ae2d0c3202e7813ea6b1.1766125676.git.cy_huang@richtek.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: ChiYuan Huang Append rt8092 compatible in rt5739 document. Compared to rt5739, RT8092 can offer up to 4A output current. Signed-off-by: ChiYuan Huang Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/regulator/richtek,rt5739.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/richtek,rt5739.yam= l b/Documentation/devicetree/bindings/regulator/richtek,rt5739.yaml index e95e046e9ed6..983f4c1ce380 100644 --- a/Documentation/devicetree/bindings/regulator/richtek,rt5739.yaml +++ b/Documentation/devicetree/bindings/regulator/richtek,rt5739.yaml @@ -15,6 +15,10 @@ description: | supply of 2.5V to 5.5V. It can provide up to 3.5A continuous current capability at over 80% high efficiency. =20 + The RT8092 is similar type buck converter. Compared to RT5739, it can of= fer + up to 4A output current and more output voltage range to meet the applic= ation + on most mobile products. + allOf: - $ref: regulator.yaml# =20 @@ -23,6 +27,7 @@ properties: enum: - richtek,rt5733 - richtek,rt5739 + - richtek,rt8092 =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sun Feb 8 05:41:38 2026 Received: from mg.richtek.com (mg.richtek.com [220.130.44.152]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 06E3F2D94B4; Fri, 19 Dec 2025 06:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.130.44.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766126414; cv=none; b=Pp5CCTgAWcKnvZZBFPCK8xcaKD78zCUWRXRoOiFtxzeIhm4lQt4s8JGlOWMolDoyPGC6fpdd8lUqsNCPP+y0oiV9Nnn1EOhzlgZT3oiVUHeCjGA6JSr2cK2QpRgCrJbKHWZ6wE5TKZzS3kZ4EnR8f98EP6ZwJ16D/BbmIa3Vzvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766126414; c=relaxed/simple; bh=VhlJGQS64FeoyKzziNvMJy5neikLCBZ7PXZ1DVTJS4o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QRPwuh4v4JPH5SbNwWiVChdeq2GNdS8egmqZnKRn764z+ywFs/M9LiwUZ1faV+EJCVABPwCf1ZXwK9FpQBe0CjAGKvrO4lzdDRcchZ/vqYsgjgUBzN8DcmUhcpFn1fmj4bS3gEdqnwJtldpoIZ07nk2M2CQBH5peya8fyCmNrf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=richtek.com; spf=pass smtp.mailfrom=richtek.com; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b=tXKRAe5Q; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b=X9AJWiV4; arc=none smtp.client-ip=220.130.44.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=richtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=richtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b="tXKRAe5Q"; dkim=pass (2048-bit key) header.d=richtek.com header.i=@richtek.com header.b="X9AJWiV4" X-MailGates: (SIP:2,PASS,NONE)(compute_score:DELIVER,40,3) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=richtek.com; s=richtek; t=1766126409; bh=R66MbqIwbyu8wG2Eyksdh3AQD2+LCWxOX+Toxv1X8JI=; l=11583; h=From:To:Subject:Date:Message-ID:MIME-Version; b=tXKRAe5QjHnuikuUORYW9RPGtDInHT8K0FCF2/7y9EHlykfinySHymIlxuaOUcDmR 9R7xqmTlezptmRmi8glJVaCCNWX1fM7dhB6XF7oQJRy9+/sMPIX2aIaHtuvoSJa2yJ 7crvmYBEZEvuL0fGsfedJsVxp96+zgGM2jWX/ag+Zgiu9MbsjdqayRZG+l+xziGann T5ZGzyYsvdYGqBUKfz2zHCQ7YYWVvVLCXq2QJ1fk3HcxadoMxlySuKCyPtioc8TBmW SJejtruSomQ0vHX3A7dX9GWMeXV3+MG5UW93m2Q/cOVWX882fjRj2A9C8m6Gu8gURT qIDge2hoYGU6w== Received: from 192.168.8.21 by mg.richtek.com with MailGates ESMTP Server V3.0(1128086:0:AUTH_RELAY) (envelope-from ); Fri, 19 Dec 2025 14:40:04 +0800 (CST) X-MailGates: (compute_score:DELIVER,40,3) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=richtek.com; s=richtek; t=1766126403; bh=R66MbqIwbyu8wG2Eyksdh3AQD2+LCWxOX+Toxv1X8JI=; l=11583; h=From:To:Subject:Date:Message-ID:MIME-Version; b=X9AJWiV4FB71eOWJMGY9mvXSzDsjvNnhPijkhZ3GBB1wOVCU/yVn9TeFxhP4qZ7oG bVA8Kj5RnuvL6KQUXpbxQ2WNg+gDV4dLs6okdhTfa1tf+MBZI7Zxh6KzJgAj1d49tL RkIkmDA8ICTf/cxE65RBaBhBaZjMq9FhF10JkWFBiBqzJZBe+znNZ3kiR6rMK0U2GY kKtaZCLy+9liq6gvaSQrvCMEbSC7L46pLw/rESDNkEh2oP9jwKZWgQchg6/tfNPGwI yC3gtwnWafBbk9KzsN9IoP/efRRD4MkTivZJ7E0TbBXIh47TEuWpEcxcAtydXnZh8J qLIfC9WkrSFjg== Received: from 192.168.10.46 by mg.richtek.com with MailGates ESMTPS Server V6.0(2572443:0:AUTH_RELAY) (envelope-from ) (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256/256); Fri, 19 Dec 2025 14:36:29 +0800 (CST) Received: from ex3.rt.l (192.168.10.46) by ex3.rt.l (192.168.10.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Fri, 19 Dec 2025 14:36:24 +0800 Received: from git-send.richtek.com (192.168.10.154) by ex3.rt.l (192.168.10.45) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Fri, 19 Dec 2025 14:36:24 +0800 From: To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Liam Girdwood , ChiYuan Huang , Alan Lan , , Subject: [PATCH 2/2] regulator: Add rt8092 support Date: Fri, 19 Dec 2025 14:36:20 +0800 Message-ID: X-Mailer: git-send-email 2.43.5 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: ChiYuan Huang RT8092 is a 3MHz 4A efficiency step-down converter with I2C control interface. It can support wide output range from 0.7 to 5.5V, based on the voltage bank selection. Signed-off-by: ChiYuan Huang --- drivers/regulator/Kconfig | 9 ++ drivers/regulator/Makefile | 1 + drivers/regulator/rt8092.c | 313 +++++++++++++++++++++++++++++++++++++ 3 files changed, 323 insertions(+) create mode 100644 drivers/regulator/rt8092.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index d2335276cce5..ca68d5e3c13c 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1394,6 +1394,15 @@ config REGULATOR_RT6245 It can support up to 14A output current and adjustable output voltage from 0.4375V to 1.3875V, per step 12.5mV. =20 +config REGULATOR_RT8092 + tristate "Richtek RT8092 voltage regulator" + depends on I2C + select REGMAP_I2C + help + The RT8092 is a peak-current mode PWM step-down DC/DC converter with + I2C control interface. It is capable of delivering 4A continuing + current over a wide input range from 2.5V to 5.5V. + config REGULATOR_RTQ2134 tristate "Richtek RTQ2134 SubPMIC Regulator" depends on I2C diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 1beba1493241..5757a450d135 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -161,6 +161,7 @@ obj-$(CONFIG_REGULATOR_RT5759) +=3D rt5759-regulator.o obj-$(CONFIG_REGULATOR_RT6160) +=3D rt6160-regulator.o obj-$(CONFIG_REGULATOR_RT6190) +=3D rt6190-regulator.o obj-$(CONFIG_REGULATOR_RT6245) +=3D rt6245-regulator.o +obj-$(CONFIG_REGULATOR_RT8092) +=3D rt8092.o obj-$(CONFIG_REGULATOR_RTMV20) +=3D rtmv20-regulator.o obj-$(CONFIG_REGULATOR_RTQ2134) +=3D rtq2134-regulator.o obj-$(CONFIG_REGULATOR_RTQ6752) +=3D rtq6752-regulator.o diff --git a/drivers/regulator/rt8092.c b/drivers/regulator/rt8092.c new file mode 100644 index 000000000000..558bd04a2090 --- /dev/null +++ b/drivers/regulator/rt8092.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (c) 2025 Richtek Technology Corp. +// +// Author: ChiYuan Huang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RT8092_REG_MNTRPT 0x00 +#define RT8092_REG_VOUTH 0x10 +#define RT8092_REG_VOUTL 0x11 +#define RT8092_REG_PWMMODE 0x14 +#define RT8092_REG_EVENT 0x18 +#define RT8092_REG_VBANKH 0x1C +#define RT8092_REG_VBANKL 0x1D +#define RT8092_REG_VBOUND 0x1E + +#define RT8092_TSDEVT_MASK BIT(7) +#define RT8092_PGEVT_MASK BIT(0) +#define RT8092_VSEL_MASK GENMASK(6, 0) +#define RT8092_VOUTEN_MASK BIT(7) +#define RT8092_FPWML_MASK BIT(7) +#define RT8092_FPWMH_MASK BIT(6) +#define RT8092_OCPEVT_MASK BIT(7) +#define RT8092_SCPEVT_MASK BIT(4) +#define RT8092_VINUVEVT_MASK BIT(1) +#define RT8092_VBANK_MASK GENMASK(1, 0) + +#define RT8092_MODE_AUTO 0 +#define RT8092_MODE_FPWM 1 +#define RT8092_VOUT_BASEUV 303125 +#define RT8092_VOUT_STEPUV 3125 +#define RT8092_VOUT_MINSEL 15 +#define RT8092_NUM_VOLTS 128 +#define RT8092_INITSS_US 400 + +static int rt8092_get_vbank_index(struct regmap *regmap, bool vsel_high, u= nsigned int *vbank_idx) +{ + unsigned int vbank_reg =3D vsel_high ? RT8092_REG_VBANKH : RT8092_REG_VBA= NKL; + unsigned int index; + int ret; + + ret =3D regmap_read(regmap, vbank_reg, &index); + if (ret) + return ret; + + *vbank_idx =3D FIELD_GET(RT8092_VBANK_MASK, index); + return 0; +} + +static int rt8092_set_operating_mode(struct regulator_dev *rdev, unsigned = int mode) +{ + const struct regulator_desc *desc =3D rdev->desc; + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int mode_mask, mode_val; + + mode_mask =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH ? RT8092_FPWMH_MASK = : RT8092_FPWML_MASK; + + switch (mode) { + case REGULATOR_MODE_FAST: + mode_val =3D mode_mask; + break; + case REGULATOR_MODE_NORMAL: + mode_val =3D 0; + break; + default: + return -EINVAL; + } + + return regmap_update_bits(regmap, RT8092_REG_PWMMODE, mode_mask, mode_val= ); +} + +static unsigned int rt8092_get_operating_mode(struct regulator_dev *rdev) +{ + const struct regulator_desc *desc =3D rdev->desc; + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int mode_mask, mode_val; + int ret; + + mode_mask =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH ? RT8092_FPWMH_MASK = : RT8092_FPWML_MASK; + + ret =3D regmap_read(regmap, RT8092_REG_PWMMODE, &mode_val); + if (ret) + return REGULATOR_MODE_INVALID; + + return mode_val & mode_mask ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; +} + +static int rt8092_get_error_flags(struct regulator_dev *rdev, unsigned int= *flags) +{ + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int mntrpt, evtrpt, events =3D 0; + int ret; + + ret =3D regmap_read(regmap, RT8092_REG_MNTRPT, &mntrpt); + if (ret) + return ret; + + ret =3D regmap_read(regmap, RT8092_REG_EVENT, &evtrpt); + if (ret) + return ret; + + if (!(mntrpt & RT8092_PGEVT_MASK) || evtrpt & RT8092_VINUVEVT_MASK) + events |=3D REGULATOR_ERROR_UNDER_VOLTAGE; + + if (mntrpt & RT8092_TSDEVT_MASK) + events |=3D REGULATOR_ERROR_OVER_TEMP; + + if (evtrpt & RT8092_OCPEVT_MASK) + events |=3D REGULATOR_ERROR_OVER_CURRENT; + + if (evtrpt & RT8092_SCPEVT_MASK) + events |=3D REGULATOR_ERROR_FAIL; + + *flags =3D events; + return 0; +} + + +static int rt8092_set_suspend_voltage(struct regulator_dev *rdev, int uV) +{ + const struct regulator_desc *desc =3D rdev->desc; + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int vsel_reg, vsel_val, vbank_idx; + bool vsel_high; + int ret; + + vsel_reg =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH ? RT8092_REG_VOUTL : = RT8092_REG_VOUTH; + vsel_high =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH; + + ret =3D rt8092_get_vbank_index(regmap, vsel_high, &vbank_idx); + if (ret) + return ret; + + /* VOUT =3D (BASEUV + STEPUV * VSEL) * 2^vbank_idx */ + uV >>=3D vbank_idx; + if (uV < RT8092_VOUT_BASEUV) + return -EINVAL; + + vsel_val =3D (uV - RT8092_VOUT_BASEUV) / RT8092_VOUT_STEPUV; + if (vsel_val < RT8092_VOUT_MINSEL || vsel_val >=3D RT8092_NUM_VOLTS) + return -EINVAL; + + return regmap_update_bits(regmap, vsel_reg, RT8092_VSEL_MASK, vsel_val); +} + +static int rt8092_set_suspend_enable(struct regulator_dev *rdev) +{ + const struct regulator_desc *desc =3D rdev->desc; + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int enable_reg; + + enable_reg =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH ? RT8092_REG_VOUTL = : RT8092_REG_VOUTH; + return regmap_set_bits(regmap, enable_reg, RT8092_VOUTEN_MASK); +} + +static int rt8092_set_suspend_disable(struct regulator_dev *rdev) +{ + const struct regulator_desc *desc =3D rdev->desc; + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int enable_reg; + + enable_reg =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH ? RT8092_REG_VOUTL = : RT8092_REG_VOUTH; + return regmap_clear_bits(regmap, enable_reg, RT8092_VOUTEN_MASK); +} + +static int rt8092_set_suspend_mode(struct regulator_dev *rdev, unsigned in= t mode) +{ + const struct regulator_desc *desc =3D rdev->desc; + struct regmap *regmap =3D rdev_get_regmap(rdev); + unsigned int mode_mask, mode_val; + + mode_mask =3D desc->vsel_reg =3D=3D RT8092_REG_VOUTH ? RT8092_FPWML_MASK = : RT8092_FPWMH_MASK; + + switch (mode) { + case REGULATOR_MODE_FAST: + mode_val =3D mode_mask; + break; + case REGULATOR_MODE_NORMAL: + mode_val =3D 0; + break; + default: + return -EINVAL; + } + + return regmap_update_bits(regmap, RT8092_REG_PWMMODE, mode_mask, mode_val= ); +} + +static const struct regulator_ops rt8092_regulator_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D rt8092_set_operating_mode, + .get_mode =3D rt8092_get_operating_mode, + .get_error_flags =3D rt8092_get_error_flags, + .set_suspend_voltage =3D rt8092_set_suspend_voltage, + .set_suspend_enable =3D rt8092_set_suspend_enable, + .set_suspend_disable =3D rt8092_set_suspend_disable, + .set_suspend_mode =3D rt8092_set_suspend_mode, +}; + +static unsigned int rt8092_of_map_mode(unsigned int mode) +{ + switch (mode) { + case RT8092_MODE_AUTO: + return REGULATOR_MODE_NORMAL; + case RT8092_MODE_FPWM: + return REGULATOR_MODE_FAST; + default: + return REGULATOR_MODE_INVALID; + } +} + +static const struct regmap_config rt8092_regmap_cfg =3D { + .name =3D "rt8092", + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D RT8092_REG_VBOUND, +}; + +static int rt8092_probe(struct i2c_client *i2c) +{ + unsigned int vbank_idx, min_uV, step_uV; + struct regulator_config cfg =3D {}; + struct device *dev =3D &i2c->dev; + struct regulator_desc *desc; + struct regulator_dev *rdev; + struct gpio_desc *enable; + struct regmap *regmap; + bool vsel_high; + int ret; + + desc =3D devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + enable =3D devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(enable)) + return dev_err_probe(dev, PTR_ERR(enable), "Failed get 'enable' gpio\n"); + + regmap =3D devm_regmap_init_i2c(i2c, &rt8092_regmap_cfg); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); + + vsel_high =3D device_property_read_bool(dev, "richtek,vsel-active-high"); + + ret =3D rt8092_get_vbank_index(regmap, vsel_high, &vbank_idx); + if (ret) + return dev_err_probe(dev, ret, "Failed to get VOUT bank index\n"); + + /* + * step VOUT =3D STEP_UV * 2^vbank_idx + * min VOUT =3D (BASEUV + STEPUV * VMIN_SEL) * 2^vbank_idx + */ + step_uV =3D RT8092_VOUT_STEPUV << vbank_idx; + min_uV =3D (RT8092_VOUT_BASEUV + RT8092_VOUT_STEPUV * RT8092_VOUT_MINSEL)= << vbank_idx; + + desc->name =3D "rt8092"; + desc->owner =3D THIS_MODULE; + desc->type =3D REGULATOR_VOLTAGE; + desc->ops =3D &rt8092_regulator_ops; + desc->n_voltages =3D RT8092_NUM_VOLTS; + desc->min_uV =3D min_uV; + desc->uV_step =3D step_uV; + desc->linear_min_sel =3D RT8092_VOUT_MINSEL; + desc->enable_reg =3D desc->vsel_reg =3D vsel_high ? RT8092_REG_VOUTH : RT= 8092_REG_VOUTL; + desc->vsel_mask =3D RT8092_VSEL_MASK; + desc->enable_mask =3D RT8092_VOUTEN_MASK; + desc->enable_time =3D RT8092_INITSS_US; + desc->of_map_mode =3D rt8092_of_map_mode; + + cfg.dev =3D dev; + cfg.of_node =3D dev_of_node(dev); + cfg.init_data =3D of_get_regulator_init_data(dev, dev_of_node(dev), desc); + + rdev =3D devm_regulator_register(dev, desc, &cfg); + if (IS_ERR(rdev)) + return dev_err_probe(dev, PTR_ERR(rdev), "Failed to register regulator\n= "); + + return 0; +} + +static const struct of_device_id rt8092_device_tables[] =3D { + { .compatible =3D "richtek,rt8092" }, + {} +}; +MODULE_DEVICE_TABLE(of, rt8092_device_tables); + +static struct i2c_driver rt8092_driver =3D { + .driver =3D { + .name =3D "rt8092", + .of_match_table =3D rt8092_device_tables, + }, + .probe =3D rt8092_probe, +}; +module_i2c_driver(rt8092_driver); + +MODULE_AUTHOR("ChiYuan Huang "); +MODULE_DESCRIPTION("Richtek RT8092 Regulator Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1