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Thu, 18 Dec 2025 12:27:13 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v1 1/9] iommu/arm-smmu-v3: Pass in ssid to arm_smmu_make_s1_cd() Date: Thu, 18 Dec 2025 12:26:47 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|DS0PR12MB6390:EE_ X-MS-Office365-Filtering-Correlation-Id: fee3961b-c61a-4581-d24b-08de3e73e240 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KIZ2Fl6InO6LSii3MeI9UISl8cLhDf7N57Cl1a1K7Zars6cftqLwLEVy77j5?= =?us-ascii?Q?xSNQju/oguItXKRXJTqwQiUA8bz5DkE975bhjMqJAQCxT+IKlGKRvRzLEvli?= =?us-ascii?Q?ODvw3C+jXMznfHt3FTArKbBD3mH7UYOsjr/NWynHZ1Ut2eViYD1vgThGfuIM?= =?us-ascii?Q?cMCnEDWmxHac8l4u8Z3t+xPYzSipm7b/CSLK7gffHsMsiaHdlvQg+lhsY/d5?= =?us-ascii?Q?jeznKxw47fiykvWVebVsnEX0+sc8n2Ws4BI85GIlGEinyAx8Cr0uE+XzWSij?= =?us-ascii?Q?orXiuBFGp604P7AhISqwQK5yQibmyA45WQd6/0CIuqb2CuZhHmEkZUlypp8y?= =?us-ascii?Q?vDwu91NDFEApovX+iwEB2NQbAgwAJ5424Mb3il+uzZ00dKLPTzah/8WaCqHN?= =?us-ascii?Q?QAqdFoOAMEjlONtjA+f9fbc8ewkIO+BMuXQCFM3m5x0fFtgluGwP3WLSJ2FB?= =?us-ascii?Q?wp4mcSph/DhcOtOZu4M5EKWxzOamXTqaXm0sk109UudoyE2a3xCviHpAU0dF?= =?us-ascii?Q?OE/EusV5XXrK9+u7M3R6fMZ7PeEiGbYkqtM/KxmUi6xDHGXpfIccAvvVQ1Mo?= =?us-ascii?Q?BkKYDckm40Ym50Qa7n1ZSz9lZdni+MAqchgKhaXtRYM3bPezruuBfPJ4mZKH?= =?us-ascii?Q?56QOM7D9kdXpJT4DtzpPHsN6MDZgfs3lbsfLjEyKUq7Aq6LAkG+KSsjaxjO9?= =?us-ascii?Q?9L4cX+so6jdrlUjQsKWbqQexEfOK05rQBL5JJOSLTf9uT23dg+XfPR8mHCEN?= =?us-ascii?Q?Auk3RtlDtdQAPaz+7cmelvx6zZrMPnm23brUXmC03cXQN1pIg4u2gf14GtKW?= =?us-ascii?Q?//E/0owKgdD7lpRlocncdfvmcsflzQIbXdLGIYKtGE8Tt5eYiPbDjz3O/bYL?= =?us-ascii?Q?PO785aV5CpeO5VBHS/F0xFdxTAKOnkZsKUuYI5FrX8qzkZGotvzZ7TmFJfaW?= =?us-ascii?Q?2W9LScTGOJvdpORwutNem3optApRalU2qiSYpdLTw8F5xw0VJ/sWFYuyn+G0?= =?us-ascii?Q?VA/IitUG5TfGjAcnceWcGolBruzPQqIYjW6AfmL88rFT+GpfS93Lok+yv4Wv?= =?us-ascii?Q?B13Sraf3YDq4msXQoxLQMrtcVnF/oBdArhcGLSMdFcWEjVncE53zkDyge7sO?= =?us-ascii?Q?ewq8UzLxmINQT5+NcH36r5SziM+MsY/cHq6sjJwRf4RTGqCMrqId8o5FdMXR?= =?us-ascii?Q?2dnOtdCgXEEFzA26auGOaXU2sQ7WxPCv2Zf66UTfni/ZZu5uiqZt0HxKpNuz?= =?us-ascii?Q?QJWba7opuFRk54ssmlBn1G5SHfWpKw7WTcrB1P/mrGRwjfOe98ww0sfcq7RO?= =?us-ascii?Q?3ikRVFH1XjJXIG9WLgBx5lHmB5vqdV7vKsxZQUOe+dYeOGFKv4RcDgsyCCwm?= =?us-ascii?Q?b8SeZ1gWvKedMYWnaFYxbEVGCOaQ7+BQLrTw7RbqCQszq3husxoQHAHtgLRU?= =?us-ascii?Q?5S+ZTnDCV4H10hZ2C/GfCc7Wdp8ACC1VJSubEGl2PtteMBHdrBqo8DJV5cR5?= =?us-ascii?Q?EnKdVI0mRq4ne944oLqeiYAjYxHj7OWNGIpTXRh3QbfDE4bfp7oMO8HhB0VC?= =?us-ascii?Q?SdbGt6gVMsS+OGeWp9M=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:36.9909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fee3961b-c61a-4581-d24b-08de3e73e240 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6390 Content-Type: text/plain; charset="utf-8" An S1 domain that holds the mappings of guest VM's RAM space can be shared across the passthrough devices, as long as the S1 page table is compatible with all the SMMU instances that the devices physically sit behind. On the other hand, ASID is per CD, which is further per STE (i.e. device). Thus, it should be decoupled from a domain structure and ideally stored in the master structure instead. There will be an ASID array stored in the arm_smmu_master structure, so it needs an SSID/PASID to index a specific ASID to program the CD. To prepare for that, pass in an SSID/PASID to arm_smmu_make_s1_cd() from its callers. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 3 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 ++++--- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4f104c1baa67..0a5aead300b6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1070,7 +1070,7 @@ struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_sm= mu_master *master, u32 ssid); void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain); + struct arm_smmu_domain *smmu_domain, ioasid_t ssid); void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, struct arm_smmu_cd *cdptr, const struct arm_smmu_cd *target); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index f1f8e01a7e91..adf802f165d1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -29,7 +29,8 @@ arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_domain= *smmu_domain) if (WARN_ON(!cdptr)) continue; =20 - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, + master_domain->ssid); arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, &target_cd); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 238bfd328b5b..e4bdb4cfdacd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -471,7 +471,7 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd= *cd, unsigned int asid) io_pgtable.cfg.arm_lpae_s1_cfg.tcr.tsz =3D 4; io_pgtable.cfg.arm_lpae_s1_cfg.mair =3D 0xabcdef012345678ULL; =20 - arm_smmu_make_s1_cd(cd, &master, &smmu_domain); + arm_smmu_make_s1_cd(cd, &master, &smmu_domain, IOMMU_NO_PASID); } =20 static void arm_smmu_v3_write_cd_test_s1_clear(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d7c492ee0936..bf0df16cec45 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1613,7 +1613,7 @@ void arm_smmu_write_cd_entry(struct arm_smmu_master *= master, int ssid, =20 void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain) + struct arm_smmu_domain *smmu_domain, ioasid_t ssid) { struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; const struct io_pgtable_cfg *pgtbl_cfg =3D @@ -3636,7 +3636,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, case ARM_SMMU_DOMAIN_S1: { struct arm_smmu_cd target_cd; =20 - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, + IOMMU_NO_PASID); arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, cdptr, &target_cd); arm_smmu_make_cdtable_ste(&target, master, state.ats_enabled, @@ -3679,7 +3680,7 @@ static int arm_smmu_s1_set_dev_pasid(struct iommu_dom= ain *domain, * We can read cd.asid outside the lock because arm_smmu_set_pasid() * will fix it */ - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, id); return arm_smmu_set_pasid(master, to_smmu_domain(domain), id, &target_cd, old); } --=20 2.43.0 From nobody Sat Feb 7 22:07:14 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011020.outbound.protection.outlook.com [52.101.62.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75E4E2BEC45 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:31.4898 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1a18c0b-a9b5-4bc6-2c27-08de3e73def7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8772 Content-Type: text/plain; charset="utf-8" An iotlb tag (ASID/VMID) will not be used: 1) Before being installed to CD/STE during a device attachment 2) After being removed from CD/STE during a device detachment Both (1) and (2) exactly align with the lifecyle of the domain->invs. So, it becomes very nature to use domain->invs to allocate/free an ASID/VMID. Add a pair of function ops in struct arm_smmu_invs, to manage iotlb tag. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 93 +++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 0a5aead300b6..b275673c03ce 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -691,6 +691,9 @@ static inline bool arm_smmu_inv_is_ats(const struct arm= _smmu_inv *inv) * @rwlock: optional rwlock to fench ATS operations * @has_ats: flag if the array contains an INV_TYPE_ATS or INV_TYPE_ATS_FU= LL * @rcu: rcu head for kfree_rcu() + * @smmu_domain: owner domain of the array + * @alloc_id: a callback to allocate a new iotlb tag + * @free_id: a callback to free an iotlb tag when its user counter reaches= 0 * @inv: flexible invalidation array * * The arm_smmu_invs is an RCU data structure. During a ->attach_dev callb= ack, @@ -720,6 +723,9 @@ struct arm_smmu_invs { rwlock_t rwlock; bool has_ats; struct rcu_head rcu; + struct arm_smmu_domain *smmu_domain; + int (*alloc_id)(struct arm_smmu_inv *inv, void *data); + void (*free_id)(struct arm_smmu_inv *inv, bool flush); struct arm_smmu_inv inv[] __counted_by(max_invs); }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index bf0df16cec45..8a2b7064d29b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3117,6 +3117,94 @@ static void arm_smmu_disable_iopf(struct arm_smmu_ma= ster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +/* + * When an array entry's users count reaches zero, it means the ASID/VMID = is no + * longer being invalidated by map/unmap and must be cleaned. The rule is = that + * all ASIDs/VMIDs not in an invalidation array are left cleared in the IO= TLB. + */ +static void arm_smmu_inv_free_asid(struct arm_smmu_inv *inv, bool flush) +{ + lockdep_assert_held(&arm_smmu_asid_lock); + + if (inv->type !=3D INV_TYPE_S1_ASID) + return; + if (refcount_read(&inv->users)) + return; + + if (flush) { + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D inv->nsize_opcode, + .tlbi.asid =3D inv->id, + }; + + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); + } + + /* Lastly, free the ASID as the last user detached */ + xa_erase(&arm_smmu_asid_xa, inv->id); +} + +static void arm_smmu_inv_free_vmid(struct arm_smmu_inv *inv, bool flush) +{ + lockdep_assert_held(&arm_smmu_asid_lock); + + /* Note S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR already */ + if (inv->type !=3D INV_TYPE_S2_VMID) + return; + if (refcount_read(&inv->users)) + return; + + if (flush) { + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D inv->nsize_opcode, + .tlbi.vmid =3D inv->id, + }; + + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); + } + + /* Lastly, free the VMID as the last user detached */ + ida_free(&inv->smmu->vmid_map, inv->id); +} + +static int arm_smmu_inv_alloc_asid(struct arm_smmu_inv *inv, void *data) +{ + struct arm_smmu_domain *smmu_domain =3D data; + struct arm_smmu_device *smmu =3D inv->smmu; + u32 asid; + int ret; + + lockdep_assert_held(&arm_smmu_asid_lock); + + /* Allocate a new iotlb_tag.id */ + WARN_ON(inv->type !=3D INV_TYPE_S1_ASID); + + ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, + XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); + if (ret) + return ret; + inv->id =3D asid; + return 0; +} + +static int arm_smmu_inv_alloc_vmid(struct arm_smmu_inv *inv, void *data) +{ + struct arm_smmu_device *smmu =3D inv->smmu; + int vmid; + + lockdep_assert_held(&arm_smmu_asid_lock); + + WARN_ON(inv->type !=3D INV_TYPE_S2_VMID); + + /* Reserve VMID 0 for stage-2 bypass STEs */ + vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, + GFP_KERNEL); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:33.2927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02bd8fce-b077-4a3d-6aa1-08de3e73e00b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C380.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 Content-Type: text/plain; charset="utf-8" Currently, ASID is allocated per smmu_domain, stored in the domain, and freed with the domain. Practically, ASID is only used in a CD as an iotlb tag. Therefore, ASID doesn't really follow the life cycle of a domain but domain attachment. On the other hand, the CD carrying ASID is installed to a device's STE. This applies to the VMID as well, which is installed in an STE directly. Since a device can only have one ASID per SSID and one VMID per SID, add an ASID array and VMID in the arm_smmu_master structure, to decouple the ASID/VMID from the domain structure. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 +++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 13 ++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++++++++++ 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index b275673c03ce..e21e95936b05 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -953,6 +953,8 @@ struct arm_smmu_master { bool stall_enabled; unsigned int ssid_bits; unsigned int iopf_refcount; + /* Store allocated ASID[1 << ssid_bits] and VMID */ + u16 *asid, vmid; }; =20 /* SMMU private data for an IOMMU domain */ @@ -1117,11 +1119,13 @@ static inline bool arm_smmu_master_canwbs(struct ar= m_smmu_master *master) * @new_invs: for new domain, this is the new invs array to update domain-= >invs; * for old domain, this is the master->build_invs to pass in as= the * to_unref argument to an arm_smmu_invs_unref() call + * @iotlb_tag: copy of the first entry in the build_invs for the domain */ struct arm_smmu_inv_state { struct arm_smmu_invs __rcu **invs_ptr; struct arm_smmu_invs *old_invs; struct arm_smmu_invs *new_invs; + struct arm_smmu_inv iotlb_tag; }; =20 struct arm_smmu_attach_state { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index e4bdb4cfdacd..ead0d84cc9a0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -449,7 +449,8 @@ static void arm_smmu_v3_test_cd_expect_hitless_transiti= on( num_syncs_expected, true); } =20 -static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd *cd, unsigned int = asid) +static void arm_smmu_test_make_s1_cd(struct kunit *test, struct arm_smmu_c= d *cd, + unsigned int asid) { struct arm_smmu_master master =3D { .smmu =3D &smmu, @@ -471,6 +472,10 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_c= d *cd, unsigned int asid) io_pgtable.cfg.arm_lpae_s1_cfg.tcr.tsz =3D 4; io_pgtable.cfg.arm_lpae_s1_cfg.mair =3D 0xabcdef012345678ULL; =20 + master.asid =3D kunit_kzalloc(test, sizeof(*master.asid), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, master.asid); + + master.asid[IOMMU_NO_PASID] =3D asid; arm_smmu_make_s1_cd(cd, &master, &smmu_domain, IOMMU_NO_PASID); } =20 @@ -479,7 +484,7 @@ static void arm_smmu_v3_write_cd_test_s1_clear(struct k= unit *test) struct arm_smmu_cd cd =3D {}; struct arm_smmu_cd cd_2; =20 - arm_smmu_test_make_s1_cd(&cd_2, 1997); + arm_smmu_test_make_s1_cd(test, &cd_2, 1997); arm_smmu_v3_test_cd_expect_non_hitless_transition( test, &cd, &cd_2, NUM_EXPECTED_SYNCS(2)); arm_smmu_v3_test_cd_expect_non_hitless_transition( @@ -491,8 +496,8 @@ static void arm_smmu_v3_write_cd_test_s1_change_asid(st= ruct kunit *test) struct arm_smmu_cd cd =3D {}; struct arm_smmu_cd cd_2; =20 - arm_smmu_test_make_s1_cd(&cd, 778); - arm_smmu_test_make_s1_cd(&cd_2, 1997); + arm_smmu_test_make_s1_cd(test, &cd, 778); + arm_smmu_test_make_s1_cd(test, &cd_2, 1997); arm_smmu_v3_test_cd_expect_hitless_transition(test, &cd, &cd_2, NUM_EXPECTED_SYNCS(1)); arm_smmu_v3_test_cd_expect_hitless_transition(test, &cd_2, &cd, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8a2b7064d29b..1bf7b7233109 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3391,6 +3391,7 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, arm_smmu_invs_merge(invst->old_invs, build_invs); if (IS_ERR(invst->new_invs)) return PTR_ERR(invst->new_invs); + invst->iotlb_tag =3D build_invs->inv[0]; } =20 if (old_smmu_domain) { @@ -3440,6 +3441,11 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_att= ach_state *state) */ smp_mb(); kfree_rcu(invst->old_invs, rcu); + + if (invst->iotlb_tag.type =3D=3D INV_TYPE_S1_ASID) + state->master->asid[state->ssid] =3D invst->iotlb_tag.id; + else + state->master->vmid =3D invst->iotlb_tag.id; } =20 /* @@ -3471,8 +3477,11 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_= smmu_inv *inv) static void arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) { + struct arm_smmu_inv *new_iotlb_tag =3D &state->new_domain_invst.iotlb_tag; + struct arm_smmu_inv *old_iotlb_tag =3D &state->old_domain_invst.iotlb_tag; struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; struct arm_smmu_invs *old_invs =3D invst->old_invs; + struct arm_smmu_master *master =3D state->master; struct arm_smmu_invs *new_invs; =20 lockdep_assert_held(&arm_smmu_asid_lock); @@ -3482,6 +3491,7 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_atta= ch_state *state) =20 arm_smmu_invs_unref(old_invs, invst->new_invs, arm_smmu_inv_flush_iotlb_tag); + *old_iotlb_tag =3D invst->new_invs->inv[0]; =20 new_invs =3D arm_smmu_invs_purge(old_invs); if (!new_invs) @@ -3506,6 +3516,14 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_att= ach_state *state) */ smp_mb(); kfree_rcu(old_invs, rcu); + + /* Make sure we don't clear the stored new iotlb tag */ + if (!new_iotlb_tag->id) { + if (old_iotlb_tag->type =3D=3D INV_TYPE_S1_ASID) + cmpxchg(&master->asid[state->ssid], old_iotlb_tag->id, 0); + else + cmpxchg(&master->vmid, old_iotlb_tag->id, 0); + } } =20 /* @@ -4286,6 +4304,13 @@ static struct iommu_device *arm_smmu_probe_device(st= ruct device *dev) master->ssid_bits =3D min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); =20 + master->asid =3D kcalloc(1 << master->ssid_bits, sizeof(*master->asid), + GFP_KERNEL); + if (!master->asid) { + ret =3D -ENOMEM; + goto err_disable_pasid; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:40.8210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ba6ff14-5769-4cde-3500-08de3e73e489 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6886 Content-Type: text/plain; charset="utf-8" If a domain->invs has an iotlb tag (ASID/VMID) for an SMMU, all the devices behind the SMMU can reuse the same iotlb tag. This exactly matches with the existing case where attaching multiple devices to the same SMMU domain has a shared iotlb tag stored in the domain (cd->asid or s2_cfg->vmid). If a domain->invs doesn't have an iotlb tag for another SMMU, there can be two cases: 1) This is a new domain so not yet attached to any devices 2) This is a shareable domain that is attached to a device behind one SMMU but not yet to the other SMMU. In either case, a new iotlb tag is required. Call the ->alloc_id op in the arm_smmu_invs_merge(). The domain->invs arrary will keep it. The allocated new iotlb tag will be returned to the caller via to_merge arrary. Relax the arm_smmu_inv_cmp(), to allow sharing an iotlb tag across devices behind the same SMMU instance. Similarly, call the ->free_id op in the arm_smmu_invs_unref() when there's no device using it any more. Lastly, add a free helper for the revert path of arm_smmu_attach_prepare() to use. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 70 +++++++++++++++++++-- 2 files changed, 69 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index e21e95936b05..230ab902a9b6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -680,6 +680,9 @@ static inline bool arm_smmu_inv_is_ats(const struct arm= _smmu_inv *inv) return inv->type =3D=3D INV_TYPE_ATS || inv->type =3D=3D INV_TYPE_ATS_FUL= L; } =20 +/* S1_ASID/S2_VMID(S1_CLEAR) types */ +#define arm_smmu_inv_is_iotlb_tag(inv) !arm_smmu_inv_is_ats(inv) + /** * struct arm_smmu_invs - Per-domain invalidation array * @max_invs: maximum capacity of the flexible array diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1bf7b7233109..ec370e54b1bc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1051,6 +1051,9 @@ static int arm_smmu_inv_cmp(const struct arm_smmu_inv= *inv_l, return cmp_int((uintptr_t)inv_l->smmu, (uintptr_t)inv_r->smmu); if (inv_l->type !=3D inv_r->type) return cmp_int(inv_l->type, inv_r->type); + /* Each SMMU shares a single iotlb tag on a domain, so it is a match */ + if (arm_smmu_inv_is_iotlb_tag(inv_l)) + return 0; return cmp_int(inv_l->id, inv_r->id); } =20 @@ -1127,9 +1130,52 @@ struct arm_smmu_invs *arm_smmu_invs_merge(struct arm= _smmu_invs *invs, size_t i, j; int cmp; =20 - arm_smmu_invs_for_each_cmp(invs, i, to_merge, j, cmp) + arm_smmu_invs_for_each_cmp(invs, i, to_merge, j, cmp) { + struct arm_smmu_inv *cur =3D &to_merge->inv[j]; + num_invs++; =20 + if (!arm_smmu_inv_is_iotlb_tag(cur)) + continue; + + /* A matching iotlb tag owned by the same SMMU can be shared */ + if (cmp =3D=3D 0) { + *cur =3D invs->inv[i]; + continue; + } + + /* Iterate the base invs array to find if next is a match */ + if (cmp < 0 && i < invs->num_invs) + continue; + + /* + * Currently the @to_merge array always carries an id (> 0) that + * is also installed in the CD/STE. So, we cannot allocate a new + * ID at this moment, because that would misalign with what's in + * the CD/STE. To not break the existing flow, bypass the new ID + * allocating code. We will lift this bypass line once rework is + * done. + */ + if (cur->id) + continue; + + /* No found. Allocate a new one */ + if (j =3D=3D 0) { + /* KUNIT test doesn't pass in an alloc_id function */ + if (to_merge->alloc_id) { + int ret; + + ret =3D to_merge->alloc_id(cur, + invs->smmu_domain); + if (ret) + return ERR_PTR(ret); + } + } else { + /* Copy the allocated iotlb tag from the previous inv */ + cur->id =3D cur[-1].id; + } + } + new_invs =3D arm_smmu_invs_alloc(num_invs); if (!new_invs) return ERR_PTR(-ENOMEM); @@ -1207,9 +1253,9 @@ void arm_smmu_invs_unref(struct arm_smmu_invs *invs, continue; } =20 - /* KUNIT test doesn't pass in a free_fn */ - if (free_fn) - free_fn(&invs->inv[i]); + /* KUNIT test doesn't pass in a free_id function */ + if (to_unref->free_id) + to_unref->free_id(&invs->inv[i], true); invs->num_trashes++; } else { /* item in to_unref is not in invs or already a trash */ @@ -3167,6 +3213,21 @@ static void arm_smmu_inv_free_vmid(struct arm_smmu_i= nv *inv, bool flush) ida_free(&inv->smmu->vmid_map, inv->id); } =20 +static void arm_smmu_inv_free_iotlb_tag(struct arm_smmu_inv *inv) +{ + switch (inv->type) { + case INV_TYPE_S1_ASID: + arm_smmu_inv_free_asid(inv, false); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:42.3128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 250f2417-5ff6-4bcd-5d45-08de3e73e568 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9326 Content-Type: text/plain; charset="utf-8" Now the iotlb tag (ASID/VMID) allocated in arm_smmu_invs_merge() is stored in the master, with a proper release and revert pathways. Replace the old smmu_domain->cd.asid and smmu_domain->s2_cfg.vmid with the master ones. The old asid/vmid will be depracated. Note that the nested pathway needs vsmmu->vmid to be updated to align with the VMID programmed in the STE as its invalidation code will overwrite the VMID field using vsmmu->vmid. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 15 +++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 4 ++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++------ 4 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 230ab902a9b6..dac412ff0d71 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1186,6 +1186,7 @@ struct arm_vsmmu { struct iommufd_viommu core; struct arm_smmu_device *smmu; struct arm_smmu_domain *s2_parent; + int nr_vmasters; u16 vmid; }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 93fdadd07431..1c877d30f86e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -136,6 +136,19 @@ void arm_smmu_attach_commit_vmaster(struct arm_smmu_at= tach_state *state) struct arm_smmu_master *master =3D state->master; =20 mutex_lock(&master->smmu->streams_mutex); + + /* Clear the old vsmmu's VMID and set the new vsmmu's VMID */ + if (master->vmaster && master->vmaster->vsmmu) { + if (--master->vmaster->vsmmu->nr_vmasters =3D=3D 0) + master->vmaster->vsmmu->vmid =3D 0; + WARN_ON(master->vmaster->vsmmu->nr_vmasters < 0); + } + if (state->vmaster && state->vmaster->vsmmu) { + cmpxchg(&state->vmaster->vsmmu->vmid, 0, master->vmid); + WARN_ON(state->vmaster->vsmmu->vmid !=3D master->vmid); + state->vmaster->vsmmu->nr_vmasters++; + } + kfree(master->vmaster); master->vmaster =3D state->vmaster; mutex_unlock(&master->smmu->streams_mutex); @@ -454,8 +467,6 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, =20 vsmmu->smmu =3D smmu; vsmmu->s2_parent =3D s2_parent; - /* FIXME Move VMID allocation from the S2 domain allocation to here */ - vsmmu->vmid =3D s2_parent->s2_cfg.vmid; =20 if (viommu->type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) { viommu->ops =3D &arm_vsmmu_ops; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index adf802f165d1..0e534f2b72e0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -164,7 +164,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) if (WARN_ON(!cdptr)) continue; arm_smmu_make_sva_cd(&target, master, NULL, - smmu_domain->cd.asid); + master->asid[master_domain->ssid]); arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, &target); } @@ -266,7 +266,7 @@ static int arm_smmu_sva_set_dev_pasid(struct iommu_doma= in *domain, * This does not need the arm_smmu_asid_lock because SVA domains never * get reassigned */ - arm_smmu_make_sva_cd(&target, master, domain->mm, smmu_domain->cd.asid); + arm_smmu_make_sva_cd(&target, master, domain->mm, master->asid[id]); ret =3D arm_smmu_set_pasid(master, smmu_domain, id, &target, old); =20 mmput(domain->mm); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ec370e54b1bc..d6ae630d0de3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1661,7 +1661,6 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t ssid) { - struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D @@ -1686,7 +1685,7 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET | - FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) + FIELD_PREP(CTXDESC_CD_0_ASID, master->asid[ssid]) ); =20 /* To enable dirty flag update, set both Access flag and dirty state upda= te */ @@ -1945,7 +1944,6 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, struct arm_smmu_domain *smmu_domain, bool ats_enabled) { - struct arm_smmu_s2_cfg *s2_cfg =3D &smmu_domain->s2_cfg; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =3D @@ -1976,7 +1974,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] =3D cpu_to_le64( - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | + FIELD_PREP(STRTAB_STE_2_S2VMID, master->vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN @@ -3850,7 +3848,7 @@ static int arm_smmu_s1_set_dev_pasid(struct iommu_dom= ain *domain, return -EINVAL; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:42.9673 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09942766-8783-4cc2-cec7-08de3e73e5d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7324 Content-Type: text/plain; charset="utf-8" The arm_smmu_inv_cmp() function no longer enforces ASID/VMID values on an iotlb tag entry, to allow sharing an existing tag in the domain->invs. If no tag is found on the same SMMU, a new tag will be allocated. Therefore, there is no point in passing in any id to the iotlb entries in the master->build_invs array. Use a dummy ID=3D0 that is out of range of an ID allocation, so as to set free cd->asid and s2_cfg->vmid. An ATS entry must still have a specific ID. Since CD/STE has the ASID/VMID coming from the master structure, lift the cur->id check in arm_smmu_invs_merge(), to use the new ID allocation path. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 29 ++++++++------------- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d6ae630d0de3..d51bad1002ff 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1148,17 +1148,6 @@ struct arm_smmu_invs *arm_smmu_invs_merge(struct arm= _smmu_invs *invs, if (cmp < 0 && i < invs->num_invs) continue; =20 - /* - * Currently the @to_merge array always carries an id (> 0) that - * is also installed in the CD/STE. So, we cannot allocate a new - * ID at this moment, because that would misalign with what's in - * the CD/STE. To not break the existing flow, bypass the new ID - * allocating code. We will lift this bypass line once rework is - * done. - */ - if (cur->id) - continue; - /* No found. Allocate a new one */ if (j =3D=3D 0) { /* KUNIT test doesn't pass in an alloc_id function */ @@ -3331,11 +3320,16 @@ arm_smmu_master_build_invs(struct arm_smmu_master *= master, bool ats_enabled, if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); =20 + /* + * Each SMMU has only one iotlb tag in the array, so leave the iotlb tag + * ID to be 0. The merge() and unref() will find the existing one in the + * array to refcount_inc/dec. In case of missing a match, merge() should + * allocate a new ID while unref() should WARN_ON. + */ switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_SVA: case ARM_SMMU_DOMAIN_S1: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, - smmu_domain->cd.asid, + if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, 0, IOMMU_NO_PASID, pgsize)) return NULL; master->build_invs->alloc_id =3D arm_smmu_inv_alloc_asid; @@ -3343,8 +3337,7 @@ arm_smmu_master_build_invs(struct arm_smmu_master *ma= ster, bool ats_enabled, master->build_invs->smmu_domain =3D smmu_domain; break; case ARM_SMMU_DOMAIN_S2: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, - smmu_domain->s2_cfg.vmid, + if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, 0, IOMMU_NO_PASID, pgsize)) return NULL; master->build_invs->alloc_id =3D arm_smmu_inv_alloc_vmid; @@ -3357,9 +3350,9 @@ arm_smmu_master_build_invs(struct arm_smmu_master *ma= ster, bool ats_enabled, =20 /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ if (nesting) { - if (!arm_smmu_master_build_inv( - master, INV_TYPE_S2_VMID_S1_CLEAR, - smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + if (!arm_smmu_master_build_inv(master, + INV_TYPE_S2_VMID_S1_CLEAR, 0, + IOMMU_NO_PASID, 0)) return NULL; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:46.5736 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abab165b-7680-47a8-61ae-08de3e73e7f7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9650 Content-Type: text/plain; charset="utf-8" This is dead code now. Remove it. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 6 ++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 34 ++----------------- 3 files changed, 6 insertions(+), 37 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index dac412ff0d71..e38d2394e3be 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1035,8 +1035,7 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, struct arm_smmu_invs *arm_smmu_invs_merge(struct arm_smmu_invs *invs, struct arm_smmu_invs *to_merge); void arm_smmu_invs_unref(struct arm_smmu_invs *invs, - struct arm_smmu_invs *to_unref, - void (*free_fn)(struct arm_smmu_inv *inv)); + struct arm_smmu_invs *to_unref); struct arm_smmu_invs *arm_smmu_invs_purge(struct arm_smmu_invs *invs); #endif =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index ead0d84cc9a0..5c8cb43f849c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -632,7 +632,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) results2[0], results2[1]); =20 /* Test3: unref invs2 (same array) */ - arm_smmu_invs_unref(test_a, &invs2, NULL); + arm_smmu_invs_unref(test_a, &invs2); arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results3[0]), results3[0], results3[1]); KUNIT_EXPECT_EQ(test, test_a->num_trashes, 0); @@ -644,7 +644,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) results4[0], results4[1]); =20 /* Test5: unref invs1 (same array) */ - arm_smmu_invs_unref(test_b, &invs1, NULL); + arm_smmu_invs_unref(test_b, &invs1); arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results5[0]), results5[0], results5[1]); KUNIT_EXPECT_EQ(test, test_b->num_trashes, 2); @@ -656,7 +656,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) results6[0], results6[1]); =20 /* Test7: unref invs3 (same array) */ - arm_smmu_invs_unref(test_a, &invs3, NULL); + arm_smmu_invs_unref(test_a, &invs3); KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); KUNIT_EXPECT_EQ(test, test_a->num_trashes, 0); =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d51bad1002ff..5052988b0e4e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1203,9 +1203,6 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge); * the user counts without deletions * @invs: the base invalidation array * @to_unref: an array of invlidations to decrease their user counts - * @free_fn: A callback function to invoke, when an entry's user count red= uces - * to 0 - * * Return: the number of trash entries in the array, for arm_smmu_invs_pur= ge() * * This function will not fail. Any entry with users=3D0 will be marked as= trash. @@ -1223,8 +1220,7 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge); */ VISIBLE_IF_KUNIT void arm_smmu_invs_unref(struct arm_smmu_invs *invs, - struct arm_smmu_invs *to_unref, - void (*free_fn)(struct arm_smmu_inv *inv)) + struct arm_smmu_invs *to_unref) { unsigned long flags; size_t num_invs =3D 0; @@ -3500,31 +3496,6 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_att= ach_state *state) state->master->vmid =3D invst->iotlb_tag.id; } =20 -/* - * When an array entry's users count reaches zero, it means the ASID/VMID = is no - * longer being invalidated by map/unmap and must be cleaned. The rule is = that - * all ASIDs/VMIDs not in an invalidation array are left cleared in the IO= TLB. - */ -static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv) -{ - struct arm_smmu_cmdq_ent cmd =3D {}; - - switch (inv->type) { - case INV_TYPE_S1_ASID: - cmd.tlbi.asid =3D inv->id; - break; - case INV_TYPE_S2_VMID: - /* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */ - cmd.tlbi.vmid =3D inv->id; - break; - default: - return; - } - - cmd.opcode =3D inv->nsize_opcode; - arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); -} - /* Should be installed after arm_smmu_install_ste_for_dev() */ static void arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) @@ -3541,8 +3512,7 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_atta= ch_state *state) if (!invst->invs_ptr) return; =20 - arm_smmu_invs_unref(old_invs, invst->new_invs, - arm_smmu_inv_flush_iotlb_tag); + arm_smmu_invs_unref(old_invs, invst->new_invs); *old_iotlb_tag =3D invst->new_invs->inv[0]; =20 new_invs =3D arm_smmu_invs_purge(old_invs); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:37.4102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7f08ce6-cb38-417c-d229-08de3e73e283 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7119 Content-Type: text/plain; charset="utf-8" Now ASID/VMID are stored in the arm_smmu_master. These are dead code now. Remove all. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 20 +------ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 3 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 58 ------------------- 4 files changed, 1 insertion(+), 88 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index e38d2394e3be..4d7b7eb52dfd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -792,10 +792,6 @@ static inline bool arm_smmu_ssids_in_use(struct arm_sm= mu_ctx_desc_cfg *cd_table) return cd_table->used_ssids; } =20 -struct arm_smmu_s2_cfg { - u16 vmid; -}; - struct arm_smmu_strtab_cfg { union { struct { @@ -974,10 +970,6 @@ struct arm_smmu_domain { atomic_t nr_ats_masters; =20 enum arm_smmu_domain_stage stage; - union { - struct arm_smmu_ctx_desc cd; - struct arm_smmu_s2_cfg s2_cfg; - }; =20 struct iommu_domain domain; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 0e534f2b72e0..ea5ce3e6514e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -282,14 +282,6 @@ static void arm_smmu_sva_domain_free(struct iommu_doma= in *domain) */ arm_smmu_domain_inv(smmu_domain); =20 - /* - * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can - * still be called/running at this point. We allow the ASID to be - * reused, and if there is a race then it just suffers harmless - * unnecessary invalidation. - */ - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); - /* * Actual free is defered to the SRCU callback * arm_smmu_mmu_notifier_free() @@ -308,7 +300,6 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_domain *smmu_domain; - u32 asid; int ret; =20 if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) @@ -327,22 +318,13 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct= device *dev, smmu_domain->domain.pgsize_bitmap =3D PAGE_SIZE; smmu_domain->stage =3D ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu =3D smmu; - - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - if (ret) - goto err_free; - - smmu_domain->cd.asid =3D asid; smmu_domain->mmu_notifier.ops =3D &arm_smmu_mmu_notifier_ops; ret =3D mmu_notifier_register(&smmu_domain->mmu_notifier, mm); if (ret) - goto err_asid; + goto err_free; =20 return &smmu_domain->domain; =20 -err_asid: - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); err_free: arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 5c8cb43f849c..b174ac2dfb4b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -458,9 +458,6 @@ static void arm_smmu_test_make_s1_cd(struct kunit *test= , struct arm_smmu_cd *cd, struct io_pgtable io_pgtable =3D {}; struct arm_smmu_domain smmu_domain =3D { .pgtbl_ops =3D &io_pgtable.ops, - .cd =3D { - .asid =3D asid, - }, }; =20 io_pgtable.cfg.arm_lpae_s1_cfg.ttbr =3D 0xdaedbeefdeadbeefULL; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5052988b0e4e..04e21af9c578 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2812,66 +2812,17 @@ struct arm_smmu_domain *arm_smmu_domain_alloc(void) static void arm_smmu_domain_free_paging(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct arm_smmu_device *smmu =3D smmu_domain->smmu; =20 free_io_pgtable_ops(smmu_domain->pgtbl_ops); - - /* Free the ASID or VMID */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - /* Prevent SVA from touching the CD while we're freeing it */ - mutex_lock(&arm_smmu_asid_lock); - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); - mutex_unlock(&arm_smmu_asid_lock); - } else { - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - if (cfg->vmid) - ida_free(&smmu->vmid_map, cfg->vmid); - } - arm_smmu_domain_free(smmu_domain); } =20 -static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain) -{ - int ret; - u32 asid =3D 0; - struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; - - /* Prevent SVA from modifying the ASID until it is written to the CD */ - mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - cd->asid =3D (u16)asid; - mutex_unlock(&arm_smmu_asid_lock); - return ret; -} - -static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain) -{ - int vmid; - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - - /* Reserve VMID 0 for stage-2 bypass STEs */ - vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, - GFP_KERNEL); - if (vmid < 0) - return vmid; - - cfg->vmid =3D (u16)vmid; - return 0; -} - static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, u32 flags) { - int ret; enum io_pgtable_fmt fmt; struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; - int (*finalise_stage_fn)(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain); bool enable_dirty =3D flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; =20 pgtbl_cfg =3D (struct io_pgtable_cfg) { @@ -2891,7 +2842,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_d= omain *smmu_domain, if (enable_dirty) pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_HD; fmt =3D ARM_64_LPAE_S1; - finalise_stage_fn =3D arm_smmu_domain_finalise_s1; break; } case ARM_SMMU_DOMAIN_S2: @@ -2900,7 +2850,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_d= omain *smmu_domain, pgtbl_cfg.ias =3D smmu->ias; pgtbl_cfg.oas =3D smmu->oas; fmt =3D ARM_64_LPAE_S2; - finalise_stage_fn =3D arm_smmu_domain_finalise_s2; if ((smmu->features & ARM_SMMU_FEAT_S2FWB) && (flags & IOMMU_HWPT_ALLOC_NEST_PARENT)) pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_S2FWB; @@ -2918,13 +2867,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_= domain *smmu_domain, smmu_domain->domain.geometry.force_aperture =3D true; if (enable_dirty && smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) smmu_domain->domain.dirty_ops =3D &arm_smmu_dirty_ops; - - ret =3D finalise_stage_fn(smmu, smmu_domain); - if (ret < 0) { - free_io_pgtable_ops(pgtbl_ops); - return ret; - } - smmu_domain->pgtbl_ops =3D pgtbl_ops; smmu_domain->smmu =3D smmu; return 0; --=20 2.43.0 From nobody Sat Feb 7 22:07:14 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011017.outbound.protection.outlook.com [40.107.208.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69F3F2DC35C for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:48.3125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa150a49-4be6-4e0c-490a-08de3e73e8fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7858 Content-Type: text/plain; charset="utf-8" VMM needs a domain holding the mappings between gPA to hPA. It can be an S1 domain or an S2 nesting parent domain, depending on whether the VM is built with a vSMMU or not. Given that the IOAS for this gPA mapping is the same across SMMU instances, this domain can be shared across devices even if they sit behind different SMMUs, so long as the underlying page table is compatible between the SMMU instances. There is no direct information about the page table from the master device, but a comparison can be done between the physical SMMU that the domain was allocated for and the physical SMMU that the device is behind. Replace the smmu test in arm_smmu_attach_dev() and arm_vsmmu_init() with a compatibility test for the S1 and S2 cases respectively. The compatibility test goes through the physical SMMU parameters that were used to decide the page table formats. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 20 +++++++++++++++++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4d7b7eb52dfd..d64e4e7c162d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -992,6 +992,26 @@ struct arm_smmu_nested_domain { __le64 ste[2]; }; =20 +static inline bool +arm_smmu_domain_can_share(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *new_smmu) +{ + struct arm_smmu_device *base_smmu =3D smmu_domain->smmu; + + if (base_smmu =3D=3D new_smmu) + return true; + /* Only support identical SMMUs for now */ + if (base_smmu->features !=3D new_smmu->features) + return false; + if (base_smmu->iommu.ops !=3D new_smmu->iommu.ops) + return false; + if (base_smmu->pgsize_bitmap !=3D new_smmu->pgsize_bitmap) + return false; + if (base_smmu->ias > new_smmu->ias || base_smmu->oas > new_smmu->oas) + return false; + return true; +} + /* The following are exposed for testing purposes. */ struct arm_smmu_entry_writer_ops; struct arm_smmu_entry_writer { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 1c877d30f86e..f2318e31d875 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -462,7 +462,7 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, container_of(viommu->iommu_dev, struct arm_smmu_device, iommu); struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent_domain); =20 - if (s2_parent->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(s2_parent, smmu)) return -EINVAL; =20 vsmmu->smmu =3D smmu; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 04e21af9c578..ab329614da1f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3684,7 +3684,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, state.master =3D master =3D dev_iommu_priv_get(dev); smmu =3D master->smmu; =20 - if (smmu_domain->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(smmu_domain, smmu)) return -EINVAL; =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { --=20 2.43.0