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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linaro-s32@linaro.org Subject: [PATCH v2 1/4] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the s32 chipsets the GMAC_0_CTRL_STS register is in GPR region. Originally, accessing this register was done in a sort of ad-hoc way, but we want to use the syscon interface to do it. This is a little bit ugly because we have to maintain backwards compatibility to the old device trees so we have to support both ways to access this register. Signed-off-by: Dan Carpenter --- Fix forward porting bug. s/PHY_INTF_SEL_RGMII/S32_PHY_INTF_SEL_RGMII/ .../net/ethernet/stmicro/stmmac/dwmac-s32.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index 5a485ee98fa7..2e6bb41f49e1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include =20 #include "stmmac_platform.h" @@ -32,6 +34,8 @@ struct s32_priv_data { void __iomem *ioaddr; void __iomem *ctrl_sts; + struct regmap *sts_regmap; + unsigned int sts_offset; struct device *dev; phy_interface_t *intf_mode; struct clk *tx_clk; @@ -40,7 +44,10 @@ struct s32_priv_data { =20 static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) { - writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + if (gmac->ctrl_sts) + writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + else + regmap_write(gmac->sts_regmap, gmac->sts_offset, S32_PHY_INTF_SEL_RGMII); =20 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); =20 @@ -125,10 +132,16 @@ static int s32_dwmac_probe(struct platform_device *pd= ev) "dt configuration failed\n"); =20 /* PHY interface mode control reg */ - gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(gmac->ctrl_sts)) - return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), - "S32CC config region is missing\n"); + gmac->sts_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "nxp,phy-sel", 1, &gmac->sts_offset); + if (gmac->sts_regmap =3D=3D ERR_PTR(-EPROBE_DEFER)) + return PTR_ERR(gmac->sts_regmap); + if (IS_ERR(gmac->sts_regmap)) { + gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(gmac->ctrl_sts)) + return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), + "S32CC config region is missing\n"); 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Mon, 15 Dec 2025 06:41:56 -0800 (PST) Date: Mon, 15 Dec 2025 17:41:52 +0300 From: Dan Carpenter To: Lee Jones Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linaro-s32@linaro.org, NXP S32 Linux Team Subject: [PATCH v2 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs Message-ID: <792d3f59b9f519529b94e673faf70d77c4b61fb3.1765806521.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NXP S32 SoCs have a GPR region which is used by a variety of drivers. Some examples of the registers in this region are: * DDR_PMU_IRQ * GMAC0_PHY_INTF_SEL * GMAC1_PHY_INTF_SEL * PFE_EMACS_INTF_SEL * PFE_COH_EN * PFE_PWR_CTRL * PFE_EMACS_GENCTRL1 * PFE_GENCTRL3 Use the syscon interface to access these registers. Signed-off-by: Dan Carpenter --- v2: Use nxp,s32g2-gpr and nxp,s32g3-gpr instead of nxp,s32g-gpr Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 55efb83b1495..694733aeb270 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -102,6 +102,8 @@ select: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32g2-gpr + - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos @@ -212,6 +214,8 @@ properties: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32g2-gpr + - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos --=20 2.51.0 From nobody Mon Dec 15 23:31:48 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33A5E30BB85 for ; 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Mon, 15 Dec 2025 06:42:01 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fb7118267sm22168335f8f.27.2025.12.15.06.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 06:42:00 -0800 (PST) Date: Mon, 15 Dec 2025 17:41:57 +0300 From: Dan Carpenter To: Jan Petrous Cc: s32@nxp.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linaro-s32@linaro.org Subject: [PATCH v2 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Message-ID: <1ecafee4bd7dc3577adfc4ada8bcc50b5eb3e863.1765806521.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The S32 chipsets have a GPR region which has a miscellaneous registers including the GMAC_0_CTRL_STS register. Originally, this code accessed that register in a sort of ad-hoc way, but it's cleaner to use a syscon interface to access these registers. We still need to maintain the old method of accessing the GMAC register but using a syscon will let us access other registers more cleanly. Signed-off-by: Dan Carpenter --- v2: Add the vendor prefix to the phandle Fix the documentation .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..a65036806d60 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -32,6 +32,15 @@ properties: - description: Main GMAC registers - description: GMAC PHY mode control register =20 + nxp,phy-sel: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to the GPR syscon node + - description: offset of PHY selection register + description: + This is a phandle/offset pair. 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charset="utf-8" Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter --- v2: Remove #address-cells and #size-cells arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..b954952d962b 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,11 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32g2-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -731,6 +736,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index eff7673e7f34..71ee1c043d03 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,11 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32g3-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -808,6 +813,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0