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Tue, 9 Dec 2025 18:45:49 -0800 From: Nicolin Chen To: , , CC: , , , , , , Subject: [PATCH rc v3 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence Date: Tue, 9 Dec 2025 18:45:16 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B372:EE_|PH8PR12MB7350:EE_ X-MS-Office365-Filtering-Correlation-Id: 41280fd2-e22d-4eeb-f701-08de37963fad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?G8JFk6n9RZTuWe9kI9N18LwPL5/UhCR0lqnqfXRzZ56GbHfXmIZKtT6rvKG5?= =?us-ascii?Q?QQFuYaZ9VRyl1KkOEloFHz3urODPRu9HVOk5Q8yEwayglvIsFG1kG69Rm8ih?= =?us-ascii?Q?188wFcRu+dnOLcdtiRWsMy60slflEtHHpUkFEKGOMzPPAsQsjC3rDpLVWwXL?= =?us-ascii?Q?rMFu74D04SUJWXvzSXWPGZBttHmT9JyzvCAaEpR3wPQWFjvUfy9poQn71EhE?= =?us-ascii?Q?6xKFWkMUE1K2z+GsBQNK8wlJKDf4syhJhk3Duv7GmqcUfcet151PXgXn7Ej1?= =?us-ascii?Q?8ZhPRtmhgMg/mg8pUSt6cm6n+Co7TQL28fw4vmwKTFhfhY1aZ7bM6Q02ymdH?= =?us-ascii?Q?mJDw+bxgaoPdf3nonfZS1RBIrlBnEUomBScDCN73Ox3Sw2E7d72ysF2kh58y?= =?us-ascii?Q?cuZ9utdJPFqXHT7XPPRVSx0NvSZhvjc3N6LSCsfbk25566v/UfCv/hFOMb6T?= =?us-ascii?Q?LVrf8gTQCZ+AnaugVNfEm5i042jCXyxfBLWbNjOjlFg0xqO1qo9gOgZbGkWs?= =?us-ascii?Q?JaRzwbDkUQnVsWhinp+yiQs12CfW4K+fC9uwWfnk0i1OJNxuFtl+6K7/T6Zy?= =?us-ascii?Q?6i61Ze2UzNGgFB7nnpefz5CBJlpu3HJ71aq9OyIXOv8yUFiU2XYC1b4rPbCN?= =?us-ascii?Q?5j7b/0QJIFYYari0A4IOMii1bL5IKFaY1Z9GK29uvby2uKko8yFNxn8XELRI?= =?us-ascii?Q?Qzh5KPErAGHhOyi3RmBOgXp5WNR+HLJhklt6IVXfje+8GWHTv12IDctO5oV+?= =?us-ascii?Q?Jmd/LPcjQDRDttFqszsl5fw6044MGwh70pnn8CxBLfnNsgJYbfTOvV5/lrZK?= =?us-ascii?Q?K1HgFZYI95QJLAaFFCkCPCFOWmI7G4fxx3wCJJAtslATjlVgQwU0uAEqq62I?= =?us-ascii?Q?cDlzrtTOKVgzvS7Dc1UeNQXW+RO98q+DWIU59KTsih7M7qY9BqvpjFPkOBPV?= =?us-ascii?Q?XdV068iya3SZHJN7khWV25z2ky5Wv4fgvmIz5jt3dOIf/flVv7P2mqhyGCQf?= =?us-ascii?Q?CXcDVdCm1RNPAiBHNCLehFtc9+wCTSJOv9epiFAH3GbwevgF8nTuGMkqvgIl?= =?us-ascii?Q?1zyOmC3Hpxel+r2FF7THyKeHV4ji2HUbt0Cs5u/3I0g4amP7hSoGfAu6wmBc?= =?us-ascii?Q?ISokFH2yuc0VU3DH9UsiCPbtc3ek+ZoSG48Fi6zYGI4/g40zql9THlGw+DL/?= =?us-ascii?Q?dUMSpBTGsMwN5FTuP/W37MeDLvp3ilZwpyHX5rj9JWdTqdaFNQNvF1WUUEC7?= =?us-ascii?Q?xh6sQJS5WFj01ZNuxVvMbnfpt46ZT6vziowNKWiQUBxLEJI/nTJwOboH9tKP?= =?us-ascii?Q?s6rlmlLHLuLRrUCho2Zbc+E62jq+PCegn6dgHE8Wa7OYP73Njw5Lt2iWI8Ms?= =?us-ascii?Q?opMuivoyrt/ZUY7CgKHoxJ5Y9hCpkVrHiMm1iczhb7rvFoZdyHscWfNRfZE7?= =?us-ascii?Q?5KKAR/jhTNmuvugvCKdWY4t9pfRRK3gaWLi6z3EEc9WQnf/3L/e5abZ9Amiz?= =?us-ascii?Q?S17xUyRVK5BYT+DdApAPCOruHSSqvUVV7RUX3G4QxDX5EVoNE3hzej7RSiJ8?= =?us-ascii?Q?26aGDXM2bw+hL2doH1w=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 02:45:58.4413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41280fd2-e22d-4eeb-f701-08de37963fad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B372.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7350 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe C_BAD_STE was observed when updating nested STE from an S1-bypass mode to an S1DSS-bypass mode. As both modes enabled S2, the used bit is slightly different than the normal S1-bypass and S1DSS-bypass modes. As a result, fields like MEV and EATS in S2's used list marked the word1 as a critical word that requested a STE.V=3D0. This breaks a hitless update. However, both MEV and EATS aren't critical in terms of STE update. One controls the merge of the events and the other controls the ATS that is managed by the driver at the same time via pci_enable_ats(). Add an arm_smmu_get_ste_ignored() to allow STE update algorithm to ignore those fields, avoiding the STE update breakages. Note that this change is required by both MEV and EATS fields, which were introduced in different kernel versions. So add this get_ignored() first. The MEV and EATS will be added in arm_smmu_get_ste_ignored() separately. Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 19 ++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24 +++++++++++++++---- 3 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ae23aacc3840..d5f0e5407b9f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -900,6 +900,7 @@ struct arm_smmu_entry_writer { =20 struct arm_smmu_entry_writer_ops { void (*get_used)(const __le64 *entry, __le64 *used); + void (*get_ignored)(__le64 *ignored_bits); void (*sync)(struct arm_smmu_entry_writer *writer); }; =20 @@ -911,6 +912,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *t= arget, =20 #if IS_ENABLED(CONFIG_KUNIT) void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); +void arm_smmu_get_ste_ignored(__le64 *ignored_bits); void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *cu= r, const __le64 *target); void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd3798..3556e65cf9ac 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -38,13 +38,16 @@ enum arm_smmu_test_master_feat { static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, + const __le64 *ignored, unsigned int length) { bool differs =3D false; unsigned int i; =20 for (i =3D 0; i < length; i++) { - if ((entry[i] & used_bits[i]) !=3D target[i]) + __le64 used =3D used_bits[i] & ~ignored[i]; + + if ((entry[i] & used) !=3D (target[i] & used)) differs =3D true; } return differs; @@ -56,12 +59,18 @@ arm_smmu_test_writer_record_syncs(struct arm_smmu_entry= _writer *writer) struct arm_smmu_test_writer *test_writer =3D container_of(writer, struct arm_smmu_test_writer, writer); __le64 *entry_used_bits; + __le64 *ignored; =20 entry_used_bits =3D kunit_kzalloc( test_writer->test, sizeof(*entry_used_bits) * NUM_ENTRY_QWORDS, GFP_KERNEL); KUNIT_ASSERT_NOT_NULL(test_writer->test, entry_used_bits); =20 + ignored =3D kunit_kzalloc(test_writer->test, + sizeof(*ignored) * NUM_ENTRY_QWORDS, + GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test_writer->test, ignored); + pr_debug("STE value is now set to: "); print_hex_dump_debug(" ", DUMP_PREFIX_NONE, 16, 8, test_writer->entry, @@ -79,14 +88,17 @@ arm_smmu_test_writer_record_syncs(struct arm_smmu_entry= _writer *writer) * configuration. */ writer->ops->get_used(test_writer->entry, entry_used_bits); + if (writer->ops->get_ignored) + writer->ops->get_ignored(ignored); KUNIT_EXPECT_FALSE( test_writer->test, arm_smmu_entry_differs_in_used_bits( test_writer->entry, entry_used_bits, - test_writer->init_entry, NUM_ENTRY_QWORDS) && + test_writer->init_entry, ignored, + NUM_ENTRY_QWORDS) && arm_smmu_entry_differs_in_used_bits( test_writer->entry, entry_used_bits, - test_writer->target_entry, + test_writer->target_entry, ignored, NUM_ENTRY_QWORDS)); } } @@ -106,6 +118,7 @@ arm_smmu_v3_test_debug_print_used_bits(struct arm_smmu_= entry_writer *writer, static const struct arm_smmu_entry_writer_ops test_ste_ops =3D { .sync =3D arm_smmu_test_writer_record_syncs, .get_used =3D arm_smmu_get_ste_used, + .get_ignored =3D arm_smmu_get_ste_ignored, }; =20 static const struct arm_smmu_entry_writer_ops test_cd_ops =3D { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d16d35c78c06..e22c0890041b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1082,6 +1082,12 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64= *used_bits) } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); =20 +VISIBLE_IF_KUNIT +void arm_smmu_get_ste_ignored(__le64 *ignored_bits) +{ +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_ignored); + /* * Figure out if we can do a hitless update of entry to become target. Ret= urns a * bit mask where 1 indicates that qword needs to be set disruptively. @@ -1094,13 +1100,22 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu= _entry_writer *writer, { __le64 target_used[NUM_ENTRY_QWORDS] =3D {}; __le64 cur_used[NUM_ENTRY_QWORDS] =3D {}; + __le64 ignored[NUM_ENTRY_QWORDS] =3D {}; u8 used_qword_diff =3D 0; unsigned int i; =20 writer->ops->get_used(entry, cur_used); writer->ops->get_used(target, target_used); + if (writer->ops->get_ignored) + writer->ops->get_ignored(ignored); =20 for (i =3D 0; i !=3D NUM_ENTRY_QWORDS; i++) { + /* + * Ignored is only used for bits that are used by both entries, + * otherwise it is sequenced according to the unused entry. + */ + ignored[i] &=3D target_used[i] & cur_used[i]; + /* * Check that masks are up to date, the make functions are not * allowed to set a bit to 1 if the used function doesn't say it @@ -1109,6 +1124,7 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu_e= ntry_writer *writer, WARN_ON_ONCE(target[i] & ~target_used[i]); =20 /* Bits can change because they are not currently being used */ + cur_used[i] &=3D ~ignored[i]; unused_update[i] =3D (entry[i] & cur_used[i]) | (target[i] & ~cur_used[i]); /* @@ -1207,12 +1223,9 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writ= er *writer, __le64 *entry, entry_set(writer, entry, target, 0, 1); } else { /* - * No inuse bit changed. Sanity check that all unused bits are 0 - * in the entry. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 02:45:52.1078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15a84c2d-0071-482a-d708-08de37963be7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4210 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV =3D=3D 0. So ignore MEV when computing the update sequence to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS = mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e22c0890041b..3e161d8298d9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); VISIBLE_IF_KUNIT void arm_smmu_get_ste_ignored(__le64 *ignored_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can ignore it + * when computing the ordering. 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X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?e6WXNJRS8aKg6j65f8lPv5ZUX0o0CgeQGNZJphU5NvXH1rkHs4Nvlth1wywp?= =?us-ascii?Q?hdU4mXpT3OuQZAZWEkjHpaH1diwyCaj1rH2IzuV0hPTxzmp4QC3OoPkhKvc6?= =?us-ascii?Q?UPATNHeYhiO1ViNrPOSSu8IIpRKVAmlDW8BXf6C9X9LJevX8lkUc8gvyiszg?= =?us-ascii?Q?nwbyhNj6WAfbdZGcS6hLl+VEz6gxr3pMjEcRGloFO73JninAZNeUTFukzRRd?= =?us-ascii?Q?OdavNbACNcYm5+11GfbhQLjCw/dA4j4Hs2EIENlWEHJidbL4YZNSlZLXVbxH?= =?us-ascii?Q?NKBztTNqbO3fWnlVibfzpxaOu4AQVSAB5Fr/JU1T1M+W9uBT4rgoukQdcrSI?= =?us-ascii?Q?dOOD9jrtI9i/icFcikg8cOCBmwdqjZF2dPgWgOrSnRoUqZeZeAThhcgoHQuc?= =?us-ascii?Q?5X7lK8BzwDN60f9/jdM30Gni133mLyABRA5w/a8omnX7UWOmBes6EabBRcNl?= =?us-ascii?Q?nmub/i/mcLrc/eJvm1qAbIL2d9VZLW67OXhig65F8MUhpIQ7F2SUDIlQILP0?= =?us-ascii?Q?L7KEY4l3fq9F6FBOlt58ePB6fTm4k/yzbjkIigbAMJuP7OFrH/oX1VHoRZJB?= =?us-ascii?Q?6TNHnhmr9Va3zVflqO89qp5ka5zf4+nOQOvIjDsYXGlA1+93tmY44/8JcW/P?= =?us-ascii?Q?VtPn99eU1SLv5dw6vpwxBL7kh9tgPZRMHXhQ+5d159Xtk2a2En700nILFCYs?= =?us-ascii?Q?Oa6yLbiWPzcHjrrEibsiNBueyxPcqiKx/ZakHEoOGulsd7jCkmvxDIHq11fT?= =?us-ascii?Q?DgJOFAJyDESN80dfCbYQZnCrHihXrp3Z/x6MOfUjTkQXyYnXrK0nEywNXgfZ?= =?us-ascii?Q?Asz91XtnJFk07Dve5C43gLIvMhaLaXq0JuvSMrV7rPYxNR0+9Aw/UpegkPbV?= =?us-ascii?Q?CJrOHi02/mOtZF25UUaiVHSgF27h32PxAF+tdqDIm2nfeV9TV9VYljQOSTd5?= =?us-ascii?Q?SY0snDlbpwbqMXaXCihdeQvFOd1WEKCq47ROWzwHibpUK6ACC7jTj7NuxSV7?= =?us-ascii?Q?v/HfCKNo4N9xh7nLMQKHPO/urZsqp2GWvG6dou37eTa+wwvlrcwa2zN2gbL4?= =?us-ascii?Q?fYmmaUPZiG6zfWzFRxI2K+ulUOVMWYrarWe/etqRQCnETL1TjPhapFUf7hYJ?= =?us-ascii?Q?nFVxOf/5b3/kwSUSb7j5Pxu/f41jZ4lXmB4FMBtXc961GOQFio6tJmPZ7EDB?= =?us-ascii?Q?MycQV7/w09Gr+P7wZWY0JOnzmjIoZmZgpOjhuXTR3b76k4Ka0UvRB7mk9O8Y?= =?us-ascii?Q?h2naxcN65Y8PCzAN/Gom8CcrTP4p3yuCb5xcnhWwyOtagMCBw7vKbxtL8+LZ?= =?us-ascii?Q?cCWJBsv6cG68XD2I3Oo36sJAmk14GdUdSCRM1PD5E79+AjCNPJG87dKIiQa3?= =?us-ascii?Q?1pbWZtjqmcocnwoFFn61fsX/vXtQBr9StmHTS6N1QhhrvYkoQx97snTgSr0v?= =?us-ascii?Q?hV78V8Zo51ScfuuuyoZXdCAonknP2BxgmRTBOBy8YP+6QxEcK4JtL6jvfO2g?= =?us-ascii?Q?Ji1TOc1j0Qme9PwzkPNTXsLZR7gX7AXbvaObHAnL4nVkr3IF3wutmX8zTyop?= =?us-ascii?Q?E2PuC9OCswfrLc6Dr3A=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 02:45:53.4909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6cf97fe-1154-459b-51b7-08de37963cb9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7282 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe If a VM wants to toggle EATS off at the same time as changing the CFG, the hypervisor will see EATS change to 0 and insert a V=3D0 breaking update into the STE even though the VM did not ask for that. In bare metal, EATS is ignored by CFG=3DABORT/BYPASS, which is why this does not cause a problem until we have nested where CFG is always a variation of S2 trans that does use EATS. Relax the rules for EATS sequencing, we don't need it to be exact because the enclosing code will always disable ATS at the PCI device if we are changing EATS. This ensures there are no ATS transactions that can race with an EATS change so we don't need to carefully sequence these bits. Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 3e161d8298d9..72ba41591fdb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1095,6 +1095,15 @@ void arm_smmu_get_ste_ignored(__le64 *ignored_bits) * fault records even when MEV =3D=3D 0. */ ignored_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + + /* + * EATS is used to reject and control the ATS behavior of the device. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 02:45:54.5376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a322130d-5f53-4833-7c69-08de37963d5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6074 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 3556e65cf9ac..ffa43e103692 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -33,8 +33,12 @@ static struct mm_struct sva_mm =3D { enum arm_smmu_test_master_feat { ARM_SMMU_MASTER_TEST_ATS =3D BIT(0), ARM_SMMU_MASTER_TEST_STALL =3D BIT(1), + ARM_SMMU_MASTER_TEST_NESTED =3D BIT(2), }; =20 +static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, + enum arm_smmu_test_master_feat feat); + static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, @@ -198,6 +202,17 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_= smmu_ste *ste, }; =20 arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { + struct arm_smmu_ste s2ste; + int i; + + arm_smmu_test_make_s2_ste(&s2ste, ARM_SMMU_MASTER_TEST_ATS); + ste->data[0] |=3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); + ste->data[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + for (i =3D 2; i < NUM_ENTRY_QWORDS; i++) + ste->data[i] =3D s2ste.data[i]; + } } =20 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) @@ -555,6 +570,35 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + /* Expect an additional sync to unset ignored bits: EATS and MEV */ + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(2)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -601,6 +645,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0