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Fri, 5 Dec 2025 16:52:18 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH rc v1 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence Date: Fri, 5 Dec 2025 16:52:00 -0800 Message-ID: <6ec73bb7cd03d90a0764f12c4b14071158163818.1764982046.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529D:EE_|PH7PR12MB8179:EE_ X-MS-Office365-Filtering-Correlation-Id: 310a8266-0768-46c0-f00a-08de3461b9d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AAWBpa3Nhrplge5BR6Nu39C7rfBwDK1X/YBqoxPYygJUPyiO9Ku+a2oihGq8?= =?us-ascii?Q?+mOlgkvsVralGnHIJqFL4WmxWtWIeLwO40XaWc1SdI950VLp7kiXv2Vx0Mna?= =?us-ascii?Q?VrvAHAHSIgR3G6nbOkjMFMgoiE4KEILn3AAoxhANZ3iYTt0yCpUn5xka2lJJ?= =?us-ascii?Q?q8uULuQgi6tu62wzaf2kEv3+g+pLf7YmUqRaWB2l+NEFIRnWDu5ID78a28BT?= =?us-ascii?Q?gFoYW+KFlwbv+dndGFy54hQ+uHveGwZNFc06eedN4bmFi0WWKZ70jZ+HIXFO?= =?us-ascii?Q?17/9UJikrYjETJ0OcR9WcNBIijEUMPEfohhE2AdqRATCJHiLKYg2V0WJLRjW?= =?us-ascii?Q?h6D30XCqMmxp0/T4I7wlycRAlzOK4u2FemiMvKiu54KUqDiyN5dhQ43Ng4ik?= =?us-ascii?Q?NcI9wrQz2YaQQyuCtA017qokQZ7jvOhGWRtt9yeZl9AdtZP/7yw8CkuRVF/j?= =?us-ascii?Q?RFKPOlgYAbW045SFP5KwhAoV08nHb7JLr2u01grG8xQg/k7rQ5hjUfzW4LTu?= =?us-ascii?Q?WeZLKuHJCp8i9dYMVWklr7itRy2ym/197uczzH/adWwA4Pqden4w8hrAqzR7?= =?us-ascii?Q?5aiITRis8YN1mkPD80u5Ekb6BQaPzQvDZ6LCATyDgmulk43kLEjxUXHQv7Rg?= =?us-ascii?Q?sR3VaLSkSpdmCZL7uNrfAFbYQh4+cFN1GWI3HyO4Nl4Y3ooD8ul4aQ2qHqxj?= =?us-ascii?Q?nUBv25ervzNW8FIm+sR/G3bjmSmUgM2TsnZ4D4HhNqxulI4QDj3kdOXWtr4K?= =?us-ascii?Q?k5JrPsZ+2odoBX3gX3/gRjRmilS97MfKh3ybctJ+LBpGfe0qkoyFkQf9B7Vv?= =?us-ascii?Q?ESGCG3tt7v1lzF252sA9ZW+a8fusDEeHRRo0JbEb/Z2ZoYAdmXaAD2o1q0+/?= =?us-ascii?Q?U3AQLrBa59SouGzSugpM3zHlCRB0z3pPBLAWhfh0G5qzz5YIUqr2GNhB6ehO?= =?us-ascii?Q?AnBPiVVBB2rdO/1J1xaYuMHw5lg+lXgQIMX4kDFoTDPcMab8g55oDrw2/5X2?= =?us-ascii?Q?sTOHfYhZU+j3UT52QY+iYQtkbFbl5qpBBYHGI+gQ4xr5Dbas1KqJ3iO7OBK9?= =?us-ascii?Q?yAFG3ZXs/nS+M3+TQhDh/HTsrNK+0mNPOVW/Yp54FUBcpDHr5Qwoz6jmQ817?= =?us-ascii?Q?VXgqKwKIzv7P+ELyVtBnKjmxswpXhrKJ7/+KlELTdb3ARxkhfvWv9xTvjAb+?= =?us-ascii?Q?DOvGVxnWJtsgWacT8bOdZLt/FftoVMFQvBFUdecBe10v3NOvYkX11ZOeQ1a6?= =?us-ascii?Q?2GlS3XRQcPtTmnADLDkAR5ZaQpHAGmUNbiuv6JM/T9nQZEZExEKxbJK0LqkP?= =?us-ascii?Q?6A4S3uXF6CuTQVqF1oYXTbvyvKySLzLlwznF9NJzwWtOQeGZ92k14xrOerwh?= =?us-ascii?Q?gX9lb+DSRcacUNF1SLhQ/KLZ2ssdx9JKKUFwEKuzmLwn23On9KCvekMZrlFb?= =?us-ascii?Q?AVWcAye1Z7qtFLNMRFESZLBVhd6ZnuZhZHE1QrcbkT1t1mQM8K0CH/D49bja?= =?us-ascii?Q?XAVvAEZcTFT0V5rwSDNU1Vfz0vI6AiYTlJ5GFRBeqLRgrcEL1tNuXmsJ3aRs?= =?us-ascii?Q?WhEkQz0MMo8W4gQexdw=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 00:52:26.6425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 310a8266-0768-46c0-f00a-08de3461b9d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8179 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe C_BAD_STE was observed when updating nested STE from an S1-bypass mode to an S1DSS-bypass mode. As both modes enabled S2, the used bit is slightly different than the normal S1-bypass and S1DSS-bypass modes. As a result, fields like MEV and EATS in S2's used list marked the word1 as a critical word that requested a STE.V=3D0. This breaks a hitless update. However, both MEV and EATS aren't critical in terms of STE update. One controls the merge of the events and the other controls the ATS that is managed by the driver at the same time via pci_enable_ats(). Add an arm_smmu_get_ste_ignored() to allow STE update algorithm to ignore those fields, avoiding the STE update breakages. Note that this change is required by both MEV and EATS fields, which were introduced in different kernel versions. So add this get_ignored() first. The MEV and EATS will be added in arm_smmu_get_ste_ignored() separately. Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 17 ++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24 ++++++++++++------- 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ae23aacc3840..d5f0e5407b9f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -900,6 +900,7 @@ struct arm_smmu_entry_writer { =20 struct arm_smmu_entry_writer_ops { void (*get_used)(const __le64 *entry, __le64 *used); + void (*get_ignored)(__le64 *ignored_bits); void (*sync)(struct arm_smmu_entry_writer *writer); }; =20 @@ -911,6 +912,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *t= arget, =20 #if IS_ENABLED(CONFIG_KUNIT) void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); +void arm_smmu_get_ste_ignored(__le64 *ignored_bits); void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *cu= r, const __le64 *target); void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd3798..9287904c93a2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -37,6 +37,7 @@ enum arm_smmu_test_master_feat { =20 static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, + const __le64 *ignored, const __le64 *target, unsigned int length) { @@ -44,7 +45,7 @@ static bool arm_smmu_entry_differs_in_used_bits(const __l= e64 *entry, unsigned int i; =20 for (i =3D 0; i < length; i++) { - if ((entry[i] & used_bits[i]) !=3D target[i]) + if ((entry[i] & used_bits[i]) !=3D (target[i] & ~ignored[i])) differs =3D true; } return differs; @@ -56,12 +57,18 @@ arm_smmu_test_writer_record_syncs(struct arm_smmu_entry= _writer *writer) struct arm_smmu_test_writer *test_writer =3D container_of(writer, struct arm_smmu_test_writer, writer); __le64 *entry_used_bits; + __le64 *ignored_bits; =20 entry_used_bits =3D kunit_kzalloc( test_writer->test, sizeof(*entry_used_bits) * NUM_ENTRY_QWORDS, GFP_KERNEL); KUNIT_ASSERT_NOT_NULL(test_writer->test, entry_used_bits); =20 + ignored_bits =3D kunit_kzalloc(test_writer->test, + sizeof(*ignored_bits) * NUM_ENTRY_QWORDS, + GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test_writer->test, ignored_bits); + pr_debug("STE value is now set to: "); print_hex_dump_debug(" ", DUMP_PREFIX_NONE, 16, 8, test_writer->entry, @@ -79,14 +86,17 @@ arm_smmu_test_writer_record_syncs(struct arm_smmu_entry= _writer *writer) * configuration. */ writer->ops->get_used(test_writer->entry, entry_used_bits); + if (writer->ops->get_ignored) + writer->ops->get_ignored(ignored_bits); KUNIT_EXPECT_FALSE( test_writer->test, arm_smmu_entry_differs_in_used_bits( test_writer->entry, entry_used_bits, - test_writer->init_entry, NUM_ENTRY_QWORDS) && + ignored_bits, test_writer->init_entry, + NUM_ENTRY_QWORDS) && arm_smmu_entry_differs_in_used_bits( test_writer->entry, entry_used_bits, - test_writer->target_entry, + ignored_bits, test_writer->target_entry, NUM_ENTRY_QWORDS)); } } @@ -106,6 +116,7 @@ arm_smmu_v3_test_debug_print_used_bits(struct arm_smmu_= entry_writer *writer, static const struct arm_smmu_entry_writer_ops test_ste_ops =3D { .sync =3D arm_smmu_test_writer_record_syncs, .get_used =3D arm_smmu_get_ste_used, + .get_ignored =3D arm_smmu_get_ste_ignored, }; =20 static const struct arm_smmu_entry_writer_ops test_cd_ops =3D { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d16d35c78c06..95a4cfc5882d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1082,6 +1082,12 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64= *used_bits) } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); =20 +VISIBLE_IF_KUNIT +void arm_smmu_get_ste_ignored(__le64 *ignored_bits) +{ +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_ignored); + /* * Figure out if we can do a hitless update of entry to become target. Ret= urns a * bit mask where 1 indicates that qword needs to be set disruptively. @@ -1094,11 +1100,14 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu= _entry_writer *writer, { __le64 target_used[NUM_ENTRY_QWORDS] =3D {}; __le64 cur_used[NUM_ENTRY_QWORDS] =3D {}; + __le64 ignored[NUM_ENTRY_QWORDS] =3D {}; u8 used_qword_diff =3D 0; unsigned int i; =20 writer->ops->get_used(entry, cur_used); writer->ops->get_used(target, target_used); + if (writer->ops->get_ignored) + writer->ops->get_ignored(ignored); =20 for (i =3D 0; i !=3D NUM_ENTRY_QWORDS; i++) { /* @@ -1106,16 +1115,17 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu= _entry_writer *writer, * allowed to set a bit to 1 if the used function doesn't say it * is used. */ - WARN_ON_ONCE(target[i] & ~target_used[i]); + WARN_ON_ONCE(target[i] & ~target_used[i] & ~ignored[i]); =20 /* Bits can change because they are not currently being used */ - unused_update[i] =3D (entry[i] & cur_used[i]) | + unused_update[i] =3D (entry[i] & (cur_used[i] | ignored[i])) | (target[i] & ~cur_used[i]); /* * Each bit indicates that a used bit in a qword needs to be * changed after unused_update is applied. */ - if ((unused_update[i] & target_used[i]) !=3D target[i]) + if ((unused_update[i] & target_used[i]) !=3D + (target[i] & ~ignored[i])) used_qword_diff |=3D 1 << i; } return used_qword_diff; @@ -1207,12 +1217,9 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writ= er *writer, __le64 *entry, entry_set(writer, entry, target, 0, 1); } else { /* - * No inuse bit changed. Sanity check that all unused bits are 0 - * in the entry. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 00:52:27.3289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c271487d-5866-4b4f-f8e1-08de3461ba42 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4416 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV =3D=3D 0. So ignore MEV when computing the update sequence to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS = mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 95a4cfc5882d..2df657c87abd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1052,7 +1052,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW | - STRTAB_STE_1_EATS | STRTAB_STE_1_MEV); + STRTAB_STE_1_EATS); used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID); =20 /* @@ -1068,7 +1068,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) if (cfg & BIT(1)) { used_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_S2FWB | STRTAB_STE_1_EATS | - STRTAB_STE_1_SHCFG | STRTAB_STE_1_MEV); + STRTAB_STE_1_SHCFG); used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); VISIBLE_IF_KUNIT void arm_smmu_get_ste_ignored(__le64 *ignored_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can ignore it + * when computing the ordering. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 00:52:29.2514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a0bee6c-f3a7-4a31-ac12-08de3461bb56 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF0000020A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9166 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe If a VM want to toggle EATS off the hypervisor will see EATS change to 0 and insert a V=3D0 breaking update into the STE even though the VM did not ask for that. Relax the rules for EATS sequencing, we don't need it to be exact because the enclosing code will always disable ATS at the PCI device if we are changing EATS. This ensures there are no ATS transactions that can race with an EATS change so we don't need to carefully sequence these bits. Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 2df657c87abd..6a982051c3c2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1051,8 +1051,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) used_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | - STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW | - STRTAB_STE_1_EATS); + STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW); used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID); =20 /* @@ -1067,8 +1066,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) /* S2 translates */ if (cfg & BIT(1)) { used_bits[1] |=3D - cpu_to_le64(STRTAB_STE_1_S2FWB | STRTAB_STE_1_EATS | - STRTAB_STE_1_SHCFG); + cpu_to_le64(STRTAB_STE_1_S2FWB | STRTAB_STE_1_SHCFG); used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | @@ -1095,6 +1093,15 @@ void arm_smmu_get_ste_ignored(__le64 *ignored_bits) * fault records even when MEV =3D=3D 0. */ ignored_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + + /* + * EATS is used to reject and control the ATS behavior of the device. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 00:52:28.2037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d2519f5-8c07-40ea-497f-08de3461bac7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7278 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 9287904c93a2..56bdcf5a517e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -553,6 +553,36 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_s2_ste(&s1_ste, ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0, + fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_s2_ste(&s1_ste, ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0, + fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(3)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -599,6 +629,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0