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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org Subject: [PATCH 1/4] net: stmmac: s32: use the syscon interface PHY_INTF_SEL_RGMII Message-ID: <6275e666a7ef78bd4c758d3f7f6fb6f30407393e.1764592300.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the s32 chipset the GMAC_0_CTRL_STS register is in GPR region. Originally, accessing this register was done in a sort of ad-hoc way, but we want to use the syscon interface to do it. This is a little bit uglier because we to maintain backwards compatibility to the old device trees so we have to support both ways to access this register. Signed-off-by: Dan Carpenter --- .../net/ethernet/stmicro/stmmac/dwmac-s32.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index 5a485ee98fa7..20de761b7d28 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include =20 #include "stmmac_platform.h" @@ -32,6 +34,8 @@ struct s32_priv_data { void __iomem *ioaddr; void __iomem *ctrl_sts; + struct regmap *sts_regmap; + unsigned int sts_offset; struct device *dev; phy_interface_t *intf_mode; struct clk *tx_clk; @@ -40,7 +44,10 @@ struct s32_priv_data { =20 static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) { - writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + if (gmac->ctrl_sts) + writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + else + regmap_write(gmac->sts_regmap, gmac->sts_offset, PHY_INTF_SEL_RGMII); =20 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); =20 @@ -125,10 +132,16 @@ static int s32_dwmac_probe(struct platform_device *pd= ev) "dt configuration failed\n"); =20 /* PHY interface mode control reg */ - gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(gmac->ctrl_sts)) - return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), - "S32CC config region is missing\n"); + gmac->sts_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "phy-sel", 1, &gmac->sts_offset); + if (gmac->sts_regmap =3D=3D ERR_PTR(-EPROBE_DEFER)) + return PTR_ERR(gmac->sts_regmap); + if (IS_ERR(gmac->sts_regmap)) { + gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(gmac->ctrl_sts)) + return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), + "S32CC config region is missing\n"); + } =20 /* tx clock */ gmac->tx_clk =3D devm_clk_get(&pdev->dev, "tx"); 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Mon, 01 Dec 2025 05:08:27 -0800 (PST) Date: Mon, 1 Dec 2025 16:08:24 +0300 From: Dan Carpenter To: Lee Jones Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , linaro-s32@linaro.org Subject: [PATCH 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NXP S32 SoCs have a GPR region which is used by a variety of drivers. Some examples of the registers in this region are: * DDR_PMU_IRQ * GMAC0_PHY_INTF_SEL * GMAC1_PHY_INTF_SEL * PFE_EMACS_INTF_SEL * PFE_COH_EN * PFE_PWR_CTRL * PFE_EMACS_GENCTRL1 * PFE_GENCTRL3 Use the syscon interface to access these registers. Signed-off-by: Dan Carpenter --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 55efb83b1495..6e6b92227092 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -102,6 +102,7 @@ select: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos @@ -212,6 +213,7 @@ properties: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos --=20 2.51.0 From nobody Mon Dec 1 20:56:10 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 983ED3164BC for ; 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Mon, 01 Dec 2025 05:08:32 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id a640c23a62f3a-b76f51c8393sm1220243266b.31.2025.12.01.05.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 05:08:31 -0800 (PST) Date: Mon, 1 Dec 2025 16:08:28 +0300 From: Dan Carpenter To: Jan Petrous Cc: s32@nxp.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org Subject: [PATCH 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Message-ID: <333487ea3d23699c7953524cda082813ac4d7be3.1764592300.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The S32 chipset has a GPR region which has a miscellaneous registers including the GMAC_0_CTRL_STS register. Originally this code accessed that register in a sort of ad-hoc way, but we want to access it using the syscon interface. We still need to maintain the old method of accessing the GMAC register but using a syscon will let us access other registers more cleanly. Signed-off-by: Dan Carpenter --- Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..17f6c50dca03 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -32,6 +32,11 @@ properties: - description: Main GMAC registers - description: GMAC PHY mode control register =20 + phy-sel: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: The offset into the s32 GPR syscon + interrupts: maxItems: 1 =20 @@ -74,6 +79,7 @@ examples: compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ + phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0 From nobody Mon Dec 1 20:56:10 2025 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1D99317709 for ; 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Mon, 01 Dec 2025 05:08:36 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id a640c23a62f3a-b76f51c67e2sm1228965866b.27.2025.12.01.05.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 05:08:36 -0800 (PST) Date: Mon, 1 Dec 2025 16:08:33 +0300 From: Dan Carpenter To: Chester Lin Cc: Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org Subject: [PATCH 4/4] dts: s32g: Add GPR syscon region Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..3c9472f6c174 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,13 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -731,6 +738,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index eff7673e7f34..0ceca3caf133 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,13 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -808,6 +815,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0