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(unknown [121.237.244.238]) by APP-01 (Coremail) with SMTP id qwCowABn_cxZ8yxpqd6vAg--.25095S2; Mon, 01 Dec 2025 09:46:03 +0800 (CST) From: zhouquan@iscas.ac.cn To: anup@brainfault.org, ajones@ventanamicro.com, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Quan Zhou Subject: [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM Date: Mon, 1 Dec 2025 09:28:25 +0800 Message-Id: <103e156ea1f2201db52034e370a907f46edafb83.1764509485.git.zhouquan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowABn_cxZ8yxpqd6vAg--.25095S2 X-Coremail-Antispam: 1UD129KBjvJXoWxArW8Ww47AryxCF17Jr1fZwb_yoW5GryDpr sxCF9akr45C34fua4xtr4kWr48u3y5WwsIgw18u34fXFy2krW8Jr1vya43Ja4DJa10grWv 9F18Wry8Zws8AwUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBC14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F 4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02 628vn2kIc2xKxwAKzVCY07xG64k0F24lc7CjxVAaw2AFwI0_Jw0_GFylc2xSY4AK67AK6w 4l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWU JVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7V AKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42 IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUYPfHDUUUU X-CM-SenderInfo: 52kr31xxdqqxpvfd2hldfou0/1tbiBg0DBmks7HsaLgAAso Content-Type: text/plain; charset="utf-8" From: Quan Zhou Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable zicfiss/zicfilp exts for Guest/VM, the rules defined in the spec [1] are as follows: --- 1) Zicfiss extension introduces the SSE field (bit 3) in henvcfg. If the SSE field is set to 1, the Zicfiss extension is activated in VS-mode. When the SSE field is 0, the Zicfiss extension remains inactive in VS-mode. 2) Zicfilp extension introduces the LPE field (bit 2) in henvcfg. When the LPE field is set to 1, the Zicfilp extension is enabled in VS-mode. When the LPE field is 0, the Zicfilp extension is not enabled in VS-mode. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Quan Zhou --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu.c | 6 ++++++ arch/riscv/kvm/vcpu_onereg.c | 2 ++ 3 files changed, 10 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 759a4852c09a..7ca087848a43 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -190,6 +190,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFBFMIN, KVM_RISCV_ISA_EXT_ZVFBFMIN, KVM_RISCV_ISA_EXT_ZVFBFWMA, + KVM_RISCV_ISA_EXT_ZICFILP, + KVM_RISCV_ISA_EXT_ZICFISS, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 5ce35aba6069..098d77f9a886 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -557,6 +557,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcp= u *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |=3D ENVCFG_CBZE; =20 + if (riscv_isa_extension_available(isa, ZICFILP)) + cfg->henvcfg |=3D ENVCFG_LPE; + + if (riscv_isa_extension_available(isa, ZICFISS)) + cfg->henvcfg |=3D ENVCFG_SSE; + if (riscv_isa_extension_available(isa, SVADU) && !riscv_isa_extension_available(isa, SVADE)) cfg->henvcfg |=3D ENVCFG_ADUE; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 865dae903aa0..3d05a4bafd9b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -72,6 +72,8 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(ZICBOP), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICCRSE), + KVM_ISA_EXT_ARR(ZICFILP), + KVM_ISA_EXT_ARR(ZICFISS), KVM_ISA_EXT_ARR(ZICNTR), KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), --=20 2.34.1 From nobody Mon Dec 1 22:04:07 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DA7172610; Mon, 1 Dec 2025 01:46:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764553582; cv=none; b=qDjwPb/Ee9R6hNve7sJ6hm1Vrzn278aYOLnGnmByZqC9a2ESrwKVaTgRrwQur5iOeQcqu9jnMlU6qJhoTSsb0uQEVWdj69kpyvOCuiJtBn7kml4JDgKvjP3Is71nE25wS0CeqEfgWpyjPZx0hG+88LF5LJKQE+HZzE06plDh3Bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764553582; c=relaxed/simple; bh=1NlUxVJXI80LACLgsudtnMDqE9VprO3S4doM6Ujl7gc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CGcVzZo3E2yS6AqwcEB9LRpLYRXsNnGko1H7HGVyDvBcR6W8c64s6U3lnMxe9RVG9vpvRAG+NNd6p+iE9azAqkUdPWoxEtUiLc5BNCrDmg/lMjmZ/pnCGN2VqWwFBRm/k4STvAtEcHiOwZuB53Du6D2peUWM6Yz/uOSmc5wr2Ag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from zq-Legion-Y7000.. (unknown [121.237.244.238]) by APP-01 (Coremail) with SMTP id qwCowADnf89j8yxpK9+vAg--.18813S2; Mon, 01 Dec 2025 09:46:12 +0800 (CST) From: zhouquan@iscas.ac.cn To: anup@brainfault.org, ajones@ventanamicro.com, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Quan Zhou Subject: [PATCH 2/4] RISC-V: KVM: Add support for software check exception Date: Mon, 1 Dec 2025 09:28:35 +0800 Message-Id: <0f23f96ee5abc5c445f1f482130e8efa33e7b97c.1764509485.git.zhouquan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowADnf89j8yxpK9+vAg--.18813S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Cryxtw1kJFyxJw4xCrWkXrb_yoW8tr47pF s8CF1v9rWrKr9akr1IyFnF9r4xGan8Kw1agryUtF45KrW7t3yUZ3s5K347JF98XF4kXF4I 9F18WFZ5uFn0qr7anT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBC14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F 4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02 628vn2kIc2xKxwAKzVCY07xG64k0F24lc7CjxVAaw2AFwI0_Jw0_GFylc2xSY4AK67AK6w 4l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWU JVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7V AKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42 IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUeKZXDUUUU X-CM-SenderInfo: 52kr31xxdqqxpvfd2hldfou0/1tbiCREDBmks7Hsa4gAAs3 Content-Type: text/plain; charset="utf-8" From: Quan Zhou zicfiss / zicfilp introduces a new exception to priv isa `software check exception` with cause code =3D 18. Delegate this exception to VS mode becau= se cfi violations in VU/VS will be reported via this exception. RISC-V KVM should ensure that even if the SBI implementation ignores hedeleg settings and routes VS-mode software check exceptions to HS mode, KVM still correctly forwards them to the guest. Otherwise, these exceptions would exit to userspace and terminate the guest. Signed-off-by: Quan Zhou --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/kvm_host.h | 3 ++- arch/riscv/kvm/vcpu_exit.c | 3 +++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 4a37a98398ad..9f10ef69de30 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -108,6 +108,7 @@ #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +#define EXC_SOFTWARE_CHECK 18 #define EXC_INST_GUEST_PAGE_FAULT 20 #define EXC_LOAD_GUEST_PAGE_FAULT 21 #define EXC_VIRTUAL_INST_FAULT 22 diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 4d794573e3db..0bb4da1c73df 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -53,7 +53,8 @@ BIT(EXC_SYSCALL) | \ BIT(EXC_INST_PAGE_FAULT) | \ BIT(EXC_LOAD_PAGE_FAULT) | \ - BIT(EXC_STORE_PAGE_FAULT)) + BIT(EXC_STORE_PAGE_FAULT)) | \ + BIT(EXC_SOFTWARE_CHECK) =20 #define KVM_HIDELEG_DEFAULT (BIT(IRQ_VS_SOFT) | \ BIT(IRQ_VS_TIMER) | \ diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 0bb0c51e3c89..5ab8e87ed248 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -243,6 +243,9 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct k= vm_run *run, run->exit_reason =3D KVM_EXIT_DEBUG; ret =3D 0; break; + case EXC_SOFTWARE_CHECK: + ret =3D vcpu_redirect(vcpu, trap); + break; default: break; } --=20 2.34.1 From nobody Mon Dec 1 22:04:07 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7A6C3B186; Mon, 1 Dec 2025 01:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764553593; cv=none; b=du5U8QEHM0hs8A5OF/NOpGihLxD9s/lZatzX95Td30wPrw+sHckuJei2dKO4D1KSbXQyZerHKIpDl1PzsHcPYSkE+1CfxURqyL1PV2cz+7Nrns9pkfdtGAnpFy5759gUcMjRfgLSHmjgKGbdMFtw7KmmobZjKpX4buSdQDy5UoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764553593; c=relaxed/simple; bh=zQk3DEOPSmblHG+Y2AODvaSB9c8Mqy/BweSJ4C9UuG8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mab7LK9A7Z6DfGUJGDtWkgnXJWNikjLhuX1TuOYjryfAKZ9YZ0YjnUCBGWIPgsZdLIR2gB96neHrlwAP8YREAQ7X/bLnTQ2ioQ4+zE5fMjZLdGT2SJycpXE3JUkKTOCC+fYNfwm4zb/ZURRFJsKl3ZwWcX/CjG51pMLxrClZmS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from zq-Legion-Y7000.. (unknown [121.237.244.238]) by APP-01 (Coremail) with SMTP id qwCowABX7Mtv8yxp69+vAg--.18496S2; Mon, 01 Dec 2025 09:46:24 +0800 (CST) From: zhouquan@iscas.ac.cn To: anup@brainfault.org, ajones@ventanamicro.com, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Quan Zhou Subject: [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features Date: Mon, 1 Dec 2025 09:28:48 +0800 Message-Id: <1793aa636969da0a09d27c9c12f6d5f8f0d1cd21.1764509485.git.zhouquan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowABX7Mtv8yxp69+vAg--.18496S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtw1xGr1UXF47Zr1rWryDJrb_yoW7tw4UpF WxWF9rWayfJr9Y93ZYyrsrWFWYgws7K3ZFyay7G34FvFy2kF45JF1kKr9rAryDA340vFWS kF4qqF1UCrs0v3JanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7Cj xVA2Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVAFwV WkMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_ Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x 0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8 JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIx AIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjiSdPUUUUU= = X-CM-SenderInfo: 52kr31xxdqqxpvfd2hldfou0/1tbiDAgDBmks7K0aZgAAs5 Content-Type: text/plain; charset="utf-8" From: Quan Zhou Add support in KVM SBI FWFT extension to allow VS-mode to request SBI_FWFT_{LANDING_PAD/SHADOW_STACK/PTE_AD_HW_UPDATING}. Signed-off-by: Quan Zhou --- arch/riscv/include/uapi/asm/kvm.h | 3 + arch/riscv/kvm/vcpu_sbi_fwft.c | 129 ++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 7ca087848a43..d93b70d89010 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -232,6 +232,9 @@ struct kvm_riscv_sbi_fwft_feature { struct kvm_riscv_sbi_fwft { struct kvm_riscv_sbi_fwft_feature misaligned_deleg; struct kvm_riscv_sbi_fwft_feature pointer_masking; + struct kvm_riscv_sbi_fwft_feature landing_pad; + struct kvm_riscv_sbi_fwft_feature shadow_stack; + struct kvm_riscv_sbi_fwft_feature pte_ad_hw_updating; }; =20 /* Possible states for kvm_riscv_timer */ diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 62cc9c3d5759..0dc0e70fc83b 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -213,6 +213,108 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu, return SBI_SUCCESS; } =20 +static long kvm_sbi_fwft_set_henvcfg_flag(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value, + unsigned long flag) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + if (value =3D=3D 1) + cfg->henvcfg |=3D flag; + else if (value =3D=3D 0) + cfg->henvcfg &=3D ~flag; + else + return SBI_ERR_INVALID_PARAM; + + if (!one_reg_access) + csr_write(CSR_HENVCFG, cfg->henvcfg); + + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_pointer_landing_pad_supported(struct kvm_vcpu *vc= pu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, ZICFILP); +} + +static void kvm_sbi_fwft_reset_landing_pad(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_LPE; +} + +static long kvm_sbi_fwft_set_landing_pad(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, E= NVCFG_LPE); +} + +static long kvm_sbi_fwft_get_landing_pad(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + *value =3D (cfg->henvcfg & ENVCFG_LPE) =3D=3D ENVCFG_LPE; + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_pointer_shadow_stack_supported(struct kvm_vcpu *v= cpu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, ZICFISS); +} + +static void kvm_sbi_fwft_reset_shadow_stack(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_SSE; +} + +static long kvm_sbi_fwft_set_shadow_stack(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, E= NVCFG_SSE); +} + +static long kvm_sbi_fwft_get_shadow_stack(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + *value =3D (cfg->henvcfg & ENVCFG_SSE) =3D=3D ENVCFG_SSE; + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_pointer_pte_ad_hw_updating_supported(struct kvm_v= cpu *vcpu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, SVADU) && + !riscv_isa_extension_available(vcpu->arch.isa, SVADE); +} + +static void kvm_sbi_fwft_reset_pte_ad_hw_updating(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_ADUE; +} + +static long kvm_sbi_fwft_set_pte_ad_hw_updating(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, E= NVCFG_ADUE); +} + +static long kvm_sbi_fwft_get_pte_ad_hw_updating(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + *value =3D (cfg->henvcfg & ENVCFG_ADUE) =3D=3D ENVCFG_ADUE; + return SBI_SUCCESS; +} + #endif =20 static const struct kvm_sbi_fwft_feature features[] =3D { @@ -236,6 +338,33 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { .get =3D kvm_sbi_fwft_get_pointer_masking_pmlen, }, #endif + { + .id =3D SBI_FWFT_LANDING_PAD, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, landing_pad.enabl= e) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_landing_pad_supported, + .reset =3D kvm_sbi_fwft_reset_landing_pad, + .set =3D kvm_sbi_fwft_set_landing_pad, + .get =3D kvm_sbi_fwft_get_landing_pad, + }, + { + .id =3D SBI_FWFT_SHADOW_STACK, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, shadow_stack.enab= le) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_shadow_stack_supported, + .reset =3D kvm_sbi_fwft_reset_shadow_stack, + .set =3D kvm_sbi_fwft_set_shadow_stack, + .get =3D kvm_sbi_fwft_get_shadow_stack, + }, + { + .id =3D SBI_FWFT_PTE_AD_HW_UPDATING, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pte_ad_hw_updatin= g.enable) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_pte_ad_hw_updating_supported, + .reset =3D kvm_sbi_fwft_reset_pte_ad_hw_updating, + .set =3D kvm_sbi_fwft_set_pte_ad_hw_updating, + .get =3D kvm_sbi_fwft_get_pte_ad_hw_updating, + }, }; =20 static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(u= nsigned long reg_num) --=20 2.34.1 From nobody Mon Dec 1 22:04:07 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09EA417A2FB; Mon, 1 Dec 2025 01:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764553614; cv=none; b=XrFrIcx88PbV7UAcgs9RQbt56GOZz9q/w17OOy4AjCwiGgaLGIEM5Hfl59UbmZqp8np+uCbemIY6XTyes1lv+vUFPYcRsAlAQeE6+5Tx9SHVVOFVkLjSnEgNPJD4ZktQ8P0n38QHlfn5LQMEcCLSEoR/ZhUWGKSqvhYQ0IgyZbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764553614; c=relaxed/simple; bh=8jfTpgaO22r45eCZ7WVt47x1jnjJkgLrg7mBE1ra28Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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(unknown [121.237.244.238]) by APP-01 (Coremail) with SMTP id qwCowAC3SMiC8yxpZOGvAg--.12442S2; Mon, 01 Dec 2025 09:46:44 +0800 (CST) From: zhouquan@iscas.ac.cn To: anup@brainfault.org, ajones@ventanamicro.com, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Quan Zhou Subject: [PATCH 4/4] KVM: riscv: selftests: Add zicfiss/zicfilp/svadu and SBI FWFT to get-reg-list test Date: Mon, 1 Dec 2025 09:29:07 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowAC3SMiC8yxpZOGvAg--.12442S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Jw1DGF1xCw1fZF1fAF45GFg_yoW7trWUpr yqyanI9r1kAwnYyrWvka4DWF4xZw4UAws5ua1xuw18tFyjyFyIqw1qyF1DGF1DJr18XrWS yFWrJr4Yya1FywUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7Cj xVA2Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVAFwV WkMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_ Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x 0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8 JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIx AIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjKZX7UUUUU= = X-CM-SenderInfo: 52kr31xxdqqxpvfd2hldfou0/1tbiBwkDBmks7NMaQgABso Content-Type: text/plain; charset="utf-8" From: Quan Zhou The KVM RISC-V allows zicfiss/zicfilp/svadu and SBI FWFT for Guest/VM, so add them to get-reg-list test. Signed-off-by: Quan Zhou --- .../selftests/kvm/riscv/get-reg-list.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 705ab3d7778b..cd9304943c9c 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -87,6 +87,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICBOP: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICCRSE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICFILP: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICFISS: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICNTR: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICOND: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICSR: @@ -546,6 +548,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(ZICBOP), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICCRSE), + KVM_ISA_EXT_ARR(ZICFILP), + KVM_ISA_EXT_ARR(ZICFISS), KVM_ISA_EXT_ARR(ZICNTR), KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), @@ -704,6 +708,15 @@ static const char *sbi_fwft_id_to_str(__u64 reg_off) case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.enable)"; case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.flags)"; case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.value)"; + case 6: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landi= ng_pad.enable)"; + case 7: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landi= ng_pad.flags)"; + case 8: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landi= ng_pad.value)"; + case 9: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shado= w_stack.enable)"; + case 10: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shad= ow_stack.flags)"; + case 11: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shad= ow_stack.value)"; + case 12: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_= ad_hw_updating.enable)"; + case 13: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_= ad_hw_updating.flags)"; + case 14: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_= ad_hw_updating.value)"; } return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_o= ff); } @@ -897,6 +910,15 @@ static __u64 sbi_fwft_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value), }; =20 static __u64 zicbom_regs[] =3D { @@ -1185,6 +1207,8 @@ KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM); KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP); KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ); KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE); +KVM_ISA_EXT_SIMPLE_CONFIG(zicfilp, ZICFILP); +KVM_ISA_EXT_SIMPLE_CONFIG(zicfiss, ZICFISS); KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR); KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND); KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR); @@ -1264,6 +1288,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_zicbop, &config_zicboz, &config_ziccrse, + &config_zicfilp, + &config_zicfiss, &config_zicntr, &config_zicond, &config_zicsr, --=20 2.34.1