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Tue, 25 Nov 2025 17:10:37 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v6 1/7] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Date: Tue, 25 Nov 2025 17:10:06 -0800 Message-ID: <479dc34a38e05ab3c88fc55703c4286a5233e7a0.1764119291.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE6:EE_|SJ0PR12MB8615:EE_ X-MS-Office365-Filtering-Correlation-Id: d786c05c-a5bb-4d8a-68e9-08de2c88a636 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?yhKi3cSxowA2VagDuNl4bvUNoW9MWFBXDATmLO5XK/SoPFblGouikWoecg1F?= =?us-ascii?Q?SCdfgT0KmCaYcUT/1s4HIMjTX5hevkQRP34PG+E+zoryzxaZDX+UzUt7Q/sE?= =?us-ascii?Q?WhNi12fEce4ZEcPhDv4462s09xzWb/ySENVXgJcik3Ic5WZyH/fDyiPHHc7e?= =?us-ascii?Q?Rks29Xm0Zihnfq9ZcEKGpd99xAOwjJp5c7t5n97LQB8Buu2VnSP0xNdVZVgI?= =?us-ascii?Q?vHS3vF+FTVrqGFS3E4umFf7G+J+CnTW2olJcGBDRpr7E/W7lx0xIv1sJYOdP?= =?us-ascii?Q?NCSUe6r2RbcPMtFBo84Kvhw2E/LtPqN8bPPeFSPz+8yzkXXJxjqe3TBOfIFj?= =?us-ascii?Q?8MrPyiXZqwmtK9lUG2uWqCUC5j4chVl0JLpm9QwYngUhYa3VG4ZMSf4QgrO2?= =?us-ascii?Q?/Txj901N8CM10NloHWXuZItVbq43SucUaFGf7tA7Nrl+NzQ86pR0p1zP1qkG?= =?us-ascii?Q?W0XXCOA6dWXS39NBfz7yNmwlG6yYDNVnT84uGtSCYTwNcAVGi2sQVR+h7emQ?= =?us-ascii?Q?vhH/Sej5MOTjSuDAeikv5VyGXQlvLdk+3pUWF1dH+lVvfOXYoxmAb5SQDu0Y?= =?us-ascii?Q?F8HpQsnxjKsTCm2NVDCadLo1lttHgiaQOa9Eeb16NjxIOHqxS/08bJISE8d3?= =?us-ascii?Q?1aLiB6D1EC6T9C2EJ7+GDp9IjCH+VAfNPR0ittZljk3GYMkKhyq7fxmOZ+gJ?= =?us-ascii?Q?WxVJ8JGWTXCkbRx8qEUy7pxXILwkuUGdOw6o8RpxNwx2dajCvsfRemmOPGet?= =?us-ascii?Q?x8Rs1ylZsguwmEroRF/blQYtE8aJ8N1UenLco0TfhJSW4IoZpTVOwkqXR/CC?= =?us-ascii?Q?g/IwxDUIDblDphwmuKI+ycjKh3v55QemZkzuBjmRqDnUFRDJ4s5OPODTGqdj?= =?us-ascii?Q?Oxz0Gt6xdCP9Az68ekcpEkhYgzuQulqRsV2dVwhPdp5gYb7QclqtWctj4bdI?= =?us-ascii?Q?FRtFRPW6Cb0EqydLzGzWkmNGhhm0ruxArFbyrCApTaw19gt0SU/LQ08i38Mu?= =?us-ascii?Q?Usf5G0oalqp/QtL/oFB9aV7eCbB3Q/NpG8zVy3P9EbTuGAw2F7ZpScJZ8+Yv?= =?us-ascii?Q?F3MwTy8lJW3HZ3+5/oOLQ5P0C6gVBKAqUIWaggk9gbZARvKL2F1l6QggGb28?= =?us-ascii?Q?xXSrawTHQu0BNXLxvCae/UoOMQ7JCbgm4LYbRqPw+SHHduY1zKLYgiAIWr+B?= =?us-ascii?Q?zD5Hz1eX+Pm/fzfgdZrf0oMZd3GcDub4Bs2CtGW7n1a8scuB52t6gV+SJKPE?= =?us-ascii?Q?yS9s51Hh2jjPObFCApGfkpEwizX2fqehTgj3CHIDrAO/+Cyou2nMYztl6JKz?= =?us-ascii?Q?/LuxCqy+SHgRVLdBE7a781woMr+bPHV7ApXWmDSk+YEe4IwL79tN/WZ1yJ9H?= =?us-ascii?Q?ovb4ZSHpQqMmoWMQ5QLKF7sKnbWD8FQXHWE5MsnjkeZjbB6eoB+386HgyyAb?= =?us-ascii?Q?V8FeGrD9USa0N7C3K8Zzo00EiKMHw/Rid5LHO2146HzHqgfiYZM4MxO4IRBr?= =?us-ascii?Q?IoxWnl+qEFtnwNmhqVDbkvyapbpDAFUAM4TILa7h3eZGOL1dw1EKGbeMuh+D?= =?us-ascii?Q?G7woHKB5fAg2EfoLe74=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:10:54.7488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d786c05c-a5bb-4d8a-68e9-08de2c88a636 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8615 Content-Type: text/plain; charset="utf-8" Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ae23aacc3840..5c0b38595d20 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -858,6 +858,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 =3D 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; =20 struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80..6097f1f540d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap =3D PAGE_SIZE; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:10:57.4108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc8f93ba-40d2-4efd-0014-08de2c88a7cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFF6E64BC2C Content-Type: text/plain; charset="utf-8" There will be a bit more things to free than smmu_domain itself. So keep a simple inline function in the header to share aross files. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Acked-by: Balbir Singh Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++-- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5c0b38595d20..96a23ca633cb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -954,6 +954,11 @@ extern struct mutex arm_smmu_asid_lock; =20 struct arm_smmu_domain *arm_smmu_domain_alloc(void); =20 +static inline void arm_smmu_domain_free(struct arm_smmu_domain *smmu_domai= n) +{ + kfree(smmu_domain); +} + void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid); struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 6097f1f540d8..440ad8cc07de 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -197,7 +197,8 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) =20 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) { - kfree(container_of(mn, struct arm_smmu_domain, mmu_notifier)); + arm_smmu_domain_free( + container_of(mn, struct arm_smmu_domain, mmu_notifier)); } =20 static const struct mmu_notifier_ops arm_smmu_mmu_notifier_ops =3D { @@ -365,6 +366,6 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, err_asid: xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); err_free: - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9d9f24a08062..e9759e8af0c0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2492,7 +2492,7 @@ static void arm_smmu_domain_free_paging(struct iommu_= domain *domain) ida_free(&smmu->vmid_map, cfg->vmid); } =20 - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); } =20 static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, @@ -3359,7 +3359,7 @@ arm_smmu_domain_alloc_paging_flags(struct device *dev= , u32 flags, return &smmu_domain->domain; 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Tue, 25 Nov 2025 17:10:39 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v6 3/7] iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_invs array Date: Tue, 25 Nov 2025 17:10:08 -0800 Message-ID: <8d02cbd9e58fe99f6a7576934d34b440b89e8c9d.1764119291.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D8:EE_|BY5PR12MB4228:EE_ X-MS-Office365-Filtering-Correlation-Id: 37e46f68-e047-42cf-340e-08de2c88a8dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?HlNsp+stPpYuAOP5tAnwduVbMfS51ikgLD2WPXYDpTxP+NyHigRGNWkbx3IE?= =?us-ascii?Q?kFPYxiwBr1/ef8WOVE+zi8OF+YxdJUVNDowF094ArdAOLI2K2gB23UDtPQMp?= =?us-ascii?Q?XnRxAEP3mbm9pn+IPhqXM/4YZcAA56szEoy9MJ1tJk7xOBFKREFGhXfPGckx?= =?us-ascii?Q?dfsy2Bgfdz6SiIzZZfpbak8Q74qsyQ2taOYFoGBGlbSlJW59WmORonPMYWWm?= =?us-ascii?Q?th485ZOKPBxN+EXSeraIxXWhGXKxJPEfikL4nTx84uFVH4tBFPk9W0cwO1oe?= =?us-ascii?Q?wekI7FQUWspyt8lbwDSjzMVjKRQykJPF0rLLG2JJPB0WVZNZgc27fCOZPpx7?= =?us-ascii?Q?eANoCV6WqBlGzY8U2GQsZZGmfHIkG92cPN6vWjTX1JP1GuRP0S3KXZ9C6acq?= =?us-ascii?Q?QG6Bpc6A4tJu8m1is2S72LqzGMMMS0WCOBC/GYqcThYWmxli5nQhvDxs0f2z?= =?us-ascii?Q?VFV5lUYADDWsieN0tHKfUfx42S8RQE6a22/cfg/4qBZle2DtUqtifaDM79z/?= =?us-ascii?Q?PTAGm5NRz8MjzcCNParwOVQsUeWzDdvRl6CZd4C2yx33SYGtjJBdnQBuWUgV?= =?us-ascii?Q?Bo95Rjr+8jGiGhrg79Rz8AV3AuVHz5dIWg2mjjW23OILSNmB5+PtBJPbS+oL?= =?us-ascii?Q?uxoaQYzYOJEzGARkvy+tioQwZt6FRqJA0u0ZeKCoVu8RikekZo7WkGRUudO4?= =?us-ascii?Q?C1sh7NwJw5j21hbIhOLWodLemSEjVHTjWzNxHjf2OSwjETXggxUfFEvo4s6y?= =?us-ascii?Q?g2xATv2RAQoms6dWF1KV0Z40LKidqEgM1DzqIqHbnwTd0iH0SWJy7t2lu309?= =?us-ascii?Q?mg5tP2cdAUyObfC3ekQp2jnIEw6eRwi7X6vhTcjmmZolspD2IjggBK5Swg3D?= =?us-ascii?Q?82vpv1bJuga5W4ay+nQkhcx2ZikNIIev6icN0HBUZGyCI3RCMe5fMgkdg7hj?= =?us-ascii?Q?qP/y4G7pMBrp5iuKZ3qxJpEeejC9afNncA+3rYntcUUSAFSKDNu06rMEcfvx?= =?us-ascii?Q?BxRFUjz7/n3ZRJfNsRVxela4o3NHRvb+vVG/csr8DR2WZTVBkv/QtxW8dya1?= =?us-ascii?Q?vNThMrtuChaS/JPK7m5dCqbd3fWVcdyV/fFe9wdtXrxGN0gqNOYXQW3j5b7D?= =?us-ascii?Q?q5WL7GE0LjLIimcH45fCkwSsCELNFmFTIE9rds7LXyceY4q/pg2ZCjR3osdC?= =?us-ascii?Q?i3nKW9X/Zcb31F2RddjOMx4aJNlHdj2QLbGGcFHsKmpqeCs6GNV4YSMWqqUr?= =?us-ascii?Q?SNmOA9xhu6exwN8hdNzTdSk3E6ouFCrmlaonq36RCHDGGxNPsaf8sES9IVYx?= =?us-ascii?Q?cNCxkBVr0rGTQnxvDtsxLhag4e5KkrbY/Cg/fKQNjK4RUibU7iHUvsBuv+s9?= =?us-ascii?Q?sRsXbyGPmsq8H160NeFqImFx20AjhKnWV7qawu1J8CHt0Vrj5QBeo7L2KZGz?= =?us-ascii?Q?68n4Ky1lav6o/WAKRK8UmEhk+IQYQBWoSh4fS7UvaZZvEpeF+/HI4SpympGC?= =?us-ascii?Q?uS9t0frKIyqOYuJXC12uC0ts/nnYEn4votpGPd1gvSum5+8wo/yLzVqVYb6v?= =?us-ascii?Q?a4idLT81Ma6RgrEwLgE=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:10:59.1874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37e46f68-e047-42cf-340e-08de2c88a8dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4228 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Create a new data structure to hold an array of invalidations that need to be performed for the domain based on what masters are attached, to replace the single smmu pointer and linked list of masters in the current design. Each array entry holds one of the invalidation actions - S1_ASID, S2_VMID, ATS or their variant with information to feed invalidation commands to HW. It is structured so that multiple SMMUs can participate in the same array, removing one key limitation of the current system. To maximize performance, a sorted array is used as the data structure. It allows grouping SYNCs together to parallelize invalidations. For instance, it will group all the ATS entries after the ASID/VMID entry, so they will all be pushed to the PCI devices in parallel with one SYNC. To minimize the locking cost on the invalidation fast path (reader of the invalidation array), the array is managed with RCU. Provide a set of APIs to add/delete entries to/from an array, which cover cannot-fail attach cases, e.g. attaching to arm_smmu_blocked_domain. Also add kunit coverage for those APIs. Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Co-developed-by: Nicolin Chen Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 97 +++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 92 +++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 256 ++++++++++++++++++ 3 files changed, 445 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 96a23ca633cb..c6fb84fc9201 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -649,6 +649,92 @@ struct arm_smmu_cmdq_batch { int num; }; =20 +/* + * The order here also determines the sequence in which commands are sent = to the + * command queue. E.g. TLBI must be done before ATC_INV. + */ +enum arm_smmu_inv_type { + INV_TYPE_S1_ASID, + INV_TYPE_S2_VMID, + INV_TYPE_S2_VMID_S1_CLEAR, + INV_TYPE_ATS, + INV_TYPE_ATS_FULL, +}; + +struct arm_smmu_inv { + struct arm_smmu_device *smmu; + u8 type; + u8 size_opcode; + u8 nsize_opcode; + u32 id; /* ASID or VMID or SID */ + union { + size_t pgsize; /* ARM_SMMU_FEAT_RANGE_INV */ + u32 ssid; /* INV_TYPE_ATS */ + }; + + refcount_t users; /* users=3D0 to mark as a trash to be purged */ +}; + +static inline bool arm_smmu_inv_is_ats(struct arm_smmu_inv *inv) +{ + return inv->type =3D=3D INV_TYPE_ATS || inv->type =3D=3D INV_TYPE_ATS_FUL= L; +} + +/** + * struct arm_smmu_invs - Per-domain invalidation array + * @max_invs: maximum capacity of the flexible array + * @num_invs: number of invalidations in the flexible array. May be smalle= r than + * @max_invs after a tailing trash entry is excluded, but must = not be + * greater than @max_invs + * @num_trashes: number of trash entries in the array for arm_smmu_invs_pu= rge(). + * Must not be greater than @num_invs + * @rwlock: optional rwlock to fench ATS operations + * @has_ats: flag if the array contains an INV_TYPE_ATS or INV_TYPE_ATS_FU= LL + * @rcu: rcu head for kfree_rcu() + * @inv: flexible invalidation array + * + * The arm_smmu_invs is an RCU data structure. During a ->attach_dev callb= ack, + * arm_smmu_invs_merge(), arm_smmu_invs_unref() and arm_smmu_invs_purge() = will + * be used to allocate a new copy of an old array for addition and deletio= n in + * the old domain's and new domain's invs arrays. + * + * The arm_smmu_invs_unref() mutates a given array, by internally reducing= the + * users counts of some given entries. This exists to support a no-fail ro= utine + * like attaching to an IOMMU_DOMAIN_BLOCKED. And it could pair with a fol= lowup + * arm_smmu_invs_purge() call to generate a new clean array. + * + * Concurrent invalidation thread will push every invalidation described i= n the + * array into the command queue for each invalidation event. It is designe= d like + * this to optimize the invalidation fast path by avoiding locks. + * + * A domain can be shared across SMMU instances. When an instance gets rem= oved, + * it would delete all the entries that belong to that SMMU instance. Then= , a + * synchronize_rcu() would have to be called to sync the array, to prevent= any + * concurrent invalidation thread accessing the old array from issuing com= mands + * to the command queue of a removed SMMU instance. + */ +struct arm_smmu_invs { + size_t max_invs; + size_t num_invs; + size_t num_trashes; + rwlock_t rwlock; + bool has_ats; + struct rcu_head rcu; + struct arm_smmu_inv inv[] __counted_by(max_invs); +}; + +static inline struct arm_smmu_invs *arm_smmu_invs_alloc(size_t num_invs) +{ + struct arm_smmu_invs *new_invs; + + new_invs =3D kzalloc(struct_size(new_invs, inv, num_invs), GFP_KERNEL); + if (!new_invs) + return NULL; + new_invs->max_invs =3D new_invs->num_invs =3D num_invs; + rwlock_init(&new_invs->rwlock); + return new_invs; +} + struct arm_smmu_evtq { struct arm_smmu_queue q; struct iopf_queue *iopf; @@ -875,6 +961,8 @@ struct arm_smmu_domain { =20 struct iommu_domain domain; =20 + struct arm_smmu_invs __rcu *invs; + /* List of struct arm_smmu_master_domain */ struct list_head devices; spinlock_t devices_lock; @@ -923,6 +1011,13 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *t= arget, void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, struct mm_struct *mm, u16 asid); + +struct arm_smmu_invs *arm_smmu_invs_merge(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_merge); +void arm_smmu_invs_unref(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_unref, + void (*free_fn)(struct arm_smmu_inv *inv)); +struct arm_smmu_invs *arm_smmu_invs_purge(struct arm_smmu_invs *invs); #endif =20 struct arm_smmu_master_domain { @@ -956,6 +1051,8 @@ struct arm_smmu_domain *arm_smmu_domain_alloc(void); =20 static inline void arm_smmu_domain_free(struct arm_smmu_domain *smmu_domai= n) { + /* No concurrency with invalidation is possible at this point */ + kfree(rcu_dereference_protected(smmu_domain->invs, true)); kfree(smmu_domain); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd3798..58ec7f2f4335 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -567,6 +567,97 @@ static void arm_smmu_v3_write_cd_test_sva_release(stru= ct kunit *test) NUM_EXPECTED_SYNCS(2)); } =20 +static void arm_smmu_v3_invs_test_verify(struct kunit *test, + struct arm_smmu_invs *invs, int num, + const int *ids, const int *users) +{ + KUNIT_EXPECT_EQ(test, invs->num_invs, num); + while (num--) { + KUNIT_EXPECT_EQ(test, invs->inv[num].id, ids[num]); + KUNIT_EXPECT_EQ(test, refcount_read(&invs->inv[num].users), + users[num]); + } +} + +static struct arm_smmu_invs invs1 =3D { + .num_invs =3D 3, + .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, + { .type =3D INV_TYPE_S2_VMID, .id =3D 2, }, + { .type =3D INV_TYPE_S2_VMID, .id =3D 3, }, }, +}; + +static struct arm_smmu_invs invs2 =3D { + .num_invs =3D 3, + .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ + { .type =3D INV_TYPE_ATS, .id =3D 4, }, + { .type =3D INV_TYPE_ATS, .id =3D 5, }, }, +}; + +static struct arm_smmu_invs invs3 =3D { + .num_invs =3D 3, + .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ + { .type =3D INV_TYPE_ATS, .id =3D 5, }, /* recover a trash */ + { .type =3D INV_TYPE_ATS, .id =3D 6, }, }, +}; + +static void arm_smmu_v3_invs_test(struct kunit *test) +{ + const int results1[2][3] =3D { { 1, 2, 3, }, { 1, 1, 1, }, }; + const int results2[2][5] =3D { { 1, 2, 3, 4, 5, }, { 2, 1, 1, 1, 1, }, }; + const int results3[2][3] =3D { { 1, 2, 3, }, { 1, 1, 1, }, }; + const int results4[2][5] =3D { { 1, 2, 3, 5, 6, }, { 2, 1, 1, 1, 1, }, }; + const int results5[2][5] =3D { { 1, 2, 3, 5, 6, }, { 1, 0, 0, 1, 1, }, }; + const int results6[2][3] =3D { { 1, 5, 6, }, { 1, 1, 1, }, }; + struct arm_smmu_invs *test_a, *test_b; + + /* New array */ + test_a =3D arm_smmu_invs_alloc(0); + KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); + + /* Test1: merge invs1 (new array) */ + test_b =3D arm_smmu_invs_merge(test_a, &invs1); + kfree(test_a); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results1[0]), + results1[0], results1[1]); + + /* Test2: merge invs2 (new array) */ + test_a =3D arm_smmu_invs_merge(test_b, &invs2); + kfree(test_b); + arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results2[0]), + results2[0], results2[1]); + + /* Test3: unref invs2 (same array) */ + arm_smmu_invs_unref(test_a, &invs2, NULL); + arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results3[0]), + results3[0], results3[1]); + KUNIT_EXPECT_EQ(test, test_a->num_trashes, 0); + + /* Test4: merge invs3 (new array) */ + test_b =3D arm_smmu_invs_merge(test_a, &invs3); + kfree(test_a); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results4[0]), + results4[0], results4[1]); + + /* Test5: unref invs1 (same array) */ + arm_smmu_invs_unref(test_b, &invs1, NULL); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results5[0]), + results5[0], results5[1]); + KUNIT_EXPECT_EQ(test, test_b->num_trashes, 2); + + /* Test6: purge test_b (new array) */ + test_a =3D arm_smmu_invs_purge(test_b); + kfree(test_b); + arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results6[0]), + results6[0], results6[1]); + + /* Test7: unref invs3 (same array) */ + arm_smmu_invs_unref(test_a, &invs3, NULL); + KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); + KUNIT_EXPECT_EQ(test, test_a->num_trashes, 0); + + kfree(test_a); +} + static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_ste_test_bypass_to_abort), KUNIT_CASE(arm_smmu_v3_write_ste_test_abort_to_bypass), @@ -590,6 +681,7 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), + KUNIT_CASE(arm_smmu_v3_invs_test), {}, }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e9759e8af0c0..f6bca44c78bf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1015,6 +1016,253 @@ static void arm_smmu_page_response(struct device *d= ev, struct iopf_fault *unused */ } =20 +/* Invalidation array manipulation functions */ +static inline struct arm_smmu_inv * +arm_smmu_invs_iter_next(struct arm_smmu_invs *invs, size_t next, size_t *i= dx) +{ + while (true) { + if (next >=3D invs->num_invs) { + *idx =3D next; + return NULL; + } + if (!refcount_read(&invs->inv[next].users)) { + next++; + continue; + } + *idx =3D next; + return &invs->inv[next]; + } +} + +/** + * arm_smmu_invs_for_each_entry - Iterate over all non-trash entries in in= vs + * @invs: the base invalidation array + * @idx: a stack variable of 'size_t', to store the array index + * @cur: a stack variable of 'struct arm_smmu_inv *' + */ +#define arm_smmu_invs_for_each_entry(invs, idx, cur) = \ + for (cur =3D arm_smmu_invs_iter_next(invs, 0, &(idx)); cur; \ + cur =3D arm_smmu_invs_iter_next(invs, idx + 1, &(idx))) + +static int arm_smmu_inv_cmp(const struct arm_smmu_inv *inv_l, + const struct arm_smmu_inv *inv_r) +{ + if (inv_l->smmu !=3D inv_r->smmu) + return cmp_int((uintptr_t)inv_l->smmu, (uintptr_t)inv_r->smmu); + if (inv_l->type !=3D inv_r->type) + return cmp_int(inv_l->type, inv_r->type); + return cmp_int(inv_l->id, inv_r->id); +} + +static inline int arm_smmu_invs_iter_next_cmp(struct arm_smmu_invs *invs_l, + size_t next_l, size_t *idx_l, + struct arm_smmu_invs *invs_r, + size_t next_r, size_t *idx_r) +{ + struct arm_smmu_inv *cur_l =3D + arm_smmu_invs_iter_next(invs_l, next_l, idx_l); + + /* + * We have to update the idx_r manually, because the invs_r cannot call + * arm_smmu_invs_iter_next() as the invs_r never sets any users counter. + */ + *idx_r =3D next_r; + + /* + * Compare of two sorted arrays items. If one side is past the end of + * the array, return the other side to let it run out the iteration. + * + * If the left entry is empty, return 1 to pick the right entry. + * If the right entry is empty, return -1 to pick the left entry. + */ + if (!cur_l) + return 1; + if (next_r >=3D invs_r->num_invs) + return -1; + return arm_smmu_inv_cmp(cur_l, &invs_r->inv[next_r]); +} + +/** + * arm_smmu_invs_for_each_entry - Iterate over two sorted arrays computing= for + * arm_smmu_invs_merge() or arm_smmu_invs_u= nref() + * @invs_l: the base invalidation array + * @idx_l: a stack variable of 'size_t', to store the base array index + * @invs_r: the build_invs array as to_merge or to_unref + * @idx_r: a stack variable of 'size_t', to store the build_invs index + * @cmp: a stack variable of 'int', to store return value (-1, 0, or 1) + */ +#define arm_smmu_invs_for_each_cmp(invs_l, idx_l, invs_r, idx_r, cmp) = \ + for (idx_l =3D idx_r =3D 0, = \ + cmp =3D arm_smmu_invs_iter_next_cmp(invs_l, 0, &(idx_l), \ + invs_r, 0, &(idx_r)); \ + idx_l < invs_l->num_invs || idx_r < invs_r->num_invs; \ + cmp =3D arm_smmu_invs_iter_next_cmp( \ + invs_l, idx_l + (cmp <=3D 0 ? 1 : 0), &(idx_l), \ + invs_r, idx_r + (cmp >=3D 0 ? 1 : 0), &(idx_r))) + +/** + * arm_smmu_invs_merge() - Merge @to_merge into @invs and generate a new a= rray + * @invs: the base invalidation array + * @to_merge: an array of invlidations to merge + * + * Return: a newly allocated array on success, or ERR_PTR + * + * This function must be locked and serialized with arm_smmu_invs_unref() = and + * arm_smmu_invs_purge(), but do not lockdep on any lock for KUNIT test. + * + * Both @invs and @to_merge must be sorted, to ensure the returned array w= ill be + * sorted as well. + * + * Caller is resposible for freeing the @invs and the returned new one. + * + * Entries marked as trash will be purged in the returned array. + */ +VISIBLE_IF_KUNIT +struct arm_smmu_invs *arm_smmu_invs_merge(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_merge) +{ + struct arm_smmu_invs *new_invs; + struct arm_smmu_inv *new; + size_t num_invs =3D 0; + size_t i, j; + int cmp; + + arm_smmu_invs_for_each_cmp(invs, i, to_merge, j, cmp) + num_invs++; + + new_invs =3D arm_smmu_invs_alloc(num_invs); + if (!new_invs) + return ERR_PTR(-ENOMEM); + + new =3D new_invs->inv; + arm_smmu_invs_for_each_cmp(invs, i, to_merge, j, cmp) { + if (cmp < 0) { + *new =3D invs->inv[i]; + } else if (cmp =3D=3D 0) { + *new =3D invs->inv[i]; + refcount_inc(&new->users); + } else { + *new =3D to_merge->inv[j]; + refcount_set(&new->users, 1); + } + + /* + * Check that the new array is sorted. This also validates that + * to_merge is sorted. + */ + if (new !=3D new_invs->inv) + WARN_ON_ONCE(arm_smmu_inv_cmp(new - 1, new) =3D=3D 1); + new++; + } + + WARN_ON(new !=3D new_invs->inv + new_invs->num_invs); + + return new_invs; +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge); + +/** + * arm_smmu_invs_unref() - Find in @invs for all entries in @to_unref, dec= rease + * the user counts without deletions + * @invs: the base invalidation array + * @to_unref: an array of invlidations to decrease their user counts + * @free_fn: A callback function to invoke, when an entry's user count red= uces + * to 0 + * + * Return: the number of trash entries in the array, for arm_smmu_invs_pur= ge() + * + * This function will not fail. Any entry with users=3D0 will be marked as= trash. + * All tailing trash entries in the array will be dropped. And the size of= the + * array will be trimmed properly. All trash entries in-between will remai= n in + * the @invs until being completely deleted by the next arm_smmu_invs_merg= e() + * or an arm_smmu_invs_purge() function call. + * + * This function must be locked and serialized with arm_smmu_invs_merge() = and + * arm_smmu_invs_purge(), but do not lockdep on any mutex for KUNIT test. + * + * Note that the final @invs->num_invs might not reflect the actual number= of + * invalidations due to trash entries. Any reader should take the read loc= k to + * iterate each entry and check its users counter till the last entry. + */ +VISIBLE_IF_KUNIT +void arm_smmu_invs_unref(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_unref, + void (*free_fn)(struct arm_smmu_inv *inv)) +{ + unsigned long flags; + size_t num_invs =3D 0; + size_t i, j; + int cmp; + + arm_smmu_invs_for_each_cmp(invs, i, to_unref, j, cmp) { + if (cmp < 0) { + /* not found in to_unref, leave alone */ + num_invs =3D i + 1; + } else if (cmp =3D=3D 0) { + /* same item */ + if (!refcount_dec_and_test(&invs->inv[i].users)) { + num_invs =3D i + 1; + continue; + } + + /* KUNIT test doesn't pass in a free_fn */ + if (free_fn) + free_fn(&invs->inv[i]); + invs->num_trashes++; + } else { + /* item in to_unref is not in invs or already a trash */ + WARN_ON(true); + } + } + + /* Exclude any tailing trash */ + invs->num_trashes -=3D invs->num_invs - num_invs; + + /* The lock is required to fence concurrent ATS operations. */ + write_lock_irqsave(&invs->rwlock, flags); + WRITE_ONCE(invs->num_invs, num_invs); /* Remove tailing trash entries */ + write_unlock_irqrestore(&invs->rwlock, flags); +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_unref); + +/** + * arm_smmu_invs_purge() - Purge all the trash entries in the @invs + * @invs: the base invalidation array + * + * Return: a newly allocated array on success removing all the trash entri= es, or + * NULL if there is no trash entry in the array or there is a bug + * + * This function must be locked and serialized with arm_smmu_invs_merge() = and + * arm_smmu_invs_unref(), but do not lockdep on any lock for KUNIT test. + * + * Caller is resposible for freeing the @invs and the returned new one. + */ +VISIBLE_IF_KUNIT +struct arm_smmu_invs *arm_smmu_invs_purge(struct arm_smmu_invs *invs) +{ + struct arm_smmu_invs *new_invs; + struct arm_smmu_inv *inv; + size_t i, num_invs =3D 0; + + if (WARN_ON(invs->num_invs < invs->num_trashes)) + return NULL; + if (!invs->num_invs || !invs->num_trashes) + return NULL; + + new_invs =3D arm_smmu_invs_alloc(invs->num_invs - invs->num_trashes); + if (!new_invs) + return ERR_PTR(-ENOMEM); + + arm_smmu_invs_for_each_entry(invs, i, inv) { + new_invs->inv[num_invs] =3D *inv; + num_invs++; + } + + WARN_ON(num_invs !=3D new_invs->num_invs); + return new_invs; +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_purge); + /* Context descriptor manipulation functions */ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) { @@ -2462,13 +2710,21 @@ static bool arm_smmu_enforce_cache_coherency(struct= iommu_domain *domain) struct arm_smmu_domain *arm_smmu_domain_alloc(void) { struct arm_smmu_domain *smmu_domain; + struct arm_smmu_invs *new_invs; =20 smmu_domain =3D kzalloc(sizeof(*smmu_domain), GFP_KERNEL); if (!smmu_domain) return ERR_PTR(-ENOMEM); =20 + new_invs =3D arm_smmu_invs_alloc(0); + if (!new_invs) { + kfree(smmu_domain); + return ERR_PTR(-ENOMEM); + } + INIT_LIST_HEAD(&smmu_domain->devices); spin_lock_init(&smmu_domain->devices_lock); + rcu_assign_pointer(smmu_domain->invs, new_invs); =20 return smmu_domain; } --=20 2.43.0 From nobody Mon Dec 1 23:34:49 2025 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011016.outbound.protection.outlook.com [40.107.208.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92EBF2F5A18 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:11:01.5676 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 766cce6b-9fe6-48f2-bcdd-08de2c88aa48 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6001 Content-Type: text/plain; charset="utf-8" When a master is attached from an old domain to a new domain, it needs to build an invalidation array to delete and add the array entries from/onto the invalidation arrays of those two domains, passed via the to_merge and to_unref arguments into arm_smmu_invs_merge/unref() respectively. Since the master->num_streams might differ across masters, a memory would have to be allocated when building an to_merge/to_unref array which might fail with -ENOMEM. On the other hand, an attachment to arm_smmu_blocked_domain must not fail so it's the best to avoid any memory allocation in that path. Pre-allocate a fixed size invalidation array for every master. This array will be used as a scratch to fill dynamically when building a to_merge or to_unref invs array. Sort fwspec->ids in an ascending order to fit to the arm_smmu_invs_merge() function. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 41 +++++++++++++++++++-- 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c6fb84fc9201..922a599ce0f1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -929,6 +929,14 @@ struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; struct arm_smmu_stream *streams; + /* + * Scratch memory for a to_merge or to_unref array to build a per-domain + * invalidation array. It'll be pre-allocated with enough enries for all + * possible build scenarios. It can be used by only one caller at a time + * until the arm_smmu_invs_merge/unref() finishes. Must be locked by the + * iommu_group mutex. + */ + struct arm_smmu_invs *build_invs; struct arm_smmu_vmaster *vmaster; /* use smmu->streams_mutex */ /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index f6bca44c78bf..81b5e28a5868 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3707,12 +3707,22 @@ static int arm_smmu_init_sid_strtab(struct arm_smmu= _device *smmu, u32 sid) return 0; } =20 +static int arm_smmu_stream_id_cmp(const void *_l, const void *_r) +{ + const typeof_member(struct arm_smmu_stream, id) *l =3D _l; + const typeof_member(struct arm_smmu_stream, id) *r =3D _r; + + return cmp_int(*l, *r); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { int i; int ret =3D 0; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + bool ats_supported =3D dev_is_pci(master->dev) && + pci_ats_supported(to_pci_dev(master->dev)); =20 master->streams =3D kcalloc(fwspec->num_ids, sizeof(*master->streams), GFP_KERNEL); @@ -3720,14 +3730,35 @@ static int arm_smmu_insert_master(struct arm_smmu_d= evice *smmu, return -ENOMEM; master->num_streams =3D fwspec->num_ids; =20 - mutex_lock(&smmu->streams_mutex); + if (!ats_supported) { + /* Base case has 1 ASID entry or maximum 2 VMID entries */ + master->build_invs =3D arm_smmu_invs_alloc(2); + } else { + /* ATS case adds num_ids of entries, on top of the base case */ + master->build_invs =3D arm_smmu_invs_alloc(2 + fwspec->num_ids); + } + if (!master->build_invs) { + kfree(master->streams); + return -ENOMEM; + } + for (i =3D 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream =3D &master->streams[i]; - struct rb_node *existing; - u32 sid =3D fwspec->ids[i]; =20 - new_stream->id =3D sid; + new_stream->id =3D fwspec->ids[i]; new_stream->master =3D master; + } + + /* Put the ids into order for sorted to_merge/to_unref arrays */ + sort_nonatomic(master->streams, master->num_streams, + sizeof(master->streams[0]), arm_smmu_stream_id_cmp, + NULL); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:11:00.1166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b46064d0-4e64-435b-4acb-08de2c88a96b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6465 Content-Type: text/plain; charset="utf-8" Update the invs array with the invalidations required by each domain type during attachment operations. Only an SVA domain or a paging domain will have an invs array: a. SVA domain will add an INV_TYPE_S1_ASID per SMMU and an INV_TYPE_ATS per SID b. Non-nesting-parent paging domain with no ATS-enabled master will add a single INV_TYPE_S1_ASID or INV_TYPE_S2_VMID per SMMU c. Non-nesting-parent paging domain with ATS-enabled master(s) will do (b) and add an INV_TYPE_ATS per SID d. Nesting-parent paging domain will add an INV_TYPE_S2_VMID followed by an INV_TYPE_S2_VMID_S1_CLEAR per vSMMU. For an ATS-enabled master, it will add an INV_TYPE_ATS_FULL per SID Note that case #d prepares for a future implementation of VMID allocation which requires a followup series for S2 domain sharing. So when a nesting parent domain is attached through a vSMMU instance using a nested domain. VMID will be allocated per vSMMU instance v.s. currectly per S2 domain. The per-domain invalidation is not needed until the domain is attached to a master (when it starts to possibly use TLB). This will make it possible to attach the domain to multiple SMMUs and avoid unnecessary invalidation overhead during teardown if no STEs/CDs refer to the domain. It also means that when the last device is detached, the old domain must flush its ASID or VMID, since any new iommu_unmap() call would not trigger invalidations given an empty domain->invs array. Introduce some arm_smmu_invs helper functions for building scratch arrays, preparing and installing old/new domain's invalidation arrays. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 17 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 246 +++++++++++++++++++- 2 files changed, 262 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 922a599ce0f1..cfd5036e3da6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1100,6 +1100,21 @@ static inline bool arm_smmu_master_canwbs(struct arm= _smmu_master *master) IOMMU_FWSPEC_PCI_RC_CANWBS; } =20 +/** + * struct arm_smmu_inv_state - Per-domain invalidation array state + * @invs_ptr: points to the domain->invs (unwinding nesting/etc.) or is NU= LL if + * no change should be made + * @old_invs: the original invs array + * @new_invs: for new domain, this is the new invs array to update domain-= >invs; + * for old domain, this is the master->build_invs to pass in as= the + * to_unref argument to an arm_smmu_invs_unref() call + */ +struct arm_smmu_inv_state { + struct arm_smmu_invs __rcu **invs_ptr; + struct arm_smmu_invs *old_invs; + struct arm_smmu_invs *new_invs; +}; + struct arm_smmu_attach_state { /* Inputs */ struct iommu_domain *old_domain; @@ -1109,6 +1124,8 @@ struct arm_smmu_attach_state { ioasid_t ssid; /* Resulting state */ struct arm_smmu_vmaster *vmaster; + struct arm_smmu_inv_state old_domain_invst; + struct arm_smmu_inv_state new_domain_invst; bool ats_enabled; }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 81b5e28a5868..d14894b99028 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3066,6 +3066,116 @@ static void arm_smmu_disable_iopf(struct arm_smmu_m= aster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +static struct arm_smmu_inv * +arm_smmu_master_build_inv(struct arm_smmu_master *master, + enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, + size_t pgsize) +{ + struct arm_smmu_invs *build_invs =3D master->build_invs; + struct arm_smmu_inv *cur, inv =3D { + .smmu =3D master->smmu, + .type =3D type, + .id =3D id, + .pgsize =3D pgsize, + }; + + if (WARN_ON(build_invs->num_invs >=3D build_invs->max_invs)) + return NULL; + cur =3D &build_invs->inv[build_invs->num_invs]; + build_invs->num_invs++; + + *cur =3D inv; + switch (type) { + case INV_TYPE_S1_ASID: + if (master->smmu->features & ARM_SMMU_FEAT_E2H) { + cur->size_opcode =3D CMDQ_OP_TLBI_EL2_VA; + cur->nsize_opcode =3D CMDQ_OP_TLBI_EL2_ASID; + } else { + cur->size_opcode =3D CMDQ_OP_TLBI_NH_VA; + cur->nsize_opcode =3D CMDQ_OP_TLBI_NH_ASID; + } + break; + case INV_TYPE_S2_VMID: + cur->size_opcode =3D CMDQ_OP_TLBI_S2_IPA; + cur->nsize_opcode =3D CMDQ_OP_TLBI_S12_VMALL; + break; + case INV_TYPE_S2_VMID_S1_CLEAR: + cur->size_opcode =3D cur->nsize_opcode =3D CMDQ_OP_TLBI_NH_ALL; + break; + case INV_TYPE_ATS: + case INV_TYPE_ATS_FULL: + cur->size_opcode =3D cur->nsize_opcode =3D CMDQ_OP_ATC_INV; + break; + } + + return cur; +} + +/* + * Use the preallocated scratch array at master->build_invs, to build a to= _merge + * or to_unref array, to pass into a following arm_smmu_invs_merge/unref()= call. + * + * Do not free the returned invs array. It is reused, and will be overwrit= ten by + * the next arm_smmu_master_build_invs() call. + */ +static struct arm_smmu_invs * +arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enable= d, + ioasid_t ssid, struct arm_smmu_domain *smmu_domain) +{ + const bool nesting =3D smmu_domain->nest_parent; + size_t pgsize =3D 0, i; + + iommu_group_mutex_assert(master->dev); + + master->build_invs->num_invs =3D 0; + + /* Range-based invalidation requires the leaf pgsize for calculation */ + if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) + pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_SVA: + case ARM_SMMU_DOMAIN_S1: + if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, + smmu_domain->cd.asid, + IOMMU_NO_PASID, pgsize)) + return NULL; + break; + case ARM_SMMU_DOMAIN_S2: + if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, + smmu_domain->s2_cfg.vmid, + IOMMU_NO_PASID, pgsize)) + return NULL; + break; + default: + WARN_ON(true); + return NULL; + } + + /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ + if (nesting) { + if (!arm_smmu_master_build_inv( + master, INV_TYPE_S2_VMID_S1_CLEAR, + smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + return NULL; + } + + for (i =3D 0; ats_enabled && i < master->num_streams; i++) { + /* + * If an S2 used as a nesting parent is changed we have no + * option but to completely flush the ATC. + */ + if (!arm_smmu_master_build_inv( + master, nesting ? INV_TYPE_ATS_FULL : INV_TYPE_ATS, + master->streams[i].id, ssid, 0)) + return NULL; + } + + /* Note this build_invs must have been sorted */ + + return master->build_invs; +} + static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, struct iommu_domain *domain, ioasid_t ssid) @@ -3095,6 +3205,131 @@ static void arm_smmu_remove_master_domain(struct ar= m_smmu_master *master, kfree(master_domain); } =20 +/* + * During attachment, the updates of the two domain->invs arrays are seque= nced: + * 1. new domain updates its invs array, merging master->build_invs + * 2. new domain starts to include the master during its invalidation + * 3. master updates its STE switching from the old domain to the new dom= ain + * 4. old domain still includes the master during its invalidation + * 5. old domain updates its invs array, unreferencing master->build_invs + * + * For 1 and 5, prepare the two updated arrays in advance, handling any ch= anges + * that can possibly failure. So the actual update of either 1 or 5 won't = fail. + * arm_smmu_asid_lock ensures that the old invs in the domains are intact = while + * we are sequencing to update them. + */ +static int arm_smmu_attach_prepare_invs(struct arm_smmu_attach_state *stat= e, + struct arm_smmu_domain *new_smmu_domain) +{ + struct arm_smmu_domain *old_smmu_domain =3D + to_smmu_domain_devices(state->old_domain); + struct arm_smmu_master *master =3D state->master; + ioasid_t ssid =3D state->ssid; + + /* A re-attach case doesn't need to update invs array */ + if (new_smmu_domain =3D=3D old_smmu_domain) + return 0; + + /* + * At this point a NULL domain indicates the domain doesn't use the + * IOTLB, see to_smmu_domain_devices(). + */ + if (new_smmu_domain) { + struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + struct arm_smmu_invs *build_invs; + + invst->invs_ptr =3D &new_smmu_domain->invs; + invst->old_invs =3D rcu_dereference_protected( + new_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + build_invs =3D arm_smmu_master_build_invs( + master, state->ats_enabled, ssid, new_smmu_domain); + if (!build_invs) + return -EINVAL; + + invst->new_invs =3D + arm_smmu_invs_merge(invst->old_invs, build_invs); + if (IS_ERR(invst->new_invs)) + return PTR_ERR(invst->new_invs); + } + + if (old_smmu_domain) { + struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + + invst->invs_ptr =3D &old_smmu_domain->invs; + invst->old_invs =3D rcu_dereference_protected( + old_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + /* For old_smmu_domain, new_invs points to master->build_invs */ + invst->new_invs =3D arm_smmu_master_build_invs( + master, master->ats_enabled, ssid, old_smmu_domain); + } + + return 0; +} + +/* Must be installed before arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_new_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + + if (!invst->invs_ptr) + return; + + rcu_assign_pointer(*invst->invs_ptr, invst->new_invs); + kfree_rcu(invst->old_invs, rcu); +} + +/* + * When an array entry's users count reaches zero, it means the ASID/VMID = is no + * longer being invalidated by map/unmap and must be cleaned. The rule is = that + * all ASIDs/VMIDs not in an invalidation array are left cleared in the IO= TLB. + */ +static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv) +{ + struct arm_smmu_cmdq_ent cmd =3D {}; + + switch (inv->type) { + case INV_TYPE_S1_ASID: + cmd.tlbi.asid =3D inv->id; + break; + case INV_TYPE_S2_VMID: + /* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */ + cmd.tlbi.vmid =3D inv->id; + break; + default: + return; + } + + cmd.opcode =3D inv->nsize_opcode; + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); +} + +/* Should be installed after arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + struct arm_smmu_invs *old_invs =3D invst->old_invs; + struct arm_smmu_invs *new_invs; + + lockdep_assert_held(&arm_smmu_asid_lock); + + if (!invst->invs_ptr) + return; + + arm_smmu_invs_unref(old_invs, invst->new_invs, + arm_smmu_inv_flush_iotlb_tag); + + new_invs =3D arm_smmu_invs_purge(old_invs); + if (!new_invs) + return; + + rcu_assign_pointer(*invst->invs_ptr, new_invs); + kfree_rcu(old_invs, rcu); +} + /* * Start the sequence to attach a domain to a master. The sequence contain= s three * steps: @@ -3152,12 +3387,16 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_= state *state, arm_smmu_ats_supported(master); } =20 + ret =3D arm_smmu_attach_prepare_invs(state, smmu_domain); + if (ret) + return ret; + if (smmu_domain) { if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { ret =3D arm_smmu_attach_prepare_vmaster( state, to_smmu_nested_domain(new_domain)); if (ret) - return ret; + goto err_unprepare_invs; } =20 master_domain =3D kzalloc(sizeof(*master_domain), GFP_KERNEL); @@ -3205,6 +3444,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_install_new_domain_invs(state); } =20 if (!state->ats_enabled && master->ats_enabled) { @@ -3224,6 +3465,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, kfree(master_domain); err_free_vmaster: kfree(state->vmaster); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:11:00.4859 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9810ca2-07bc-4ebf-8eb4-08de2c88a9a1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7714 Content-Type: text/plain; charset="utf-8" Each smmu_domain now has an arm_smmu_invs that specifies the invalidation steps to perform after any change the IOPTEs. This includes supports for basic ASID/VMID, the special case for nesting, and ATC invalidations. Introduce a new arm_smmu_domain_inv helper iterating smmu_domain->invs to convert the invalidation array to commands. Any invalidation request with no size specified means an entire flush over a range based one. Take advantage of the sorted array to compatible batch operations together to the same SMMU. For instance, ATC invaliations for multiple SIDs can be pushed as a batch. ATC invalidations must be completed before the driver disables ATS. Or the device is permitted to ignore any racing invalidation that would cause an SMMU timeout. The sequencing is done with a rwlock where holding the write side of the rwlock means that there are no outstanding ATC invalidations. If ATS is not used the rwlock is ignored, similar to the existing code. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 236 ++++++++++++++++++-- 2 files changed, 232 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index cfd5036e3da6..ecc49ec99df6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1085,6 +1085,15 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova,= size_t size, int asid, int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size); =20 +void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, + unsigned long iova, size_t size, + unsigned int granule, bool leaf); + +static inline void arm_smmu_domain_inv(struct arm_smmu_domain *smmu_domain) +{ + arm_smmu_domain_inv_range(smmu_domain, 0, 0, 0, false); +} + void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d14894b99028..af3d067d7028 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2514,23 +2514,19 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_atc_inv_domain(smmu_domain, 0, 0); } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) +static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + size_t granule, size_t pgsize) { - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - unsigned long end =3D iova + size, num_pages =3D 0, tg =3D 0; + unsigned long end =3D iova + size, num_pages =3D 0, tg =3D pgsize; size_t inv_range =3D granule; - struct arm_smmu_cmdq_batch cmds; =20 if (!size) return; =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { - /* Get the leaf page size */ - tg =3D __ffs(smmu_domain->domain.pgsize_bitmap); - num_pages =3D size >> tg; =20 /* Convert page size of 12,14,16 (log2) to 1,2,3 */ @@ -2550,8 +2546,6 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_= cmdq_ent *cmd, num_pages++; } =20 - arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); - while (iova < end) { if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { /* @@ -2579,9 +2573,26 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu= _cmdq_ent *cmd, } =20 cmd->tlbi.addr =3D iova; - arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); + arm_smmu_cmdq_batch_add(smmu, cmds, cmd); iova +=3D inv_range; } +} + +static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + size_t granule, + struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_cmdq_batch cmds; + size_t pgsize; + + /* Get the leaf page size */ + pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); + + arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); + arm_smmu_cmdq_batch_add_range(smmu, &cmds, cmd, iova, size, granule, + pgsize); arm_smmu_cmdq_batch_submit(smmu, &cmds); } =20 @@ -2637,6 +2648,193 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova= , size_t size, int asid, __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); } =20 +static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t= size, + size_t granule) +{ + size_t max_tlbi_ops; + + /* 0 size means invalidate all */ + if (!size || size =3D=3D SIZE_MAX) + return true; + + if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) + return false; + + /* + * Borrowed from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, + * this is used as a threshold to replace "size_opcode" commands with a + * single "nsize_opcode" command, when SMMU doesn't implement the range + * invalidation feature, where there can be too many per-granule TLBIs, + * resulting in a soft lockup. + */ + max_tlbi_ops =3D 1 << (ilog2(granule) - 3); + return size >=3D max_tlbi_ops * granule; +} + +/* Used by non INV_TYPE_ATS* invalidations */ +static void arm_smmu_inv_to_cmdq_batch(struct arm_smmu_inv *inv, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + unsigned int granule) +{ + if (arm_smmu_inv_size_too_big(inv->smmu, size, granule)) { + cmd->opcode =3D inv->nsize_opcode; + arm_smmu_cmdq_batch_add(inv->smmu, cmds, cmd); + return; + } + + cmd->opcode =3D inv->size_opcode; + arm_smmu_cmdq_batch_add_range(inv->smmu, cmds, cmd, iova, size, granule, + inv->pgsize); +} + +static inline bool arm_smmu_invs_end_batch(struct arm_smmu_inv *cur, + struct arm_smmu_inv *next) +{ + /* Changing smmu means changing command queue */ + if (cur->smmu !=3D next->smmu) + return true; + /* The batch for S2 TLBI must be done before nested S1 ASIDs */ + if (cur->type !=3D INV_TYPE_S2_VMID_S1_CLEAR && + next->type =3D=3D INV_TYPE_S2_VMID_S1_CLEAR) + return true; + /* ATS must be after a sync of the S1/S2 invalidations */ + if (!arm_smmu_inv_is_ats(cur) && arm_smmu_inv_is_ats(next)) + return true; + return false; +} + +static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs, + unsigned long iova, size_t size, + unsigned int granule, bool leaf) +{ + struct arm_smmu_cmdq_batch cmds =3D {}; + struct arm_smmu_inv *cur; + struct arm_smmu_inv *end; + + cur =3D invs->inv; + end =3D cur + READ_ONCE(invs->num_invs); + /* Skip any leading entry marked as a trash */ + for (; cur !=3D end; cur++) + if (refcount_read(&cur->users)) + break; + while (cur !=3D end) { + struct arm_smmu_device *smmu =3D cur->smmu; + struct arm_smmu_cmdq_ent cmd =3D { + /* + * Pick size_opcode to run arm_smmu_get_cmdq(). This can + * be changed to nsize_opcode, which would result in the + * same CMDQ pointer. + */ + .opcode =3D cur->size_opcode, + }; + struct arm_smmu_inv *next; + + if (!cmds.num) + arm_smmu_cmdq_batch_init(smmu, &cmds, &cmd); + + switch (cur->type) { + case INV_TYPE_S1_ASID: + cmd.tlbi.asid =3D cur->id; + cmd.tlbi.leaf =3D leaf; + arm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size, + granule); + break; + case INV_TYPE_S2_VMID: + cmd.tlbi.vmid =3D cur->id; + cmd.tlbi.leaf =3D leaf; + arm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size, + granule); + break; + case INV_TYPE_S2_VMID_S1_CLEAR: + /* CMDQ_OP_TLBI_S12_VMALL already flushed S1 entries */ + if (arm_smmu_inv_size_too_big(cur->smmu, size, granule)) + continue; + cmd.tlbi.vmid =3D cur->id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + break; + case INV_TYPE_ATS: + arm_smmu_atc_inv_to_cmd(cur->ssid, iova, size, &cmd); + cmd.atc.sid =3D cur->id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + break; + case INV_TYPE_ATS_FULL: + arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); + cmd.atc.sid =3D cur->id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + break; + default: + WARN_ON_ONCE(1); + continue; + } + + /* Skip any trash entry in-between */ + for (next =3D cur + 1; next !=3D end; next++) + if (refcount_read(&next->users)) + break; + + if (cmds.num && + (next =3D=3D end || arm_smmu_invs_end_batch(cur, next))) { + arm_smmu_cmdq_batch_submit(smmu, &cmds); + cmds.num =3D 0; + } + cur =3D next; + } +} + +void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, + unsigned long iova, size_t size, + unsigned int granule, bool leaf) +{ + struct arm_smmu_invs *invs; + + /* + * An invalidation request must follow some IOPTE change and then load + * an invalidation array. In the meantime, a domain attachment mutates + * the array and then stores an STE/CD asking SMMU HW to acquire those + * changed IOPTEs. In other word, these two are interdependent and can + * race. + * + * In a race, the RCU design (with its underlying memory barriers) can + * ensure the invalidation array to always get updated before loaded. + * + * smp_mb() is used here, paired with the smp_mb() following the array + * update in a concurrent attach, to ensure: + * - HW sees the new IOPTEs if it walks after STE installation + * - Invalidation thread sees the updated array with the new ASID. + * + * [CPU0] | [CPU1] + * | + * change IOPTEs and TLB flush: | + * arm_smmu_domain_inv_range() { | arm_smmu_install_new_domain_invs { + * ... | rcu_assign_pointer(new_invs); + * smp_mb(); // ensure IOPTEs | smp_mb(); // ensure new_invs + * ... | kfree_rcu(old_invs, rcu); + * // load invalidation array | } + * invs =3D rcu_dereference(); | arm_smmu_install_ste_for_dev { + * | STE =3D TTB0 // read new IOPTEs + */ + smp_mb(); + + rcu_read_lock(); + invs =3D rcu_dereference(smmu_domain->invs); + + /* + * Avoid locking unless ATS is being used. No ATC invalidation can be + * going on after a domain is detached. + */ + if (invs->has_ats) { + read_lock(&invs->rwlock); + __arm_smmu_domain_inv_range(invs, iova, size, granule, leaf); + read_unlock(&invs->rwlock); + } else { + __arm_smmu_domain_inv_range(invs, iova, size, granule, leaf); + } + + rcu_read_unlock(); +} + static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, unsigned long iova, size_t granule, void *cookie) @@ -3278,6 +3476,12 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_att= ach_state *state) return; =20 rcu_assign_pointer(*invst->invs_ptr, invst->new_invs); + /* + * We are committed to updating the STE. Ensure the invalidation array + * is visable to concurrent map/unmap threads, and acquire any racying + * IOPTE updates. + */ + smp_mb(); kfree_rcu(invst->old_invs, rcu); } =20 @@ -3327,6 +3531,12 @@ arm_smmu_install_old_domain_invs(struct arm_smmu_att= ach_state *state) return; =20 rcu_assign_pointer(*invst->invs_ptr, new_invs); + /* + * We are committed to updating the STE. Ensure the invalidation array + * is visable to concurrent map/unmap threads, and acquire any racying + * IOPTE updates. + */ + smp_mb(); kfree_rcu(old_invs, rcu); } =20 --=20 2.43.0 From nobody Mon Dec 1 23:34:49 2025 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010071.outbound.protection.outlook.com [52.101.193.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C4FF2FF65F for ; Wed, 26 Nov 2025 01:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.193.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764119478; cv=fail; b=OfIFeKag3664qN5tOLuSvBnrliADgHgehdFZqgKWjIcnaKQAp/PcqqeoUJuntqbPkS7paV0M19zQcRkTLnUmJ3e8t/RPv+X4gdmUV8Y9Aww1zWDkvZraOJ4r3mLGAbwr/2Mu2TIcQEE3YLfxU3QQZiAqpnk1gvkkv+FHFsa4/qs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 01:11:04.3318 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10c78bf4-fa72-4bd5-c0cc-08de2c88abe8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6172 Content-Type: text/plain; charset="utf-8" Replace the old invalidation functions with arm_smmu_domain_inv_range() in all the existing invalidation routines. And deprecate the old functions. The new arm_smmu_domain_inv_range() handles the CMDQ_MAX_TLBI_OPS as well, so drop it in the SVA function. Since arm_smmu_cmdq_batch_add_range() has only one caller now, and it must be given a valid size, add a WARN_ON_ONCE to catch any missed case. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 - .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 29 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 165 +----------------- 3 files changed, 11 insertions(+), 190 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ecc49ec99df6..47d534d3c15e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1078,13 +1078,6 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old); =20 -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain); -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size); - void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size, unsigned int granule, bool leaf); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 440ad8cc07de..f1f8e01a7e91 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -122,15 +122,6 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_sva_cd); =20 -/* - * Cloned from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, this - * is used as a threshold to replace per-page TLBI commands to issue in the - * command queue with an address-space TLBI command, when SMMU w/o a range - * invalidation feature handles too many per-page TLBI commands, which will - * otherwise result in a soft lockup. - */ -#define CMDQ_MAX_TLBI_OPS (1 << (PAGE_SHIFT - 3)) - static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier= *mn, struct mm_struct *mm, unsigned long start, @@ -146,21 +137,8 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs= (struct mmu_notifier *mn, * range. So do a simple translation here by calculating size correctly. */ size =3D end - start; - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { - if (size >=3D CMDQ_MAX_TLBI_OPS * PAGE_SIZE) - size =3D 0; - } else { - if (size =3D=3D ULONG_MAX) - size =3D 0; - } - - if (!size) - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - else - arm_smmu_tlb_inv_range_asid(start, size, smmu_domain->cd.asid, - PAGE_SIZE, false, smmu_domain); =20 - arm_smmu_atc_inv_domain(smmu_domain, start, size); + arm_smmu_domain_inv_range(smmu_domain, start, size, PAGE_SIZE, false); } =20 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct = *mm) @@ -191,8 +169,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) @@ -302,7 +279,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domai= n *domain) /* * Ensure the ASID is empty in the iommu cache before allowing reuse. */ - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); + arm_smmu_domain_inv(smmu_domain); =20 /* * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index af3d067d7028..d53e685e1968 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1264,16 +1264,6 @@ struct arm_smmu_invs *arm_smmu_invs_purge(struct arm= _smmu_invs *invs) EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_purge); =20 /* Context descriptor manipulation functions */ -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, - .tlbi.asid =3D asid, - }; - - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); -} =20 /* * Based on the value of ent report which bits of the STE the HW will acce= ss. It @@ -2428,74 +2418,10 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_= master *master, return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); } =20 -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size) -{ - struct arm_smmu_master_domain *master_domain; - int i; - unsigned long flags; - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D CMDQ_OP_ATC_INV, - }; - struct arm_smmu_cmdq_batch cmds; - - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) - return 0; - - /* - * Ensure that we've completed prior invalidation of the main TLBs - * before we read 'nr_ats_masters' in case of a concurrent call to - * arm_smmu_enable_ats(): - * - * // unmap() // arm_smmu_enable_ats() - * TLBI+SYNC atomic_inc(&nr_ats_masters); - * smp_mb(); [...] - * atomic_read(&nr_ats_masters); pci_enable_ats() // writel() - * - * Ensures that we always see the incremented 'nr_ats_masters' count if - * ATS was enabled at the PCI device before completion of the TLBI. - */ - smp_mb(); - if (!atomic_read(&smmu_domain->nr_ats_masters)) - return 0; - - arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); - - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_for_each_entry(master_domain, &smmu_domain->devices, - devices_elm) { - struct arm_smmu_master *master =3D master_domain->master; - - if (!master->ats_enabled) - continue; - - if (master_domain->nested_ats_flush) { - /* - * If a S2 used as a nesting parent is changed we have - * no option but to completely flush the ATC. - */ - arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); - } else { - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, - &cmd); - } - - for (i =3D 0; i < master->num_streams; i++) { - cmd.atc.sid =3D master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); - } - } - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); - - return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); -} - /* IO_PGTABLE API */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd; =20 /* * NOTE: when io-pgtable is in non-strict mode, we may get here with @@ -2504,14 +2430,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); - } - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu, @@ -2523,7 +2442,7 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_= smmu_device *smmu, unsigned long end =3D iova + size, num_pages =3D 0, tg =3D pgsize; size_t inv_range =3D granule; =20 - if (!size) + if (WARN_ON_ONCE(!size)) return; =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { @@ -2578,76 +2497,6 @@ static void arm_smmu_cmdq_batch_add_range(struct arm= _smmu_device *smmu, } } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_batch cmds; - size_t pgsize; - - /* Get the leaf page size */ - pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); - - arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); - arm_smmu_cmdq_batch_add_range(smmu, &cmds, cmd, iova, size, granule, - pgsize); - arm_smmu_cmdq_batch_submit(smmu, &cmds); -} - -static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .tlbi =3D { - .leaf =3D leaf, - }, - }; - - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->cd.asid; - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); - - if (smmu_domain->nest_parent) { - /* - * When the S2 domain changes all the nested S1 ASIDs have to be - * flushed too. - */ - cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; - arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); - } - - /* - * Unfortunately, this can't be leaf-only since we may have - * zapped an entire table. - */ - arm_smmu_atc_inv_domain(smmu_domain, iova, size); -} - -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA, - .tlbi =3D { - .asid =3D asid, - .leaf =3D leaf, - }, - }; - - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); -} - static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t= size, size_t granule) { @@ -2848,7 +2697,9 @@ static void arm_smmu_tlb_inv_page_nosync(struct iommu= _iotlb_gather *gather, static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size, size_t granule, void *cookie) { - arm_smmu_tlb_inv_range_domain(iova, size, granule, false, cookie); + struct arm_smmu_domain *smmu_domain =3D cookie; + + arm_smmu_domain_inv_range(smmu_domain, iova, size, granule, false); } =20 static const struct iommu_flush_ops arm_smmu_flush_ops =3D { @@ -4114,9 +3965,9 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *= domain, if (!gather->pgsize) return; =20 - arm_smmu_tlb_inv_range_domain(gather->start, - gather->end - gather->start + 1, - gather->pgsize, true, smmu_domain); + arm_smmu_domain_inv_range(smmu_domain, gather->start, + gather->end - gather->start + 1, + gather->pgsize, true); } =20 static phys_addr_t --=20 2.43.0