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Mon, 17 Nov 2025 13:47:12 -0800 (PST) Date: Mon, 17 Nov 2025 18:47:05 -0300 From: Geraldo Nascimento To: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley , Johan Jonker , Geraldo Nascimento , Dragan Simic Cc: linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/4] PCI: rockchip: limit RK3399 to 2.5 GT/s to prevent damage Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Shawn Lin from Rockchip has reiterated that there may be danger in using their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change from the default and drive at 2.5 GT/s only, even if the DT max-link-speed property is invalid or inexistent. This change is corroborated by RK3399 official datasheet [1], which says maximum link speed for this platform is 2.5 GT/s. [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet= _V2.1-20200323.pdf Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock= -chips.com/ Cc: stable@vger.kernel.org Reported-by: Dragan Simic Reported-by: Shawn Lin Reviewed-by: Dragan Simic Signed-off-by: Geraldo Nascimento Acked-by: Shawn Lin --- drivers/pci/controller/pcie-rockchip.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controlle= r/pcie-rockchip.c index 0f88da378805..992ccf4b139e 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchi= p) } =20 rockchip->link_gen =3D of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen =3D 2; + if (rockchip->link_gen < 0 || rockchip->link_gen > 2) { + rockchip->link_gen =3D 1; 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charset="utf-8" According to Rockchip sources, there is grave danger in enabling 5.0 GT/s speed for this core. Add a comment documenting that danger and discouraging end-users from forcing higher speed. Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock= -chips.com/ Cc: stable@vger.kernel.org Reported-by: Dragan Simic Reported-by: Shawn Lin Reviewed-by: Dragan Simic Signed-off-by: Geraldo Nascimento Acked-by: Shawn Lin --- drivers/pci/controller/pcie-rockchip-host.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index ee1822ca01db..0af550277ee5 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -332,6 +332,9 @@ static int rockchip_pcie_host_init_port(struct rockchip= _pcie *rockchip) /* * Enable retrain for gen2. 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Mon, 17 Nov 2025 13:47:51 -0800 (PST) Received: from geday ([2804:7f2:800b:a807::dead:c001]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3e8522b268fsm6350105fac.18.2025.11.17.13.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 13:47:50 -0800 (PST) Date: Mon, 17 Nov 2025 18:47:43 -0300 From: Geraldo Nascimento To: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley , Johan Jonker , Geraldo Nascimento , Dragan Simic Cc: linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: rockchip: remove dangerous max-link-speed from helios64 Message-ID: <43bb639c120f599106fca2deee6c6599b2692c5c.1763415706.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Shawn Lin from Rockchip strongly discourages attempts to use their RK3399 PCIe core at 5.0 GT/s speed, citing concerns about catastrophic failures that may happen. Even if the odds are low, drop from last user of this non-default property for the RK3399 platform, helios64 board dts. Fixes: 755fff528b1b ("arm64: dts: rockchip: add variables for pcie completi= on to helios64") Link: https://lore.kernel.org/all/e8524bf8-a90c-423f-8a58-9ef05a3db1dd@rock= -chips.com/ Cc: stable@vger.kernel.org Reported-by: Shawn Lin Reviewed-by: Dragan Simic Signed-off-by: Geraldo Nascimento Acked-by: Shawn Lin --- arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/= arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index e7d4a2f9a95e..78a7775c3b22 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -424,7 +424,6 @@ &pcie_phy { =20 &pcie0 { ep-gpios =3D <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - max-link-speed =3D <2>; num-lanes =3D <2>; pinctrl-names =3D "default"; status =3D "okay"; --=20 2.49.0 From nobody Tue Dec 2 02:52:31 2025 Received: from mail-oo1-f46.google.com (mail-oo1-f46.google.com [209.85.161.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44EFF2417D1 for ; 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Mon, 17 Nov 2025 13:48:06 -0800 (PST) Received: from geday ([2804:7f2:800b:a807::dead:c001]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c73a283b3asm5938805a34.4.2025.11.17.13.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 13:48:05 -0800 (PST) Date: Mon, 17 Nov 2025 18:47:59 -0300 From: Geraldo Nascimento To: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley , Johan Jonker , Geraldo Nascimento , Dragan Simic Cc: linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: rockchip: remove redundant max-link-speed from nanopi-r4s Message-ID: <6694456a735844177c897581f785cc00c064c7d1.1763415706.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is already the default in rk3399-base.dtsi, remove redundant declaration from rk3399-nanopi-r4s.dtsi. Fixes: db792e9adbf8 ("rockchip: rk3399: Add support for FriendlyARM NanoPi = R4S") Cc: stable@vger.kernel.org Reported-by: Dragan Simic Reviewed-by: Dragan Simic Signed-off-by: Geraldo Nascimento Acked-by: Shawn Lin --- arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi index 8d94d9f91a5c..3a9a10f531bd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi @@ -71,7 +71,6 @@ &i2c4 { }; =20 &pcie0 { - max-link-speed =3D <1>; num-lanes =3D <1>; vpcie3v3-supply =3D <&vcc3v3_sys>; }; --=20 2.49.0