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Mon, 10 Nov 2025 21:13:13 -0800 From: Nicolin Chen To: , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v5 1/5] iommu: Lock group->mutex in iommu_deferred_attach() Date: Mon, 10 Nov 2025 21:12:51 -0800 Message-ID: <11b3ab833d717feb41ce23ae6ebdc3af13ea55a7.1762835355.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|SN7PR12MB7883:EE_ X-MS-Office365-Filtering-Correlation-Id: 967611e0-4ea0-45f8-0447-08de20e1097d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nrTeELvhBSRe2R2/trtVaVvZUgapDmtJzP6dI+2c4UGJEOkdzm9OY/tV974R?= =?us-ascii?Q?TT7Mhm9/qhrXJbGCMzTpKcjbshVpz2fZELH+G5tjlCcsCPXOg1zNJ6nTXtUI?= =?us-ascii?Q?nj2I/7g2fbcKCXwqCD4YxsC9clfoVjC3yXsr7naF0gQ2qK1UkYozeih25bwm?= =?us-ascii?Q?Oi59moPx5xpTGX2aFNBHF27e5V8MtWQumwIrOzfAq9wk/qX3YBPTs07aD4fO?= =?us-ascii?Q?YD2FKDsV0Zl5qVXLlXOuS2QmeWLmzJmdNelAYTs2UUxPl8ppTat/fu1mvNFr?= =?us-ascii?Q?orQS3zXoMW6KCJ28L/++oqUDn7lbTmHIfU8GR996zZApLIB61G/7asw1PPJl?= =?us-ascii?Q?IKLX4gHDwJKFfjIglybr/T02yo7RUeH3uUowJh0ziAweDUMKEhtwtOje7iPn?= =?us-ascii?Q?NJ3xjHNYdEw4m79dgDuPhhoArBuhCMCyFQCZtwNOXw1GXe5DxBJeA/rxKtpM?= =?us-ascii?Q?bjInTvo93lx+qIy1VODFwfv5SA9SK00BQZ2A7Zp0Ys2Ry4lC05rg7a59m1ju?= =?us-ascii?Q?/jwAyQWAfyQGtng093XH+MkCO7a83nv7nECzKZjqi1/yKh1BdVTurmkDfy+o?= =?us-ascii?Q?nQQiNdeSPMLlBx970vCGV/CQOvYqgxjt523PR+5yunSIzu09ZT8DJLz+vDPx?= =?us-ascii?Q?8mhIy1BoPpIzgMrYbzJVzwGI8UsFbGgC+NXz/VVmJHpYW8FtEOhe1BI2Wqha?= =?us-ascii?Q?YrPmdi6J5i9oNL9KJsizkfkVl79GpxT+1A4kp1CivXx0W/rEAkwnrUXJqyOt?= =?us-ascii?Q?XcuqwWKKcsUDuxzNzXJlYkNFblYJH8sFYkP+bCIVol9ety68UnCxpSu3abDy?= =?us-ascii?Q?oR95UGdFoJgtPLcR8TORoi0/A7SYo1b15ztAQn1Hx7R0oJPQsw8pFCUiS2LY?= =?us-ascii?Q?D4NAkUwkvnp5BDhPpUtyn79YMSBNVY5XfihIpk9YAf4l/YOpB6Mh9dDcuT+d?= =?us-ascii?Q?cPtOKE2oFXp2dbuy+p2RqwORIh42mVxlMesL0gDP4feWb83B0P37P53Xd8QJ?= =?us-ascii?Q?s2hfC91ON6QtqGpnv8H8mtyBkJm7FIyhNgzXrafmE0gKTYBWU+jxaTCOZrpM?= =?us-ascii?Q?X/KP11LD1IBiR/u5XlQx+iNXUVFfnHK/VjLPTTeItEeSoEKzxeezPTXrmjuU?= =?us-ascii?Q?LJlhuZQGyfwrJFJHk4nOXtLmVX33PLaF0iGqPbzQ+MDvXamhRGzOfvjU2w6a?= =?us-ascii?Q?DqwBE5hiwuxhYeH6JUQS9E6V0aX1Jmq7S8VJQBUdBjNdwLlehp234hxuwwSF?= =?us-ascii?Q?lsYD0lzWbqSSkqoB+Tu1LxgpkgQF1Bc+wNF93zFAuydPxKfc1UetRzB3KlwT?= =?us-ascii?Q?ubvpl1h0QWB+VZukB9Zik0Fa2Axz6UTAHWPueycBPc/wS5GTfxULhn4vsWWj?= =?us-ascii?Q?hM7A3rHoIqLYw+d/bu4xjb/qG33cnTGUCRrBiLBpPr7w03l3+6lW0HpdCzjW?= =?us-ascii?Q?LRydRILzaIq0L5vUbkS+80KJeEXanTTskJEY2bcpTS2yHJBES/PntFVSZ+hj?= =?us-ascii?Q?NOKyiHBzJZGs8NtpcPnHbbwp2udymVSiX0M8HSsOG7NJRewCvhSQzjYRewL+?= =?us-ascii?Q?TEJ76WClS1nv9svvnCg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 05:13:23.0674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 967611e0-4ea0-45f8-0447-08de20e1097d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7883 Content-Type: text/plain; charset="utf-8" The iommu_deferred_attach() function invokes __iommu_attach_device(), but doesn't hold the group->mutex like other __iommu_attach_device() callers. Though there is no pratical bug being triggered so far, it would be better to apply the same locking to this __iommu_attach_device(), since the IOMMU drivers nowaday are more aware of the group->mutex -- some of them use the iommu_group_mutex_assert() function that could be potentially in the path of an attach_dev callback function invoked by the __iommu_attach_device(). Worth mentioning that the iommu_deferred_attach() will soon need to check group->resetting_domain that must be locked also. Thus, grab the mutex to guard __iommu_attach_device() like other callers. Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 2ca990dfbb884..170e522b5bda4 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2185,10 +2185,17 @@ EXPORT_SYMBOL_GPL(iommu_attach_device); =20 int iommu_deferred_attach(struct device *dev, struct iommu_domain *domain) { - if (dev->iommu && dev->iommu->attach_deferred) - return __iommu_attach_device(domain, dev, NULL); + /* + * This is called on the dma mapping fast path so avoid locking. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 05:13:25.0859 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38564999-91bb-4563-4cba-08de20e10aac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5867 Content-Type: text/plain; charset="utf-8" This function can only be called on the default_domain. Trivally pass it in. In all three existing cases, the default domain was just attached to the device. This avoids iommu_setup_dma_ops() calling iommu_get_domain_for_dev() the that will be used by external callers. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/dma-iommu.h | 5 +++-- drivers/iommu/dma-iommu.c | 4 +--- drivers/iommu/iommu.c | 6 +++--- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index eca201c1f9639..040d002525632 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -9,7 +9,7 @@ =20 #ifdef CONFIG_IOMMU_DMA =20 -void iommu_setup_dma_ops(struct device *dev); +void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain); =20 int iommu_get_dma_cookie(struct iommu_domain *domain); void iommu_put_dma_cookie(struct iommu_domain *domain); @@ -26,7 +26,8 @@ extern bool iommu_dma_forcedac; =20 #else /* CONFIG_IOMMU_DMA */ =20 -static inline void iommu_setup_dma_ops(struct device *dev) +static inline void iommu_setup_dma_ops(struct device *dev, + struct iommu_domain *domain) { } =20 diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 7944a3af4545e..e8ffb50c66dbf 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2096,10 +2096,8 @@ void dma_iova_destroy(struct device *dev, struct dma= _iova_state *state, } EXPORT_SYMBOL_GPL(dma_iova_destroy); =20 -void iommu_setup_dma_ops(struct device *dev) +void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain) { - struct iommu_domain *domain =3D iommu_get_domain_for_dev(dev); - if (dev_is_pci(dev)) dev->iommu->pci_32bit_workaround =3D !iommu_dma_forcedac; =20 diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 170e522b5bda4..1e322f87b1710 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -661,7 +661,7 @@ static int __iommu_probe_device(struct device *dev, str= uct list_head *group_list } =20 if (group->default_domain) - iommu_setup_dma_ops(dev); + iommu_setup_dma_ops(dev, group->default_domain); =20 mutex_unlock(&group->mutex); =20 @@ -1949,7 +1949,7 @@ static int bus_iommu_probe(const struct bus_type *bus) return ret; } for_each_group_device(group, gdev) - iommu_setup_dma_ops(gdev->dev); + iommu_setup_dma_ops(gdev->dev, group->default_domain); mutex_unlock(&group->mutex); =20 /* @@ -3155,7 +3155,7 @@ static ssize_t iommu_group_store_type(struct iommu_gr= oup *group, =20 /* Make sure dma_ops is appropriatley set */ for_each_group_device(group, gdev) - iommu_setup_dma_ops(gdev->dev); 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Mon, 10 Nov 2025 21:13:16 -0800 From: Nicolin Chen To: , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v5 3/5] iommu: Add iommu_driver_get_domain_for_dev() helper Date: Mon, 10 Nov 2025 21:12:53 -0800 Message-ID: <0303739735f3f49bcebc244804e9eeb82b1c41dc.1762835355.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37A:EE_|DS7PR12MB5744:EE_ X-MS-Office365-Filtering-Correlation-Id: 87e8d29e-3df7-43a9-757c-08de20e10c9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FotMdHZeDkXht+OmWkhBQprgOoBTWD9UYDgMBXTp6QYOr+E+l/BTHZ0rqU3b?= =?us-ascii?Q?TAKluIsskF0RKYVUR75WaxQ1X12C7RpuANLUAUkaCMKGX13K9kc48Y52FJEp?= =?us-ascii?Q?n2rVv8ZkwYA0hR9ggapGKpgZnWaKM8PZP4A78UiIa9o/q4oHeY0ZFBzDPavv?= =?us-ascii?Q?Ng7Qb+kSNpHl+xx++4yuFfqxyd+W4/bFvpgiDjp1n98dzDqgUYWFcnqpGGxA?= =?us-ascii?Q?do4FEsUu7FeOVprepuMuNaJeVAOJHolkM1biFDe9bH1I2o/IOKDf2vkz3ysM?= =?us-ascii?Q?U1mC3g2G+RfrwR9A2XgT/V5Whx356EizxBgv/Bnm7AonoGaSD0mS4bSVSu5P?= =?us-ascii?Q?Bs18r+bFAs5BFOqTjP94eY/M+x+F7rt9puqpzCRdxJSDStYrJMVDDe1C695d?= =?us-ascii?Q?B9fL/8b+EDJgLFiSTABLPSS06q7SJSQEIHexJH0yPIwwqsbcZm5YnyKiNIpr?= =?us-ascii?Q?bRVeysLvh5fqnBvCIr1mY15fJISRUTlcFQkGGLWFstMFzdRUn0+csAkvCShZ?= =?us-ascii?Q?hmmL+eU6Ra1znitWTJBxWuYXqsr5TxIoBVIY5b5asuce2/cMB2o6VBUcOE3X?= =?us-ascii?Q?UBWORUb+Sg8TFk1e1b6+3N4WoOrXGSXLhpMqaKi5Bw5mlQaf07yTCE7j4GD2?= =?us-ascii?Q?XOvqe+oFqFihYMySrmWW89umMpLtMIayJ1yCQprdZbWMvT34ni9YafK+uVKK?= =?us-ascii?Q?bta26wQ+JcrGgFee7qbIXcVMmKCpI3fgFOWf7sdiLNDJpE6jgx+iqPc+FQUE?= =?us-ascii?Q?aEeSTWPklw05nz9mg91LgdvyuCNaZOymjYd310mmnpA2cJz7YgHRbWLKO7fz?= =?us-ascii?Q?xak4Xmc3kiyGyUrmB+G1rMIUnEJxDuoBH0BgZygP7bT65LbsvrFtjA8BhUmR?= =?us-ascii?Q?/TDEtSGDJh+M3jlVZznOhTMytwhBgZQR80hr8tbcurUNrXzDj7diY0H2d9SV?= =?us-ascii?Q?7b3jjFJeOe0a+ZKOSG62TEbCm+t1tsQvlfWrjRg+X17d/DfT5peJ3hNEWnxX?= =?us-ascii?Q?Vj2QxIcYgQQjOk4mpvnCKvQmx4/PdGl8xNvXs+phBQhwq2fx/Ym9iExdlb5I?= =?us-ascii?Q?v2i/ldos+TFsZcKvDuIPdObD+zly4DK5GQ4u3ofcmnsC6OsP13JvS64GPjT1?= =?us-ascii?Q?YttosLOPmb9AY4LKwLg4rE64PKhi9wNkIka+Q/uGhFuNqOhH5R1ZRefIm+fs?= =?us-ascii?Q?4qE4x891qBgkN3QMNz+hQmwvTTgna2ARzaWzkXGCQj3xwX0Ntmb51/T7yZlC?= =?us-ascii?Q?3Qvwxzai0D0r39BJqcuNWD93cr/qeXVSg47Uh/50femz90fEjAwqAcWRh7Gr?= =?us-ascii?Q?zvLuecJHEqPE+nXy5+Z6D1jV3VxpHt+Zucyb0MBsg0qkV2y3DqupIfN9pOwo?= =?us-ascii?Q?jVJUAGNg8eF8MDd/auYRh3KYn9X6obh6sgdjItdARNn2SeocNUVDye0TJAsO?= =?us-ascii?Q?P5vSW20esDesvT61FSy6z02n161h9fEg3i/8trbiJm9Q2aSn4EsCJWC4TOfk?= =?us-ascii?Q?r3seC5xm/o2iPFeP9dQMuiRM/utkeBAOzplBvnk432M/GDBMreLOMMteFqD+?= =?us-ascii?Q?XIKu68F8sEtUqDOzNSk=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 05:13:28.3185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87e8d29e-3df7-43a9-757c-08de20e10c9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5744 Content-Type: text/plain; charset="utf-8" There is a need to stage a resetting PCI device to temporally the blocked domain and then attach back to its previously attached domain after reset. This can be simply done by keeping the "previously attached domain" in the iommu_group->domain pointer while adding an iommu_group->resetting_domain, which gives troubles to IOMMU drivers using the iommu_get_domain_for_dev() for a device's physical domain in order to program IOMMU hardware. And in such for-driver use cases, the iommu_group->mutex must be held, so it doesn't fit in external callers that don't hold the iommu_group->mutex. Introduce a new iommu_driver_get_domain_for_dev() helper, exclusively for driver use cases that hold the iommu_group->mutex, to separate from those external use cases. Add a lockdep_assert_not_held to the existing iommu_get_domain_for_dev() and highlight that in a kdoc. Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 5 ++-- drivers/iommu/iommu.c | 28 +++++++++++++++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 801b2bd9e8d49..a42a2d1d7a0b7 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -910,6 +910,7 @@ extern int iommu_attach_device(struct iommu_domain *dom= ain, extern void iommu_detach_device(struct iommu_domain *domain, struct device *dev); extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); +struct iommu_domain *iommu_driver_get_domain_for_dev(struct device *dev); extern struct iommu_domain *iommu_get_dma_domain(struct device *dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot, gfp_t gfp); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a33fbd12a0dd9..412d1a9b31275 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3125,7 +3125,8 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old) { - struct iommu_domain *sid_domain =3D iommu_get_domain_for_dev(master->dev); + struct iommu_domain *sid_domain =3D + iommu_driver_get_domain_for_dev(master->dev); struct arm_smmu_attach_state state =3D { .master =3D master, .ssid =3D pasid, @@ -3191,7 +3192,7 @@ static int arm_smmu_blocking_set_dev_pasid(struct iom= mu_domain *new_domain, */ if (!arm_smmu_ssids_in_use(&master->cd_table)) { struct iommu_domain *sid_domain =3D - iommu_get_domain_for_dev(master->dev); + iommu_driver_get_domain_for_dev(master->dev); =20 if (sid_domain->type =3D=3D IOMMU_DOMAIN_IDENTITY || sid_domain->type =3D=3D IOMMU_DOMAIN_BLOCKED) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 1e322f87b1710..1f4d6ca0937bc 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2217,6 +2217,15 @@ void iommu_detach_device(struct iommu_domain *domain= , struct device *dev) } EXPORT_SYMBOL_GPL(iommu_detach_device); =20 +/** + * iommu_get_domain_for_dev() - Return the DMA API domain pointer + * @dev - Device to query + * + * This function can be called within a driver bound to dev. The returned + * pointer is valid for the lifetime of the bound driver. + * + * It should not be called by drivers with driver_managed_dma =3D true. + */ struct iommu_domain *iommu_get_domain_for_dev(struct device *dev) { /* Caller must be a probed driver on dev */ @@ -2225,10 +2234,29 @@ struct iommu_domain *iommu_get_domain_for_dev(struc= t device *dev) if (!group) return NULL; =20 + lockdep_assert_not_held(&group->mutex); + return group->domain; } EXPORT_SYMBOL_GPL(iommu_get_domain_for_dev); =20 +/** + * iommu_driver_get_domain_for_dev() - Return the driver-level domain poin= ter + * @dev - Device to query + * + * This function can be called by an iommu driver that wants to get the ph= ysical + * domain within an iommu callback function where group->mutex is held. + */ +struct iommu_domain *iommu_driver_get_domain_for_dev(struct device *dev) +{ + struct iommu_group *group =3D dev->iommu_group; + + lockdep_assert_held(&group->mutex); + + return group->domain; +} +EXPORT_SYMBOL_GPL(iommu_driver_get_domain_for_dev); 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Mon, 10 Nov 2025 21:13:20 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 10 Nov 2025 21:13:19 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 10 Nov 2025 21:13:18 -0800 From: Nicolin Chen To: , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v5 4/5] iommu: Introduce iommu_dev_reset_prepare() and iommu_dev_reset_done() Date: Mon, 10 Nov 2025 21:12:54 -0800 Message-ID: <28af027371a981a2b4154633e12cdb1e5a11da4a.1762835355.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|CH3PR12MB8307:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ccbabbc-b027-408e-93ec-08de20e10d3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 05:13:29.3529 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ccbabbc-b027-408e-93ec-08de20e10d3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8307 Content-Type: text/plain; charset="utf-8" PCIe permits a device to ignore ATS invalidation TLPs, while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out. E.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The OS should do something to mitigate this as we do not want production systems to be reporting critical ATS failures, especially in a hypervisor environment. Broadly, OS could arrange to ignore the timeouts, block page table mutations to prevent invalidations, or disable and block ATS. The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. Provide a callback from the PCI subsystem that will enclose the reset and have the iommu core temporarily change all the attached domain to BLOCKED. After attaching a BLOCKED domain, IOMMU hardware would fence any incoming ATS queries. And IOMMU drivers should also synchronously stop issuing new ATS invalidations and wait for all ATS invalidations to complete. This can avoid any ATS invaliation timeouts. However, if there is a domain attachment/replacement happening during an ongoing reset, ATS routines may be re-activated between the two function calls. So, introduce a new resetting_domain in the iommu_group structure to reject any concurrent attach_dev/set_dev_pasid call during a reset for a concern of compatibility failure. Since this changes the behavior of an attach operation, update the uAPI accordingly. Note that there are two corner cases: 1. Devices in the same iommu_group Since an attachment is always per iommu_group, disallowing one device to switch domains (or HWPTs in iommufd) would have to disallow others in the same iommu_group to switch domains as well. So, play safe by preventing a shared iommu_group from going through the iommu reset. 2. SRIOV devices that its PF is resetting while its VF isn't In such case, the VF itself is already broken. So, there is no point in preventing PF from going through the iommu reset. Reviewed-by: Lu Baolu Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 12 +++ include/uapi/linux/vfio.h | 3 + drivers/iommu/iommu.c | 183 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index a42a2d1d7a0b7..25a2c2b00c9f7 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1169,6 +1169,9 @@ void dev_iommu_priv_set(struct device *dev, void *pri= v); extern struct mutex iommu_probe_device_lock; int iommu_probe_device(struct device *dev); =20 +int iommu_dev_reset_prepare(struct device *dev); +void iommu_dev_reset_done(struct device *dev); + int iommu_device_use_default_domain(struct device *dev); void iommu_device_unuse_default_domain(struct device *dev); =20 @@ -1453,6 +1456,15 @@ static inline int iommu_fwspec_add_ids(struct device= *dev, u32 *ids, return -ENODEV; } =20 +static inline int iommu_dev_reset_prepare(struct device *dev) +{ + return 0; +} + +static inline void iommu_dev_reset_done(struct device *dev) +{ +} + static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) { return NULL; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 75100bf009baf..6cc9d2709d13a 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -963,6 +963,9 @@ struct vfio_device_bind_iommufd { * hwpt corresponding to the given pt_id. * * Return: 0 on success, -errno on failure. + * + * When a device gets reset, any attach will be rejected with -EBUSY until= that + * reset routine finishes. */ struct vfio_device_attach_iommufd_pt { __u32 argsz; diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 1f4d6ca0937bc..74b9f2bfc0458 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -61,6 +61,11 @@ struct iommu_group { int id; struct iommu_domain *default_domain; struct iommu_domain *blocking_domain; + /* + * During a group device reset, @resetting_domain points to the physical + * domain, while @domain points to the attached domain before the reset. + */ + struct iommu_domain *resetting_domain; struct iommu_domain *domain; struct list_head entry; unsigned int owner_cnt; @@ -2195,6 +2200,12 @@ int iommu_deferred_attach(struct device *dev, struct= iommu_domain *domain) =20 guard(mutex)(&dev->iommu_group->mutex); =20 + /* + * This is a concurrent attach while a group device is resetting. Reject + * it until iommu_dev_reset_done() attaches the device to group->domain. + */ + if (dev->iommu_group->resetting_domain) + return -EBUSY; return __iommu_attach_device(domain, dev, NULL); } =20 @@ -2253,6 +2264,16 @@ struct iommu_domain *iommu_driver_get_domain_for_dev= (struct device *dev) =20 lockdep_assert_held(&group->mutex); =20 + /* + * Driver handles the low-level __iommu_attach_device(), including the + * one invoked by iommu_dev_reset_done(), in which case the driver must + * get the resetting_domain over group->domain caching the one prior to + * iommu_dev_reset_prepare(), so that it wouldn't end up with attaching + * the device from group->domain (old) to group->domain (new). + */ + if (group->resetting_domain) + return group->resetting_domain; + return group->domain; } EXPORT_SYMBOL_GPL(iommu_driver_get_domain_for_dev); @@ -2409,6 +2430,13 @@ static int __iommu_group_set_domain_internal(struct = iommu_group *group, if (WARN_ON(!new_domain)) return -EINVAL; =20 + /* + * This is a concurrent attach while a group device is resetting. Reject + * it until iommu_dev_reset_done() attaches the device to group->domain. + */ + if (group->resetting_domain) + return -EBUSY; + /* * Changing the domain is done by calling attach_dev() on the new * domain. This switch does not have to be atomic and DMA can be @@ -3527,6 +3555,16 @@ int iommu_attach_device_pasid(struct iommu_domain *d= omain, return -EINVAL; =20 mutex_lock(&group->mutex); + + /* + * This is a concurrent attach while a group device is resetting. Reject + * it until iommu_dev_reset_done() attaches the device to group->domain. + */ + if (group->resetting_domain) { + ret =3D -EBUSY; + goto out_unlock; + } + for_each_group_device(group, device) { /* * Skip PASID validation for devices without PASID support @@ -3610,6 +3648,16 @@ int iommu_replace_device_pasid(struct iommu_domain *= domain, return -EINVAL; =20 mutex_lock(&group->mutex); + + /* + * This is a concurrent attach while a group device is resetting. Reject + * it until iommu_dev_reset_done() attaches the device to group->domain. + */ + if (group->resetting_domain) { + ret =3D -EBUSY; + goto out_unlock; + } + entry =3D iommu_make_pasid_array_entry(domain, handle); curr =3D xa_cmpxchg(&group->pasid_array, pasid, NULL, XA_ZERO_ENTRY, GFP_KERNEL); @@ -3867,6 +3915,141 @@ int iommu_replace_group_handle(struct iommu_group *= group, } EXPORT_SYMBOL_NS_GPL(iommu_replace_group_handle, "IOMMUFD_INTERNAL"); =20 +/** + * iommu_dev_reset_prepare() - Block IOMMU to prepare for a device reset + * @dev: device that is going to enter a reset routine + * + * When certain device is entering a reset routine, it wants to block any = IOMMU + * activity during the reset routine. This includes blocking any translati= on as + * well as cache invalidation (especially the device cache). + * + * This function attaches all RID/PASID of the device's to IOMMU_DOMAIN_BL= OCKED + * allowing any blocked-domain-supporting IOMMU driver to pause translatio= n and + * cahce invalidation, but leaves the software domain pointers intact so l= ater + * the iommu_dev_reset_done() can restore everything. + * + * Return: 0 on success or negative error code if the preparation failed. + * + * Caller must use iommu_dev_reset_prepare() and iommu_dev_reset_done() to= gether + * before/after the core-level reset routine, to unset the resetting_domai= n. + * + * These two functions are designed to be used by PCI reset functions that= would + * not invoke any racy iommu_release_device(), since PCI sysfs node gets r= emoved + * before it notifies with a BUS_NOTIFY_REMOVED_DEVICE. When using them in= other + * case, callers must ensure there will be no racy iommu_release_device() = call, + * which otherwise would UAF the dev->iommu_group pointer. + */ +int iommu_dev_reset_prepare(struct device *dev) +{ + struct iommu_group *group =3D dev->iommu_group; + unsigned long pasid; + void *entry; + int ret =3D 0; + + if (!dev_has_iommu(dev)) + return 0; + + guard(mutex)(&group->mutex); + + /* + * Once the resetting_domain is set, any concurrent attachment to this + * iommu_group will be rejected, which would break the attach routines + * of the sibling devices in the same iommu_group. So, skip this case. + */ + if (dev_is_pci(dev)) { + struct group_device *gdev; + + for_each_group_device(group, gdev) { + if (gdev->dev !=3D dev) + return 0; + } + } + + /* Re-entry is not allowed */ + if (WARN_ON(group->resetting_domain)) + return -EBUSY; + + ret =3D __iommu_group_alloc_blocking_domain(group); + if (ret) + return ret; + + /* Stage RID domain at blocking_domain while retaining group->domain */ + if (group->domain !=3D group->blocking_domain) { + ret =3D __iommu_attach_device(group->blocking_domain, dev, + group->domain); + if (ret) + return ret; + } + + /* + * Stage PASID domains at blocking_domain while retaining pasid_array. + * + * The pasid_array is mostly fenced by group->mutex, except one reader + * in iommu_attach_handle_get(), so it's safe to read without xa_lock. + */ + xa_for_each_start(&group->pasid_array, pasid, entry, 1) + iommu_remove_dev_pasid(dev, pasid, + pasid_array_entry_to_domain(entry)); + + group->resetting_domain =3D group->blocking_domain; + return ret; +} +EXPORT_SYMBOL_GPL(iommu_dev_reset_prepare); + +/** + * iommu_dev_reset_done() - Restore IOMMU after a device reset is finished + * @dev: device that has finished a reset routine + * + * When certain device has finished a reset routine, it wants to restore i= ts + * IOMMU activity, including new translation as well as cache invalidation= , by + * re-attaching all RID/PASID of the device's back to the domains retained= in + * the core-level structure. + * + * Caller must pair it with a successfully returned iommu_dev_reset_prepar= e(). + * + * Note that, although unlikely, there is a risk that re-attaching domains= might + * fail due to some unexpected happening like OOM. + */ +void iommu_dev_reset_done(struct device *dev) +{ + struct iommu_group *group =3D dev->iommu_group; + unsigned long pasid; + void *entry; + + if (!dev_has_iommu(dev)) + return; + + guard(mutex)(&group->mutex); + + /* iommu_dev_reset_prepare() was bypassed for the device */ + if (!group->resetting_domain) + return; + + /* iommu_dev_reset_prepare() was not successfully called */ + if (WARN_ON(!group->blocking_domain)) + return; + + /* Re-attach RID domain back to group->domain */ + if (group->domain !=3D group->blocking_domain) { + WARN_ON(__iommu_attach_device(group->domain, dev, + group->blocking_domain)); + } + + /* + * Re-attach PASID domains back to the domains retained in pasid_array. + * + * The pasid_array is mostly fenced by group->mutex, except one reader + * in iommu_attach_handle_get(), so it's safe to read without xa_lock. + */ + xa_for_each_start(&group->pasid_array, pasid, entry, 1) + WARN_ON(__iommu_set_group_pasid( + pasid_array_entry_to_domain(entry), group, pasid, + group->blocking_domain)); + + group->resetting_domain =3D NULL; +} +EXPORT_SYMBOL_GPL(iommu_dev_reset_done); + #if IS_ENABLED(CONFIG_IRQ_MSI_IOMMU) /** * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain --=20 2.43.0 From nobody Tue Nov 11 11:26:18 2025 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010058.outbound.protection.outlook.com [52.101.46.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F8B7330B17; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 05:13:31.3237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 279c5b1d-5a07-4932-4bfa-08de20e10e6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6871 Content-Type: text/plain; charset="utf-8" PCIe permits a device to ignore ATS invalidation TLPs, while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. Now iommu_dev_reset_prepare/done() helpers are introduced for this matter. Use them in all the existing reset functions, which will attach the device to an IOMMU_DOMAIN_BLOCKED during a reset, so as to allow IOMMU driver to: - invoke pci_disable_ats() and pci_enable_ats(), if necessary - wait for all ATS invalidations to complete - stop issuing new ATS invalidations - fence any incoming ATS queries Signed-off-by: Nicolin Chen --- drivers/pci/pci.h | 2 ++ drivers/pci/pci-acpi.c | 12 ++++++-- drivers/pci/pci.c | 68 ++++++++++++++++++++++++++++++++++++++---- drivers/pci/quirks.c | 18 ++++++++++- 4 files changed, 92 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b5..a29286dfd870c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -198,6 +198,8 @@ void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); int __pci_reset_bus(struct pci_bus *bus); +int pci_reset_iommu_prepare(struct pci_dev *dev); +void pci_reset_iommu_done(struct pci_dev *dev); =20 struct pci_cap_saved_data { u16 cap_nr; diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa0..60d29b183f2c2 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -971,6 +971,7 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { acpi_handle handle =3D ACPI_HANDLE(&dev->dev); + int ret =3D 0; =20 if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; @@ -978,12 +979,19 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool prob= e) if (probe) return 0; =20 + ret =3D pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { pci_warn(dev, "ACPI _RST failed\n"); - return -ENOTTY; + ret =3D -ENOTTY; } =20 - return 0; + pci_reset_iommu_done(dev); + return ret; } =20 bool acpi_pci_power_manageable(struct pci_dev *dev) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006cc..52461d952cbf1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +97,23 @@ bool pci_reset_supported(struct pci_dev *dev) return dev->reset_methods[0] !=3D 0; } =20 +/* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS be= fore + * initiating a reset. Notify the iommu driver that enabled ATS. + */ +int pci_reset_iommu_prepare(struct pci_dev *dev) +{ + if (pci_ats_supported(dev)) + return iommu_dev_reset_prepare(&dev->dev); + return 0; +} + +void pci_reset_iommu_done(struct pci_dev *dev) +{ + if (pci_ats_supported(dev)) + iommu_dev_reset_done(&dev->dev); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported =3D 1; #endif @@ -4478,13 +4497,22 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret =3D 0; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing func= tion level reset anyway\n"); =20 + /* Have to call it after waiting for pending DMA transaction */ + ret =3D pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4493,7 +4521,10 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); =20 - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_reset_iommu_done(dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); =20 @@ -4521,6 +4552,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); =20 static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret =3D 0; int pos; u8 cap; =20 @@ -4547,10 +4579,17 @@ static int pci_af_flr(struct pci_dev *dev, bool pro= be) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF f= unction level reset anyway\n"); =20 + /* Have to call it after waiting for pending DMA transaction */ + ret =3D pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4560,7 +4599,10 @@ static int pci_af_flr(struct pci_dev *dev, bool prob= e) */ msleep(100); =20 - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_reset_iommu_done(dev); + return ret; } =20 /** @@ -4581,6 +4623,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; + int ret; =20 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4595,6 +4638,12 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) if (dev->current_state !=3D PCI_D0) return -EINVAL; =20 + ret =3D pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + csr &=3D ~PCI_PM_CTRL_STATE_MASK; csr |=3D PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); @@ -4605,7 +4654,9 @@ static int pci_pm_reset(struct pci_dev *dev, bool pro= be) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); =20 - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + pci_reset_iommu_done(dev); + return ret; } =20 /** @@ -5060,6 +5111,12 @@ static int cxl_reset_bus_function(struct pci_dev *de= v, bool probe) if (rc) return -ENOTTY; =20 + rc =3D pci_reset_iommu_prepare(dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU\n"); + return rc; + } + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { val =3D reg; } else { @@ -5074,6 +5131,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev= , bool probe) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg); =20 + pci_reset_iommu_done(dev); return rc; } =20 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 214ed060ca1b3..891d9e5a97e93 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4226,6 +4226,22 @@ static const struct pci_dev_reset_methods pci_dev_re= set_methods[] =3D { { 0 } }; =20 +static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, + const struct pci_dev_reset_methods *i) +{ + int ret; + + ret =3D pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + ret =3D i->reset(dev, probe); + pci_reset_iommu_done(dev); + return ret; +} + /* * These device-specific reset methods are here rather than in a driver * because when a host assigns a device to a guest VM, the host may need @@ -4240,7 +4256,7 @@ int pci_dev_specific_reset(struct pci_dev *dev, bool = probe) i->vendor =3D=3D (u16)PCI_ANY_ID) && (i->device =3D=3D dev->device || i->device =3D=3D (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return __pci_dev_specific_reset(dev, probe, i); } =20 return -ENOTTY; --=20 2.43.0