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Sun, 19 Oct 2025 20:33:51 -0700 (PDT) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, unicorn_wang@outlook.com, conor+dt@kernel.org, rabenda.cn@gmail.com, inochiama@gmail.com, krzk+dt@kernel.org, mani@kernel.org, liujingqi@lanxincomputing.com, palmer@dabbelt.com, pjw@kernel.org, robh@kernel.org, tglx@linutronix.de, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 1/4] riscv: sophgo: dts: add PCIe controllers for SG2042 Date: Mon, 20 Oct 2025 11:33:43 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Acked-by: Manivannan Sadhasivam Signed-off-by: Inochi Amaoto Signed-off-by: Han Gao Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index c5e49709b308..85d8b89cf9fc 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -240,6 +240,94 @@ clkgen: clock-controller@7030012000 { #clock-cells =3D <1>; }; =20 + pcie_rc0: pcie@7060000000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <3>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000= >, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; 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charset="utf-8" From: Chen Wang Enable PCIe controllers for PioneerBox, which uses SG2042 SoC. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/ris= cv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index ef3a602172b1..c4d5f8d7d4ad 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -128,6 +128,18 @@ uart0-rx-pins { }; }; =20 +&pcie_rc0 { + status =3D "okay"; +}; + +&pcie_rc2 { + status =3D "okay"; +}; + +&pcie_rc3 { + status =3D "okay"; +}; + &sd { pinctrl-0 =3D <&sd_cfg>; pinctrl-names =3D "default"; --=20 2.34.1 From nobody Sat Feb 7 15:15:22 2026 Received: from mail-ot1-f51.google.com (mail-ot1-f51.google.com [209.85.210.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E59DF1C8606 for ; Mon, 20 Oct 2025 03:39:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Chen Wang Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board, which uses SG2042 SoC. Signed-off-by: Han Gao Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot= /dts/sophgo/sg2042-evb-v1.dts index 3320bc1dd2c6..a186d036cf36 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -164,6 +164,18 @@ phy0: phy@0 { }; }; =20 +&pcie_rc0 { + status =3D "okay"; +}; + +&pcie_rc1 { + status =3D "okay"; +}; + +&pcie_rc2 { + status =3D "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { --=20 2.34.1 From nobody Sat Feb 7 15:15:22 2026 Received: from mail-ot1-f53.google.com (mail-ot1-f53.google.com [209.85.210.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 122351EE02F for ; Mon, 20 Oct 2025 03:40:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 19 Oct 2025 20:40:16 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c28879e8d5sm2272678a34.5.2025.10.19.20.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Oct 2025 20:40:16 -0700 (PDT) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, unicorn_wang@outlook.com, conor+dt@kernel.org, rabenda.cn@gmail.com, inochiama@gmail.com, krzk+dt@kernel.org, mani@kernel.org, liujingqi@lanxincomputing.com, palmer@dabbelt.com, pjw@kernel.org, robh@kernel.org, tglx@linutronix.de, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 4/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Date: Mon, 20 Oct 2025 11:40:09 +0800 Message-Id: <50a753f9b8cbd5a90b5b2df737f87fc77a9b33a7.1760929111.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board, which uses SG2042 SoC. Signed-off-by: Han Gao Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot= /dts/sophgo/sg2042-evb-v2.dts index 46980e41b886..0cd0dc0f537c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -152,6 +152,18 @@ phy0: phy@0 { }; }; =20 +&pcie_rc0 { + status =3D "okay"; +}; + +&pcie_rc1 { + status =3D "okay"; +}; + +&pcie_rc2 { + status =3D "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { --=20 2.34.1