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charset="utf-8" Previously, the driver always used the amount of precision bits of differential input channels to provide the scale to mV. Though, differential and common-mode voltage channels have different amount of precision bits and the correct number of precision bits must be considered to get to a proper mV scale factor for each one. Use channel specific number of precision bits to provide the correct scale value for each channel. Fixes: de67f28abe58 ("iio: adc: ad4030: check scan_type for error") Fixes: 949abd1ca5a4 ("iio: adc: ad4030: add averaging support") Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- drivers/iio/adc/ad4030.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 1bc2f9a22470..d8bee6a4215a 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -385,7 +385,7 @@ static int ad4030_get_chan_scale(struct iio_dev *indio_= dev, struct ad4030_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; =20 - scan_type =3D iio_get_current_scan_type(indio_dev, st->chip->channels); + scan_type =3D iio_get_current_scan_type(indio_dev, chan); if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 --=20 2.50.1 From nobody Thu Oct 2 09:16:53 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86DEA319601; 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charset="utf-8" AD4030 and similar devices all connect to the system as SPI peripherals. Reference spi-peripheral-props so common SPI peripheral can be used from ad4030 dt-binding. Signed-off-by: Marcelo Schmitt Acked-by: Conor Dooley --- Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 54e7349317b7..a8fee4062d0e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -20,6 +20,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf =20 +$ref: /schemas/spi/spi-peripheral-props.yaml# + properties: compatible: enum: --=20 2.50.1 From nobody Thu Oct 2 09:16:53 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2626D25B31B; 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charset="utf-8" Document double PWM setup SPI offload wiring schema. Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- Change log v1 -> v2 - Swapped PWM numbering. - Expanded double PWM description and capture zone description. Documentation/iio/ad4030.rst | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst index b57424b650a8..9501d3fee9bb 100644 --- a/Documentation/iio/ad4030.rst +++ b/Documentation/iio/ad4030.rst @@ -92,6 +92,41 @@ Interleaved mode In this mode, both channels conversion results are bit interleaved one SDO= line. As such the wiring is the same as `One lane mode`_. =20 +SPI offload wiring +^^^^^^^^^^^^^^^^^^ + +.. code-block:: + + +-------------+ +-------------+ + | CNV |<-----+--| GPIO | + | | +--| PWM0 | + | | | | + | | +--| PWM1 | + | | | +-------------+ + | | +->| TRIGGER | + | CS |<--------| CS | + | | | | + | ADC | | SPI | + | | | | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | SCLK |<--------| SCLK | + +-------------+ +-------------+ + +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are require= d. +The ``pwms`` property specifies the PWM that is connected to the ADC CNV p= in. +The SPI offload will have a ``trigger-sources`` property to indicate the S= PI +offload (PWM) trigger source. For AD4030 and similar ADCs, there are two +possible data transfer zones for sample N. One of them (zone 1) starts aft= er the +data conversion for sample N is complete while the other one (zone 2) star= ts 9.8 +nanoseconds after the rising edge of CNV for sample N + 1. + +The configuration depicted in the above ASCII art is intended to perform d= ata +transfer in zone 2. To achieve high sample rates while meeting ADC timing +requirements, an offset is added between the rising edges of PWM0 and PWM1= to +delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. 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charset="utf-8" In setups designed for high speed data rate capture, a PWM is used to generate the CNV signal that issues data captures from the ADC. Document the use of a PWM for AD4030 and similar devices. Signed-off-by: Marcelo Schmitt Acked-by: Conor Dooley Reviewed-by: David Lechner --- Change log v1 -> v2 - Dropped pwm-names since only one PWM signal is directly requested by the = ADC. Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index a8fee4062d0e..564b6f67a96e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -64,6 +64,10 @@ properties: The Reset Input (/RST). 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charset="utf-8" Use BIT macro to make the list of average modes more readable. Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/linux-iio/CAHp75Vfu-C3Hd0ZXTj4rxEgRe_O84cfo6j= iRCPFxZJnYrvROWQ@mail.gmail.com/ Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4030.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index d8bee6a4215a..aa0e27321869 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -233,9 +233,11 @@ struct ad4030_state { } =20 static const int ad4030_average_modes[] =3D { - 1, 2, 4, 8, 16, 32, 64, 128, - 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, - 65536, + BIT(0), /* No averaging/oversampling */ + BIT(1), BIT(2), BIT(3), BIT(4), /* 2 to 16 */ + BIT(5), BIT(6), BIT(7), BIT(8), /* 32 to 256 */ + BIT(9), BIT(10), BIT(11), BIT(12), /* 512 to 4096 */ + BIT(13), BIT(14), BIT(15), BIT(16), /* 8192 to 65536 */ }; =20 static int ad4030_enter_config_mode(struct ad4030_state *st) --=20 2.50.1 From nobody Thu Oct 2 09:16:53 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45C231B109; 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charset="utf-8" AD4030 and similar ADCs can capture data at sample rates up to 2 mega samples per second (MSPS). Not all SPI controllers are able to achieve such high throughputs and even when the controller is fast enough to run transfers at the required speed, it may be costly to the CPU to handle transfer data at such high sample rates. Add SPI offload support for AD4030 and similar ADCs to enable data capture at maximum sample rates. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Co-developed-by: Nuno Sa Signed-off-by: Nuno Sa Co-developed-by: Trevor Gamblin Signed-off-by: Trevor Gamblin Co-developed-by: Axel Haslam Signed-off-by: Axel Haslam Signed-off-by: Marcelo Schmitt --- Most of the code for SPI offload support is based on work from Sergiu Cuciu= rean, Nuno Sa, Axel Haslam, and Trevor Gamblin. Thus, this patch comes with many co-developed-by tags. I also draw inspiration from other drivers supporting= SPI offload, many of them written by David Lechner. Change log v1 -> v2 - Dropped all clock-modes and DDR related stuff for now as those will requi= re further changes to the SPI subsystem or to SPI controller drivers. - Update the modes register with proper output data mode bits when sample averaging (oversampling_ratio) is set. - Lock on device state mutex before updating oversampling and sampling freq= uency. - Made sampling_frequency shared by all channels. - Better checking the requested sampling frequency is valid. - Adjusted to SPI offload data capture preparation and stop procedures. - Error out if try to get/set sampling frequency without offload trigger. - Depend on PWM so build always succeed. - Drop unmatched/unbalanced call to iio_device_release_direct(). - No longer shadowing error codes. Suggestions to v1 that I did not comply to: [SPI] > I would be tempted to put the loop check here [in drivers/spi/spi-offload= -trigger-pwm.c]: >=20 > offload_offset_ns =3D periodic->offset_ns; >=20 > do { > wf.offset_ns =3D offload_offset_ns; > ret =3D pwm_round_waveform_might_sleep(st->pwm, &wf); > if (ret) > return ret; > offload_offset_ns +=3D 10; >=20 > } while (wf.offset_ns < periodic->offset_ns); >=20 > wf.duty_offset_ns =3D periodic->offset_ns; >=20 > instead of in the ADC driver so that all future callers don't have to > repeat this. Not sure implementing the PWM trigger phase approximation/rounding/setup wi= thin spi-offload-trigger-pwm is actually desirable. The PWM phase approximation/rounding/setup done in AD4030 iterates over the configuration= of a second PWM (the PWM connected to the CNV pin). I haven't seen any other dev= ice that would use such double PWM setup schema so pushing an additional argume= nt to spi_offload_trigger_pwm_validate() doesn't seem worth it. [IIO] > Why using slower speed for offload? Looks like it's the same max speed for both register access and data sample. So, just reusing the existing define for the max transfer speed. drivers/iio/adc/Kconfig | 3 + drivers/iio/adc/ad4030.c | 485 +++++++++++++++++++++++++++++++++++---- 2 files changed, 445 insertions(+), 43 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58a14e6833f6..2a44fcaccf54 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -60,8 +60,11 @@ config AD4030 tristate "Analog Devices AD4030 ADC Driver" depends on SPI depends on GPIOLIB + depends on PWM select REGMAP select IIO_BUFFER + select IIO_BUFFER_DMA + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER help Say yes here to build support for Analog Devices AD4030 and AD4630 high= speed diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index aa0e27321869..52805c779934 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -14,15 +14,25 @@ */ =20 #include +#include #include +#include +#include #include #include #include +#include +#include +#include +#include +#include #include #include +#include #include #include #include +#include =20 #define AD4030_REG_INTERFACE_CONFIG_A 0x00 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) @@ -111,6 +121,8 @@ #define AD4632_TCYC_NS 2000 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) #define AD4030_TRESET_COM_DELAY_MS 750 +/* Datasheet says 9.8ns, so use the closest integer value */ +#define AD4030_TQUIET_CNV_DELAY_NS 10 =20 enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, @@ -136,11 +148,13 @@ struct ad4030_chip_info { const char *name; const unsigned long *available_masks; const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; + const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; + unsigned int max_sample_rate_hz; }; =20 struct ad4030_state { @@ -153,6 +167,15 @@ struct ad4030_state { int offset_avail[3]; unsigned int avg_log2; enum ad4030_out_mode mode; + struct mutex lock; /* Protect read-modify-write and multi write sequences= */ + /* Offload sampling */ + struct spi_transfer offload_xfer; + struct spi_message offload_msg; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger_config offload_trigger_config; + struct pwm_device *cnv_trigger; + struct pwm_waveform cnv_wf; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -209,8 +232,9 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define AD4030_CHAN_DIFF(_idx, _scan_type) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ .info_mask_shared_by_all =3D \ + (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -232,6 +256,12 @@ struct ad4030_state { .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +#define AD4030_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + +#define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + static const int ad4030_average_modes[] =3D { BIT(0), /* No averaging/oversampling */ BIT(1), BIT(2), BIT(3), BIT(4), /* 2 to 16 */ @@ -240,6 +270,11 @@ static const int ad4030_average_modes[] =3D { BIT(13), BIT(14), BIT(15), BIT(16), /* 8192 to 65536 */ }; =20 +static const struct spi_offload_config ad4030_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + static int ad4030_enter_config_mode(struct ad4030_state *st) { st->tx_data[0] =3D AD4030_REG_ACCESS; @@ -453,6 +488,106 @@ static int ad4030_get_chan_calibbias(struct iio_dev *= indio_dev, } } =20 +static void ad4030_get_sampling_freq(struct ad4030_state *st, int *freq) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + + /* + * Conversion data is fetched from the device when the offload transfer + * is triggered. Thus, provide the SPI offload trigger frequency as the + * sampling frequency. + */ + *freq =3D config->periodic.frequency_hz; +} + +static int __ad4030_set_sampling_freq(struct ad4030_state *st, + unsigned int freq, unsigned int avg_log2) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + struct pwm_waveform cnv_wf =3D { }; + u64 target =3D AD4030_TCNVH_NS; + u64 offload_period_ns; + u64 offload_offset_ns; + int ret; + + /* + * When averaging/oversampling over N samples, we fire the offload + * trigger once at every N pulses of the CNV signal. Conversely, the CNV + * signal needs to be N times faster than the offload trigger. Take that + * into account to correctly re-evaluate both the PWM waveform connected + * to CNV and the SPI offload trigger. + */ + if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) + freq <<=3D avg_log2; + + cnv_wf.period_length_ns =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq); + /* + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the + * rounded PWM's value is less than 10, increase the target value by 10 + * and attempt to round the waveform again, until the value is at least + * 10 ns. Use a separate variable to represent the target in case the + * rounding is severe enough to keep putting the first few results under + * the minimum 10ns condition checked by the while loop. + */ + do { + cnv_wf.duty_length_ns =3D target; + ret =3D pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); + if (ret) + return ret; + target +=3D AD4030_TCNVH_NS; + } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS); + + if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX)) + return -EINVAL; + + offload_period_ns =3D cnv_wf.period_length_ns; + if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) + offload_period_ns <<=3D avg_log2; + + config->periodic.frequency_hz =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, + offload_period_ns); + + /* + * The hardware does the capture on zone 2 (when SPI trigger PWM + * is used). This means that the SPI trigger signal should happen at + * tsync + tquiet_con_delay being tsync the conversion signal period + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. + * + * The PWM waveform API only supports nanosecond resolution right now, + * so round this setting to the closest available value. + */ + offload_offset_ns =3D AD4030_TQUIET_CNV_DELAY_NS; + do { + config->periodic.offset_ns =3D offload_offset_ns; + ret =3D spi_offload_trigger_validate(st->offload_trigger, config); + if (ret) + return ret; + offload_offset_ns +=3D AD4030_TQUIET_CNV_DELAY_NS; + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); + + st->cnv_wf =3D cnv_wf; + + return 0; +} + +static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + /* + * We have no control over the sampling frequency without SPI offload + * triggering. + */ + if (!st->offload_trigger) + return -ENODEV; + + if (!in_range(freq, 1, st->chip->max_sample_rate_hz)) + return -EINVAL; + + guard(mutex)(&st->lock); + return __ad4030_set_sampling_freq(st, freq, st->avg_log2); +} + static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int gain_int, @@ -507,27 +642,6 @@ static int ad4030_set_chan_calibbias(struct iio_dev *i= ndio_dev, st->tx_data, AD4030_REG_OFFSET_BYTES_NB); } =20 -static int ad4030_set_avg_frame_len(struct iio_dev *dev, int avg_val) -{ - struct ad4030_state *st =3D iio_priv(dev); - unsigned int avg_log2 =3D ilog2(avg_val); - unsigned int last_avg_idx =3D ARRAY_SIZE(ad4030_average_modes) - 1; - int ret; - - if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) - return -EINVAL; - - ret =3D regmap_write(st->regmap, AD4030_REG_AVG, - AD4030_REG_AVG_MASK_AVG_SYNC | - FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2)); - if (ret) - return ret; - - st->avg_log2 =3D avg_log2; - - return 0; -} - static bool ad4030_is_common_byte_asked(struct ad4030_state *st, unsigned int mask) { @@ -536,11 +650,10 @@ static bool ad4030_is_common_byte_asked(struct ad4030= _state *st, AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK); } =20 -static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask) +static int ad4030_set_mode(struct ad4030_state *st, unsigned long mask, + unsigned int avg_log2) { - struct ad4030_state *st =3D iio_priv(indio_dev); - - if (st->avg_log2 > 0) { + if (avg_log2 > 0) { st->mode =3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF; } else if (ad4030_is_common_byte_asked(st, mask)) { switch (st->chip->precision_bits) { @@ -564,6 +677,50 @@ static int ad4030_set_mode(struct iio_dev *indio_dev, = unsigned long mask) st->mode); } =20 +static int ad4030_set_avg_frame_len(struct iio_dev *dev, unsigned long mas= k, int avg_val) +{ + struct ad4030_state *st =3D iio_priv(dev); + unsigned int avg_log2 =3D ilog2(avg_val); + unsigned int last_avg_idx =3D ARRAY_SIZE(ad4030_average_modes) - 1; + int freq; + int ret; + + if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) + return -EINVAL; + + guard(mutex)(&st->lock); + ret =3D ad4030_set_mode(st, mask, avg_log2); + if (ret) + return ret; + + if (st->offload_trigger) { + /* + * The sample averaging and sampling frequency configurations + * are mutually dependent one from another. That's because the + * effective data sample rate is fCNV / 2^N, where N is the + * number of samples being averaged. + * + * When SPI offload is supported and we have control over the + * sample rate, the conversion start signal (CNV) and the SPI + * offload trigger frequencies must be re-evaluated so data is + * fetched only after 'avg_val' conversions. + */ + ad4030_get_sampling_freq(st, &freq); + ret =3D __ad4030_set_sampling_freq(st, freq, avg_log2); + if (ret) + return ret; + } + + ret =3D regmap_write(st->regmap, AD4030_REG_AVG, + AD4030_REG_AVG_MASK_AVG_SYNC | + FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2)); + if (ret) + return ret; + + st->avg_log2 =3D avg_log2; + return 0; +} + /* * Descramble 2 32bits numbers out of a 64bits. The bits are interleaved: * 1 bit for first number, 1 bit for the second, and so on... @@ -672,7 +829,7 @@ static int ad4030_single_conversion(struct iio_dev *ind= io_dev, struct ad4030_state *st =3D iio_priv(indio_dev); int ret; =20 - ret =3D ad4030_set_mode(indio_dev, BIT(chan->scan_index)); + ret =3D ad4030_set_mode(st, BIT(chan->scan_index), st->avg_log2); if (ret) return ret; =20 @@ -769,6 +926,13 @@ static int ad4030_read_raw_dispatch(struct iio_dev *in= dio_dev, *val =3D BIT(st->avg_log2); return IIO_VAL_INT; =20 + case IIO_CHAN_INFO_SAMP_FREQ: + if (!st->offload_trigger) + return -ENODEV; + + ad4030_get_sampling_freq(st, val); + return IIO_VAL_INT; + default: return -EINVAL; } @@ -807,7 +971,10 @@ static int ad4030_write_raw_dispatch(struct iio_dev *i= ndio_dev, return ad4030_set_chan_calibbias(indio_dev, chan, val); =20 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - return ad4030_set_avg_frame_len(indio_dev, val); + return ad4030_set_avg_frame_len(indio_dev, BIT(chan->scan_index), val); + + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4030_set_sampling_freq(indio_dev, val); =20 default: return -EINVAL; @@ -869,7 +1036,9 @@ static int ad4030_get_current_scan_type(const struct i= io_dev *indio_dev, static int ad4030_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { - return ad4030_set_mode(indio_dev, *scan_mask); + struct ad4030_state *st =3D iio_priv(indio_dev); + + return ad4030_set_mode(st, *scan_mask, st->avg_log2); } =20 static const struct iio_info ad4030_iio_info =3D { @@ -898,6 +1067,88 @@ static const struct iio_buffer_setup_ops ad4030_buffe= r_setup_ops =3D { .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 +static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + u8 offload_bpw; + + if (st->mode =3D=3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) + offload_bpw =3D 32; + else + offload_bpw =3D st->chip->precision_bits; + + st->offload_xfer.speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED; + st->offload_xfer.bits_per_word =3D roundup_pow_of_two(offload_bpw); + st->offload_xfer.len =3D spi_bpw_to_bytes(offload_bpw); + st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); +} + +static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D regmap_write(st->regmap, AD4030_REG_EXIT_CFG_MODE, BIT(0)); + if (ret) + return ret; + + ad4030_prepare_offload_msg(indio_dev); + st->offload_msg.offload =3D st->offload; + ret =3D spi_optimize_message(st->spi, &st->offload_msg); + if (ret) + goto out_reset_mode; + + ret =3D pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, false); + if (ret) + goto out_unoptimize; + + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &st->offload_trigger_config); + if (ret) + goto out_pwm_disable; + + return 0; + +out_pwm_disable: + pwm_disable(st->cnv_trigger); +out_unoptimize: + spi_unoptimize_message(&st->offload_msg); +out_reset_mode: + /* reenter register configuration mode */ + ret =3D ad4030_enter_config_mode(st); + if (ret) + dev_err(&st->spi->dev, + "couldn't reenter register configuration mode\n"); + return ret; +} + +static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + pwm_disable(st->cnv_trigger); + + spi_unoptimize_message(&st->offload_msg); + + /* reenter register configuration mode */ + ret =3D ad4030_enter_config_mode(st); + if (ret) + dev_err(&st->spi->dev, + "couldn't reenter register configuration mode\n"); + + return ret; +} + +static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4030_offload_buffer_postenable, + .predisable =3D &ad4030_offload_buffer_predisable, + .validate_scan_mask =3D ad4030_validate_scan_mask, +}; + static int ad4030_regulators_get(struct ad4030_state *st) { struct device *dev =3D &st->spi->dev; @@ -967,6 +1218,24 @@ static int ad4030_detect_chip_info(const struct ad403= 0_state *st) return 0; } =20 +static int ad4030_pwm_get(struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + + st->cnv_trigger =3D devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnv_trigger)) + return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), + "Failed to get CNV PWM\n"); + + /* + * Preemptively disable the PWM, since we only want to enable it with + * the buffer. + */ + pwm_disable(st->cnv_trigger); + + return 0; +} + static int ad4030_config(struct ad4030_state *st) { int ret; @@ -994,6 +1263,31 @@ static int ad4030_config(struct ad4030_state *st) return 0; } =20 +static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct dma_chan *rx_dma; + + indio_dev->setup_ops =3D &ad4030_offload_buffer_setup_ops; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + + st->offload_trigger_config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1018,6 +1312,10 @@ static int ad4030_probe(struct spi_device *spi) if (!st->chip) return -EINVAL; =20 + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + ret =3D ad4030_regulators_get(st); if (ret) return ret; @@ -1045,24 +1343,57 @@ static int ad4030_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), "Failed to get cnv gpio\n"); =20 - /* - * One hardware channel is split in two software channels when using - * common byte mode. Add one more channel for the timestamp. - */ - indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; indio_dev->name =3D st->chip->name; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->info =3D &ad4030_iio_info; - indio_dev->channels =3D st->chip->channels; - indio_dev->available_scan_masks =3D st->chip->available_masks; =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - ad4030_trigger_handler, - &ad4030_buffer_setup_ops); - if (ret) - return dev_err_probe(dev, ret, - "Failed to setup triggered buffer\n"); + st->offload =3D devm_spi_offload_get(dev, spi, &ad4030_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "failed to get offload\n"); + + /* Fall back to low speed usage when no SPI offload is available. */ + if (ret =3D=3D -ENODEV) { + /* + * One hardware channel is split in two software channels when + * using common byte mode. Add one more channel for the timestamp. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; + indio_dev->channels =3D st->chip->channels; + indio_dev->available_scan_masks =3D st->chip->available_masks; + + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4030_trigger_handler, + &ad4030_buffer_setup_ops); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup triggered buffer\n"); + } else { + /* + * One hardware channel is split in two software channels when + * using common byte mode. Offloaded SPI transfers can't support + * software timestamp so no additional timestamp channel is added. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs; + indio_dev->channels =3D st->chip->offload_channels; + indio_dev->available_scan_masks =3D st->chip->available_masks; + ret =3D ad4030_spi_offload_setup(indio_dev, st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup SPI offload\n"); + + ret =3D ad4030_pwm_get(st); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to get PWM: %d\n", ret); + + ret =3D __ad4030_set_sampling_freq(st, st->chip->max_sample_rate_hz, + st->avg_log2); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to set offload samp freq\n"); + } =20 return devm_iio_device_register(dev, indio_dev); } @@ -1100,6 +1431,23 @@ static const struct iio_scan_type ad4030_24_scan_typ= es[] =3D { }, }; =20 +static const struct iio_scan_type ad4030_24_offload_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 24, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, +}; + static const struct iio_scan_type ad4030_16_scan_types[] =3D { [AD4030_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', @@ -1117,6 +1465,23 @@ static const struct iio_scan_type ad4030_16_scan_typ= es[] =3D { } }; =20 +static const struct iio_scan_type ad4030_16_offload_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 16, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, +}; + static const struct ad4030_chip_info ad4030_24_chip_info =3D { .name =3D "ad4030-24", .available_masks =3D ad4030_channel_masks, @@ -1125,10 +1490,15 @@ static const struct ad4030_chip_info ad4030_24_chip= _info =3D { AD4030_CHAN_CMO(1, 0), IIO_CHAN_SOFT_TIMESTAMP(2), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_CHAN_CMO(1, 0), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 1, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4630_16_chip_info =3D { @@ -1141,10 +1511,17 @@ static const struct ad4030_chip_info ad4630_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4630_24_chip_info =3D { @@ -1157,10 +1534,17 @@ static const struct ad4030_chip_info ad4630_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, }; =20 static const struct ad4030_chip_info ad4632_16_chip_info =3D { @@ -1173,10 +1557,17 @@ static const struct ad4030_chip_info ad4632_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 static const struct ad4030_chip_info ad4632_24_chip_info =3D { @@ -1189,10 +1580,17 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; 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charset="utf-8" ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a PGA (programmable gain amplifier) that scales the input signal prior to it reaching the ADC inputs. The PGA is controlled through a couple of pins (A0 and A1) that set one of four possible signal gain configurations. Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2 - Use pattern to specify devices that require gain related properties. - Disallow gain related properties for devices that don't come with embedde= d PGA. - Documented VDDH and VDD_FDA supplies for ADAQ4216 and ADAQ4224. - Updated PGA gain constants. .../bindings/iio/adc/adi,ad4030.yaml | 65 +++++++++++++++++-- 1 file changed, 60 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 564b6f67a96e..bd43c617ae11 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -19,6 +19,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4030-24-4032-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4216.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4224.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -31,6 +33,8 @@ properties: - adi,ad4630-24 - adi,ad4632-16 - adi,ad4632-24 + - adi,adaq4216 + - adi,adaq4224 =20 reg: maxItems: 1 @@ -54,6 +58,14 @@ properties: description: Internal buffered Reference. Used when ref-supply is not connected. =20 + vddh-supply: + description: + PGIA Positive Power Supply. + + vdd-fda-supply: + description: + FDA Positive Power Supply. + cnv-gpios: description: The Convert Input (CNV). It initiates the sampling conversions. @@ -64,6 +76,27 @@ properties: The Reset Input (/RST). Used for asynchronous device reset. maxItems: 1 =20 + pga-gpios: + description: + A0 and A1 pins for gain selection. For devices that have PGA configu= ration + input pins, pga-gpios should be defined if adi,gain-milli is absent. + minItems: 2 + maxItems: 2 + + adi,pga-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if PGA control inputs are pin-strapped. The values + specify the gain per mille. For example, 333 means the input signal = is + scaled by a 0.333 factor (i.e. attenuated to one third of it's origi= nal + magnitude). Possible values: + Gain 333 (A1=3D0, A0=3D0) + Gain 555 (A1=3D0, A0=3D1) + Gain 2222 (A1=3D1, A0=3D0) + Gain 6666 (A1=3D1, A0=3D1) + If defined, pga-gpios must be absent. + enum: [333, 555, 2222, 6666] + pwms: description: PWM signal connected to the CNV pin. maxItems: 1 @@ -86,11 +119,33 @@ required: - vio-supply - cnv-gpios =20 -oneOf: - - required: - - ref-supply - - required: - - refin-supply +allOf: + - oneOf: + - required: + - ref-supply + - required: + - refin-supply + # ADAQ devices require a gain property to indicate how hardware PGA is s= et + - if: + properties: + compatible: + contains: + pattern: ^adi,adaq + then: + allOf: + - required: [vddh-supply, vdd-fda-supply] + properties: + ref-supply: false + - oneOf: + - required: + - adi,pga-value + - required: + - pga-gpios + else: + properties: + adi,pga-value: false + pga-gpios: false + =20 unevaluatedProperties: false =20 --=20 2.50.1 From nobody Thu Oct 2 09:16:53 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB4631A7F6; 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The PGA is controlled through a pair of pins (A0 and A1) whose state define the gain that is applied to the input signal. Add support for ADAQ4216 and ADAQ4224. Provide a list of PGA options through the IIO device channel scale available interface and enable control of the PGA through the channel scale interface. Signed-off-by: Marcelo Schmitt --- Change log v1 -> v2 - Updated PGA gain constants. - Dropped redundant call to ad4030_set_pga_gain() on PGA GPIO setup. - Better state struct field placement to avoid holes in data. drivers/iio/adc/ad4030.c | 229 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 225 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 52805c779934..f5d369099f37 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -47,6 +47,8 @@ #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 +#define AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE 0x1E +#define AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE 0x1C #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -124,6 +126,10 @@ /* Datasheet says 9.8ns, so use the closest integer value */ #define AD4030_TQUIET_CNV_DELAY_NS 10 =20 +/* HARDWARE_GAIN */ +#define ADAQ4616_PGA_PINS 2 +#define ADAQ4616_PGA_GAIN_MAX_NANO (NANO * 2 / 3) + enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, AD4030_OUT_DATA_MD_16_DIFF_8_COM, @@ -144,6 +150,23 @@ enum { AD4030_SCAN_TYPE_AVG, }; =20 +/* + * Gains computed as fractions of 1000 so they can be expressed by integer= s. + */ +static const int ad4030_hw_gains[] =3D { + MILLI / 3, /* 333 */ + (5 * MILLI / 9), /* 555 */ + (20 * MILLI / 9), /* 2222 */ + (20 * MILLI / 3), /* 6666 */ +}; + +static const int ad4030_hw_gains_frac[][2] =3D { + { 1, 3 }, /* 1/3 gain */ + { 5, 9 }, /* 5/9 gain */ + { 20, 9 }, /* 20/9 gain */ + { 20, 3 }, /* 20/3 gain */ +}; + struct ad4030_chip_info { const char *name; const unsigned long *available_masks; @@ -151,6 +174,7 @@ struct ad4030_chip_info { const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; + bool has_pga; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; @@ -175,7 +199,11 @@ struct ad4030_state { struct spi_offload_trigger *offload_trigger; struct spi_offload_trigger_config offload_trigger_config; struct pwm_device *cnv_trigger; + size_t scale_avail_size; struct pwm_waveform cnv_wf; + unsigned int scale_avail[ARRAY_SIZE(ad4030_hw_gains)][2]; + struct gpio_descs *pga_gpios; + unsigned int pga_index; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -232,7 +260,7 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload, _pga) { \ .info_mask_shared_by_all =3D \ (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -243,6 +271,7 @@ struct ad4030_state { BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT(IIO_CHAN_INFO_RAW), \ .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + (_pga ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ BIT(IIO_CHAN_INFO_CALIBSCALE), \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -257,10 +286,16 @@ struct ad4030_state { } =20 #define AD4030_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 0) =20 #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 0) + +#define ADAQ4216_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 1) + +#define ADAQ4216_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 1) =20 static const int ad4030_average_modes[] =3D { BIT(0), /* No averaging/oversampling */ @@ -414,6 +449,65 @@ static const struct regmap_config ad4030_regmap_config= =3D { .max_register =3D AD4030_REG_DIG_ERR, }; =20 +static void ad4030_fill_scale_avail(struct ad4030_state *st) +{ + unsigned int mag_bits, int_part, fract_part, i; + u64 range; + + /* + * The maximum precision of differential channels is retrieved from the + * chip properties. The output code of differential channels is in two's + * complement format (i.e. signed), so the MSB is the sign bit and only + * (precision_bits - 1) bits express voltage magnitude. + */ + mag_bits =3D st->chip->precision_bits - 1; + + for (i =3D 0; i < ARRAY_SIZE(ad4030_hw_gains); i++) { + range =3D mult_frac(st->vref_uv, ad4030_hw_gains_frac[i][1], + ad4030_hw_gains_frac[i][0]); + /* + * If range were in mV, we would multiply it by NANO below. + * Though, range is in =C2=B5V so multiply it by MICRO only so the + * result after right shift and division scales output codes to + * millivolts. + */ + int_part =3D div_u64_rem(((u64)range * MICRO) >> mag_bits, NANO, &fract_= part); + st->scale_avail[i][0] =3D int_part; + st->scale_avail[i][1] =3D fract_part; + } +} + +static int ad4030_set_pga_gain(struct ad4030_state *st) +{ + DECLARE_BITMAP(bitmap, ADAQ4616_PGA_PINS) =3D { }; + + bitmap_write(bitmap, st->pga_index, 0, ADAQ4616_PGA_PINS); + + return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); +} + +static int ad4030_set_pga(struct iio_dev *indio_dev, int gain_int, int gai= n_fract) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + unsigned int mag_bits =3D st->chip->precision_bits - 1; + u64 gain_nano, tmp; + + if (!st->pga_gpios) + return -EINVAL; + + gain_nano =3D gain_int * NANO + gain_fract; + + if (!in_range(gain_nano, 1, ADAQ4616_PGA_GAIN_MAX_NANO)) + return -EINVAL; + + tmp =3D DIV_ROUND_CLOSEST_ULL(gain_nano << mag_bits, NANO); + gain_nano =3D DIV_ROUND_CLOSEST_ULL(st->vref_uv, tmp); + st->pga_index =3D find_closest(gain_nano, ad4030_hw_gains, + ARRAY_SIZE(ad4030_hw_gains)); + + return ad4030_set_pga_gain(st); +} + static int ad4030_get_chan_scale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -433,7 +527,14 @@ static int ad4030_get_chan_scale(struct iio_dev *indio= _dev, =20 *val2 =3D scan_type->realbits; =20 - return IIO_VAL_FRACTIONAL_LOG2; + /* The LSB of the 8-bit common-mode data is always vref/256. */ + if (scan_type->realbits =3D=3D 8 || !st->chip->has_pga) + return IIO_VAL_FRACTIONAL_LOG2; + + *val =3D st->scale_avail[st->pga_index][0]; + *val2 =3D st->scale_avail[st->pga_index][1]; + + return IIO_VAL_INT_PLUS_NANO; } =20 static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev, @@ -901,6 +1002,15 @@ static int ad4030_read_avail(struct iio_dev *indio_de= v, *length =3D ARRAY_SIZE(ad4030_average_modes); return IIO_AVAIL_LIST; =20 + case IIO_CHAN_INFO_SCALE: + if (st->scale_avail_size =3D=3D 1) + *vals =3D (int *)st->scale_avail[st->pga_index]; + else + *vals =3D (int *)st->scale_avail; + *length =3D st->scale_avail_size * 2; /* print int and nano part */ + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_LIST; + default: return -EINVAL; } @@ -976,6 +1086,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *i= ndio_dev, case IIO_CHAN_INFO_SAMP_FREQ: return ad4030_set_sampling_freq(indio_dev, val); =20 + case IIO_CHAN_INFO_SCALE: + return ad4030_set_pga(indio_dev, val, val2); + default: return -EINVAL; } @@ -997,6 +1110,17 @@ static int ad4030_write_raw(struct iio_dev *indio_dev, return ret; } =20 +static int ad4030_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } +} + static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { @@ -1045,6 +1169,7 @@ static const struct iio_info ad4030_iio_info =3D { .read_avail =3D ad4030_read_avail, .read_raw =3D ad4030_read_raw, .write_raw =3D ad4030_write_raw, + .write_raw_get_fmt =3D &ad4030_write_raw_get_fmt, .debugfs_reg_access =3D ad4030_reg_access, .read_label =3D ad4030_read_label, .get_current_scan_type =3D ad4030_get_current_scan_type, @@ -1288,6 +1413,50 @@ static int ad4030_spi_offload_setup(struct iio_dev *= indio_dev, IIO_BUFFER_DIRECTION_IN); } =20 +static int ad4030_setup_pga(struct device *dev, struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + unsigned int i; + int pga_value; + int ret; + + ret =3D device_property_read_u32(dev, "adi,pga-value", &pga_value); + if (ret =3D=3D -EINVAL) { + /* Setup GPIOs for PGA control */ + st->pga_gpios =3D devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); + if (IS_ERR(st->pga_gpios)) + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), + "Failed to get PGA gpios.\n"); + + if (st->pga_gpios->ndescs !=3D ADAQ4616_PGA_PINS) + return dev_err_probe(dev, -EINVAL, + "Expected 2 GPIOs for PGA control.\n"); + + st->scale_avail_size =3D ARRAY_SIZE(ad4030_hw_gains); + st->pga_index =3D 0; + return 0; + } else if (ret !=3D 0) { + return dev_err_probe(dev, ret, "Failed to get PGA value.\n"); + } + + /* Set ADC driver to handle pin-strapped PGA pins setup */ + for (i =3D 0; i < ARRAY_SIZE(ad4030_hw_gains); i++) { + if (pga_value !=3D ad4030_hw_gains[i]) + continue; + + st->pga_index =3D i; + break; + } + if (i =3D=3D ARRAY_SIZE(ad4030_hw_gains)) + return dev_err_probe(dev, -EINVAL, "Invalid PGA value: %d.\n", + pga_value); + + st->scale_avail_size =3D 1; + st->pga_gpios =3D NULL; + + return 0; +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1334,6 +1503,14 @@ static int ad4030_probe(struct spi_device *spi) if (ret) return ret; =20 + if (st->chip->has_pga) { + ret =3D ad4030_setup_pga(dev, indio_dev, st); + if (ret) + return ret; + + ad4030_fill_scale_avail(st); + } + ret =3D ad4030_config(st); if (ret) return ret; @@ -1593,12 +1770,54 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { .max_sample_rate_hz =3D 500 * HZ_PER_KHZ, }; =20 +static const struct ad4030_chip_info adaq4216_chip_info =3D { + .name =3D "adaq4216", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), + AD4030_CHAN_CMO(1, 0), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, + .precision_bits =3D 16, + .has_pga =3D true, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, +}; + +static const struct ad4030_chip_info adaq4224_chip_info =3D { + .name =3D "adaq4224", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), + AD4030_CHAN_CMO(1, 0), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, + .precision_bits =3D 24, + .has_pga =3D true, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * HZ_PER_MHZ, +}; + static const struct spi_device_id ad4030_id_table[] =3D { { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, + { "adaq4216", (kernel_ulong_t)&adaq4216_chip_info }, + { "adaq4224", (kernel_ulong_t)&adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4030_id_table); @@ -1609,6 +1828,8 @@ static const struct of_device_id ad4030_of_match[] = =3D { { .compatible =3D "adi,ad4630-24", .data =3D &ad4630_24_chip_info }, { .compatible =3D "adi,ad4632-16", .data =3D &ad4632_16_chip_info }, { .compatible =3D "adi,ad4632-24", .data =3D &ad4632_24_chip_info }, + { .compatible =3D "adi,adaq4216", .data =3D &adaq4216_chip_info }, + { .compatible =3D "adi,adaq4224", .data =3D &adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4030_of_match); --=20 2.50.1